2096E

2096E LATTICE | Alldatasheet

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Technical content

Features

• SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional/JEDEC Upward Compatible with ispLSI 2096 Devices
• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay — TTL Compatible Inputs and Outputs — 5V Programmable Logic Core — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems — PCI Compatible Outputs — Open-Drain Output Option — Electrically Erasable and Reprogrammable — Non-Volatile — Unused Product Term Shutdown Saves Power
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com November 1998

Description

The ispLSI 2096E is a High Density Programmable Logic Device. The device contains 96 Registers, 96 Universal I/O pins, six Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2096E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2096E offers non-volatile reprogrammability of all logic, as well as the interconnect to provide truly reconfigurable sys- tems. The basic unit of logic on the ispLSI 2096E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. C7 (see Figure 1). There are a total of 24 GLBs in the ispLSI 2096E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 96 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, output or bi- directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be pro- grammed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting Global Routing Pool (GRP) Output Routing Pool (ORP) Output Routing Pool (ORP) 0919/2096E C 7 C 4C 5C 6 A4 A7A6A5 GLB Logic Array DQ DQ DQ DQ Output Routing Pool (ORP) Output Routing Pool (ORP) C 3 C 0C 1C 2 B0 B3B2B1 Output Routing Pool (ORP) Output Routing Pool (ORP)

Specifications ispLSI 2096E Absolute Maximum Ratings 1 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition Capacitance (TA =25°C, f=1.0 MHz) Erase/Reprogram Specification TA = 0°C to +70°C SYMBOL Table 2-0005/2096E VCC VIH VIL PARAMETER Supply Voltage: Logic Core, Input Buffers Input High Voltage Input Low Voltage MIN. MAX. UNITS 4.75 2.0 5.25 Vcc+1 0.8 V VCCIO Supply Voltage: Output Drivers 4.75 5.25 V 3.3V 3.0 3.6 V V V C SYMBOL Table 2-0006/2096E C PARAMETER I/O Capacitance UNITS TEST CONDITIONS Dedicated Input Capacitance pf pf V = 5.0V, V = 2.0V V = 5.0V, V = 2.0VCC CC I/O IN C Clock Capacitance TYP 103 pf V = 5.0V, V = 2.0VCC Y Table 2-0008/2096E PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 10,000 – Cycles

Figure 2. Test Load *C L includes Test Fixture and Probe Capacitance.

1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.

1. Meaured using six 16-bit counters.
2. Unused inputs held at 0.0V.

Specifications ispLSI 2096E tpd1 UNITS -180 MIN. TEST COND. 1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030A/2096E tsu2 + tco1( ) -135 MIN.MAX. MAX.DESCRIPTION#2 4PARAMETER A 1 Data Prop Delay, 4PT Bypass, ORP Bypass – 5.0 – 7.5 ns tpd2 A 2 Data Prop Delay –– ns fmax A 3 Clk Freq with Internal Feedback3 180 – 135 – MHz fmax (Ext.) – 4 Clk Freq with External Feedback –– MHz fmax (Tog.) – 5 Clk Frequency, Max. Toggle –– MHz tsu1 – 6 GLB Reg Setup Time before Clk, 4 PT Bypass –– ns tco1 A 7 GLB Reg Clk to Output Delay, ORP Bypass –– ns th1 – 8 GLB Reg Hold Time after Clk, 4 PT Bypass 0.0 – ns tsu2 – 9 GLB Reg Setup Time before Clk 5.0 – ns tco2 – 10 GLB Reg Clk to Output Delay –– ns th2 – 11 GLB Reg Hold Time after Clk 0.0 – ns tr1 A 12 External Reset Pin to Output Delay –– ns trw1 – 13 External Reset Pulse Duration 4.0 – ns tptoeen B 14 Input to Output Enable –– ns tptoedis C 15 Input to Output Disable –– ns tgoeen B 16 Global OE Output Enable –– ns tgoedis C 17 Global OE Output Disable –– ns twh – 18 External Synch Clk Pulse Duration, High 2.5 –– ns twl – 19 External Synch Clk Pulse Duration, Low 2.5 –– ns 125 200 4.0 3.0 3.5 7.0 10.0 10.0 5.0 5.0 7.5 100 143 5.0 0.0 6.0 0.0 5.0 3.5 3.5 10.0 4.0 4.5 10.0 12.0 12.0 7.0 7.0 -100 MIN. MAX. – 10.0 100 – 0.0 8.0 0.0 6.5 5.0 – 5.0 – 100 6.5 5.0 6.0 13.5 15.0 15.0 9.0 9.0 13.0 External Timing Parameters Over Recommended Operating Conditions

Specifications ispLSI 2096E Internal Timing Parameters1 Over Recommended Operating Conditions tio 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036A/2096E Inputs UNITS -135 MIN. MAX.DESCRIPTION#2PARAMETER 20 Input Buffer Delay – 0.5 ns tdin 21 Dedicated Input Delay – 1.7 ns tgrp 22 GRP Delay – 1.2 ns GLB t1ptxor 25 1 Product Term/XOR Path Delay – 5.2 ns t20ptxor 26 20 Product Term/XOR Path Delay – 5.2 ns txoradj 27 XOR Adjacent Path Delay – 5.2 ns tgbp 28 GLB Register Bypass Delay – 0.5 ns tgsu 29 GLB Register Setup Time before Clock 0.7 – ns tgh 30 GLB Register Hold Time after Clock 4.3 – ns tgco 31 GLB Register Clock to Output Delay – 0.3 ns tgro 32 GLB Register Reset to Output Delay – 1.1 ns tptre 33 GLB Product Term Reset to Register Delay – 6.0 ns tptoe 34 GLB Product Term Output Enable to I/O Cell Delay – 6.9 ns tptck 35 GLB Product Term Clock Delay 2.5 5.5 ns ORP tob 38 Output Buffer Delay – 1.6 ns tsl 39 Output Slew Limited Delay Adder – 1.5 ns GRP t4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial) – 3.7 ns t4ptbpr 24 4 Product Term Bypass Path Delay (Registered) – 4.2 ns torp 36 ORP Delay – 1.0 ns torpbp 37 ORP Bypass Delay – 0.5 ns Outputs toen 40 I/O Cell OE to Output Enabled – 3.4 ns todis 41 I/O Cell OE to Output Disabled – 3.4 ns tgoe 42 Global Output Enable – 3.6 ns tgy0 43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 1.6 1.6 ns tgy1/2 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 1.8 1.8 ns Clocks tgr 45 Global Reset to GLB – 6.3 ns Global Reset -180 MIN. MAX. 0.5 1.1 0.6 3.9 3.9 3.9 0.0 1.9 2.9 0.7 3.3 0.3 0.6 4.8 5.9 1.0 4.0 0.9 0.4 1.6 1.5 3.0 3.0 – 2.0 0.7 0.9 0.7 0.9 – 4.4 -100 MIN. MAX. 0.5 2.2 1.7 6.8 7.3 8.0 0.5 5.8 5.8 1.2 4.0 0.3 1.3 6.1 8.6 4.1 7.1 1.4 0.4 1.6 1.0 4.2 4.2 – 4.8 2.7 2.7 2.7 2.7 – 9.2

Specifications ispLSI 2096E ispLSI 2096E Timing Model Note: Calculations are based upon timing specifications for the ispLSI 2096E-180L. Derivations of tsu, th and tco from the Product Term Clock tsu Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) th Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) tco Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) Table 2-0042/2096E 3.6 3.4 7.9 GLB Reg Delay I/O Pin (Output) ORP Delay Feedback Reg 4 PT Bypass 20 PT XOR Delays Control PTs I/O Pin (Input) Y0,1,2 GRP GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Delay I/O CellORPGLBGRPI/O Cell #24 #25 - 27 #33 - 35 #43, 44 #36 Reset Ded. In #21 #20 #28 #29 - 32 GOE0, 1 #42 #40, 41 0491/2096E #22 Comb 4 PT Bypass #23 #37 #45 #38, #39

Specifications ispLSI 2096E Pin Description Input - This pin performs two functions. When BSCAN is logic low, it functions as a pin to control the operation of the isp state machine. When BSCAN is high, it functions as a dedicated input pin. 1. Pins have dual function capability. Input/Output Pins - These are the general purpose I/O pins used by the logic array. NAME Table 2-0002/2096E PQFP & TQFP PIN NUMBERS DESCRIPTION 21, 27, 34, 40, 52, 58, 66, 72, 85, 91, 98, 104, 117, 123, 22, 28, 35, 41, 53, 59, 67, 73, 86, 92, 99, 105, 118, 124, 64, 114 23, 29, 36, 42, 54, 60, 68, 74, 87, 93, 100, 106, 119, 125, 10, 110 I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 24, 30, 37, 43, 55, 61, 69, 75, 88, 94, 101, 107, 120, 126, 11, 25, 31, 38, 44, 56, 62, 70, 76, 89, 95, 102, 108, 121, 127, 12, 103 109 122 128 97, 17, 112, 33, 115, 49, 116 16, 48, 82, 113 65, 81, Global Output Enables input pins.GOE 0, GOE 1 GND VCCVCC Ground (GND) Input - This pin performs two functions. When BSCAN is logic low, it functions as an input pin to load programming data into the device. TDI/IN0 also is used as one of the two control pins for the isp state machine. When BSCAN is high, it functions as a dedicated input pin. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK options become active. RESET Y0, Y1, Y2 TDI/IN 0 BSCAN TMS/IN 11 51, 84, 8083, Dedicated input pins to the device.IN 2, IN 4, IN 5 Output - When BSCAN is logic low, it functions as an output pin to read serial shift register data. TDO 1 Input - This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Serial Shift Register. When BSCAN is high, it functions as a dedicated input pin. TCK/IN 31 14, 47, 79, 111 Supply voltage for output drivers, 5V or 3.3V. All VCCIO pins must be connected to the same voltage level VCCIO

Specifications ispLSI 2096E Pin Configuration ispLSI 2096E 128-pin PQFP and TQFP Pinout Diagram I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 VCCIO VCC GND BSCAN RESET I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 GND I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 4 VCC GND TCK/IN 3 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 GND GND VCC VCCIO IN 5 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 1TMS/IN 1 VCC GND TDO IN 2 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 ispLSI 2096E Top View I/O 10 1TDI/IN 0 I/O 59 GND VCCIO GND GND VCCIO 128 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 9764 122 GOE 0 GOE 1 1. Pins have dual function capability. 0124/2096E

Specifications ispLSI 2096E Part Number Description ispLSI 2096E Ordering Information Table 2-0041/2096E FAMILY fmax (MHz) 180 135 ORDERING NUMBER PACKAGE 128-Pin TQFP 128-Pin TQFP tpd (ns) 5.0 7.5 ispLSI ispLSI 2096E-180LT128 180 128-Pin PQFP5.0 ispLSI 2096E-180LQ128 ispLSI 2096E-135LT128 135 128-Pin PQFP7.5 ispLSI 2096E-135LQ128 100 128-Pin TQFP10.0 ispLSI 2096E-100LT128 100 128-Pin PQFP10.0 ispLSI 2096E-100LQ128 Device Number ispLSI2096E XXX X XXXX Grade Blank = Commercial X Speed 180 = 180 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax Power L = Low Package T128 = TQFP Q128 = PQFP Device Family 0212/2096E