160V

160V LATTICE | Alldatasheet

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Technical content

3.3V Generic Digital Crosspoint TM Functional Block DiagramFeatures

• IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation — Space-Saving PQFP and BGA Packaging — Dedicated IEEE 1149.1-Compliant Boundary Scan Test
• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — 3.3V Core Power Supply — 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay* — 250MHz Maximum Clock Frequency* — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable)* — Low-Power: 16.5mA Quiescent Icc* — 24mA I OL Drive with Programmable Slew Rate Control Option — PCI Compatible Drive Capability* — Schmitt Trigger Inputs for Noise Immunity — Electrically Erasable and Reprogrammable — Non-Volatile E 2CMOS Technology
• ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES — 3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP) — Change Interconnects in Seconds
• FLEXIBLE ARCHITECTURE — Combinatorial/Latched/Registered Inputs or Outputs — Individual I/O Tri-state Control with Polarity Control — Dedicated Clock/Clock Enable Input Pins (four) or Programmable Clocks/Clock Enables from I/O Pins (40) — Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns) — Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX — Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins — Outputs Tri-state During Power-up (“Live Insertion” Friendly)
• DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE — MS Windows or NT / PC-Based or Sun O/S — Easy Text-Based Design Entry — Automatic Signal Routing — Program up to 100 ISP Devices Concurrently — Simulator Netlist Generation for Easy Board-Level Simulation * “VA” Version Only Global Routing Pool (GRP) I/O Cells I/O Pins B Boundary Scan Control I/O Cells ISP Control I/O Pins A I/O Pins C I/O Pins D

Description

The ispGDXV/VA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface require- ments including:

• Multi-Port Multiprocessor Interfaces
• Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX)
• Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.)
• Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Rout- ing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs gdx160va_04 Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

can be driven directly from selected sets of I/O pins. for the Vcc and I/O pins must still be met. Table 1. ispGDXV Family Members CLKEN3 respectively in all devices.

test is supported by dedicated registers at each I/O pin. standard Boundary Scan protocol. together with one group per side. and MUX1 can be driven from either MUXsel1 or MUXsel2. Figure 1. ispGDXV/VA I/O Cell and GRP Detail (160 I/O Device)

80 I/O Cells

160 Input GRP

160 I/O Inputs

programmed as active high or active low.

00 M 0

01 M 1

11 M 2

10 M 3

cells as well as their relationship to direct MUX inputs. extrapolated from the pattern shown in the table. Figure 2. I/O Hemisphere Configuration of

Table 2. Adjacent I/O Cells (Mapping of Figure 3. Adjacent I/O Cells vs. Direct Input Path for need for an off-chip Open-Drain or Open-Collector buffer. resistor value for the pull-up ranges from 50kΩ to 80kΩ . fanout delays and has PCI compatible drive capability.

Specifications ispGDX160V/VA The ispGDXV/VA Family architecture has been devel- oped to deliver an in-system programmable signal routing solution with high speed and high flexibility. The devices are targeted for three similar but distinct classes of end- system applications: Programmable, Random Signal Interconnect (PRSI) This class includes PCB-level programmable signal rout- ing and may be used to provide arbitrary signal swapping between chips. It opens up the possibilities of program- mable system hardware. It is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control in- puts. Programmable Data Path (PDP) This application area includes system data path trans- ceiver, MUX and latch functions. With today’s 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, PCBs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. Many of these applications consist of “on-board” bus and memory inter- faces that do not require the very high drive of standard glue functions but can benefit from higher integration. Therefore, there is a need for a flexible means to inte- grate these on-board data path functions in an analogous way to programmable logic’s solution to control logic integration. Lattice’s CPLDs make an ideal control logic complement to the ispGDXV/VA in-system program- mable data path devices as shown below. Data Path Bus #1 Control Inputs (from P) Address Inputs (from P) Control Outputs System Clock(s) Data Path Bus #2 Configuration (Switch) Outputs ISP/JTAG Interface ispLSI/ ispMACH Device ispGDXV/VA Device Buffers / RegistersDecoders Buffers / RegistersState Machines Figure 4. ispGDXV/VA Complements Lattice CPLDs

Applications

Programmable Switch Replacement (PSR) Includes solid-state replacement and integration of me- chanical DIP Switch and jumper functions. Through in-system programming, pins of the ispGDXV/VA de- vices can be driven to HIGH or LOW logic levels to emulate the traditional device outputs. PSR functions do not require any input pin connections. These applications actually require somewhat different silicon features. PRSI functions require that the device support arbitrary signal routing on-chip between any two pins with no routing restrictions. The routing connections are static (determined at programming time) and each input-to-output path operates independently. As a result, there is little need for dynamic signal controls (OE, clocks, etc.). Because the ispGDXV/VA device will inter- face with control logic outputs from other components (such as ispLSI or ispMACH) on the board (which fre- quently change late in the design process as control logic is finalized), there must be no restrictions on pin-to-pin signal routing for this type of application. PDP functions, on the other hand, require the ability to dynamically switch signal routing (MUXing) as well as latch and tri-state output signals. As a result, the pro- grammable interconnect is used to define possible signal routes that are then selected dynamically by control signals from an external MPU or control logic. These functions are usually formulated early in the conceptual design of a product. The data path requirements are driven by the microprocessor, bus and memory architec- ture defined for the system. This part of the design is the earliest portion of the system design frozen, and will not usually change late in the design because the result would be total system and PCB redesign. As a result, the ability to accommodate arbitrary any pin-to-any pin re- routing is not a strong requirement as long as the designer has the ability to define his functions with a reasonable degree of freedom initially. As a result, the ispGDXV/VA architecture has been defined to support PSR and PRSI applications (including bidirectional paths) with no restrictions, while PDP appli- cations (using dynamic MUXing) are supported with a minimal number of restrictions as described below. In this way, speed and cost can be optimized and the devices can still support the system designer’s needs. The following diagrams illustrate several ispGDXV/VA applications.

Specifications ispGDX160VA Absolute Maximum Ratings 1,2 Max. Junction Temp. (T J) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Conditions C SYMBOL Table 2-0006/gdx160va C PARAMETER PACKAGE TYPE Dedicated Clock Capacitance 8 UNITSTYPICAL TEST CONDITIONS 7PQFP BGA, fpBGA PQFP BGA, fpBGA I/O Capacitance pf 10 pf pf 10 pf V = 3.3V, V = 2.0V V = 3.3V, V = 2.0VCC CC Y I/O Capacitance (TA =25oC, f=1.0 MHz) PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 10,000 — Cycles Erase/Reprogram Specifications SYMBOL Table 2-0005/gdx160va VCC VCCIO PARAMETER Supply Voltage I/O Reference Voltage Commercial TA = 0°C to +70°C MIN. MAX. UNITS 3.00 2.3 3.60 3.60 V Industrial TA = -40°C to +85°C 3.00 3.60 V V

3-state levels are measured 0.5V from steady-state active level. Figure 8. Test Load *C L includes Test Fixture and Probe Capacitance.

1. I/O voltage configuration must be set to VCC. Table 2-0007/gdx160va

Specifications ispGDX160VA Over Recommended Operating Conditions VIH SYMBOL 2.5V/gdx160va VOH PARAMETER Input High Voltage Output High Voltage VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX) VOH(MIN) ≤ VOUT or VOUT ≤ VOL(MAX) VCCIO=MIN , IOH = -8mA VCCIO=MIN , IOL = 8mA CONDITION MIN. TYP. MAX. UNITS 1.7 1.8 5.25 V VCCIO VIL I/O Reference Voltage Input Low Voltage 2.3 -0.3 2.7 0.7 V V V VCCIO=MIN , IOH = -100µA 2.1 –– V –– 0.6 V VCCIO=MIN , IOL = 100µA –– 0.2 V VOL Output Low Voltage 1. I/O voltage configuration must be set to VCCIO. Over Recommended Operating Conditions SYMBOL 1. One output at a time for a maximum of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized, but not 100% tested. 2. Typical values are at VCC = 3.3V and TA = 25°C. 3. ICC / MHz = (0.003 x I/O cell fanout) + 0.029. 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. DC Char_gdx160va IPU IBHLS PARAMETER I/O Active Pullup Current Bus Hold Low Sustaining Current IIH IIL Input or I/O High Leakage Current Input or I/O Low Leakage Current 0V ≤ VIN ≤ VIL (MAX) CONDITION MIN. TYP. 2 MAX. UNITS -10 -200 µAIBHT Bus Hold Trip Points VIL – VIH V µA µA µA 40 –– µA (VCCIO -0.2) ≤ VIN ≤ VCCIO VCCIO ≤ VIN ≤ 5.25V 0V ≤ VIN ≤ VIL (MAX) IOS 1 Output Short Circuit Current –– -250 mAVCC = 3.3V, VOUT = 0.5V, TA = 25°C ICCQ 4 Quiescent Power Supply Current – 16.5 – mAVIL = 0.5V, VIH = VCC VIN = VIL (MAX) IBHHS Bus Hold High Sustaining Current -40 –– µAVIN = VIH (MIN) IBHLO Bus Hold Low Overdrive Current –– 550 µA0V ≤ VIN ≤ VCCIO ICC Dynamic Power Supply Current per Input Switching One input toggling at 50% duty cycle, outputs open. – See Note 3 – mA/ MHz ICONT 5 Maximum Continuous I/O Pin Sink Current Through Any GND Pin – –– 160 mA IBHHO Bus Hold High Overdrive Current –– -550 µA0V ≤ VIN ≤ VCCIO

Specifications ispGDX160VA 5.0 5.0 5.0 8.5 6.0 9.5 6.0 6.0 6.0 6.0 14.0 5.0 0.5 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX) Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) Clock Frequency, Max. Toggle Clock Frequency with External Feedback Input Latch or Register Setup Time Before Y x Input Latch or Register Setup Time Before I/O Clock Output Latch or Register Setup Time Before Y x Output Latch or Register Setup Time Before I/O Clock Global Clock Enable Setup Time Before Y x Global Clock Enable Setup Time Before I/O Clock I/O Clock Enable Setup Time Before Y x Input Latch or Reg. Hold Time (Yx) Input Latch or Reg. Hold Time (I/O Clock) Output Latch or Reg. Hold Time (Y Output Latch or Reg. Hold Time (I/O Clock) Global Clock Enable Hold Time (Y Global Clock Enable Hold Time (I/O Clock) I/O Clock Enable Hold Time (Y Output Latch or Reg. Clock (from Yx) to Output Delay Input Latch or Register Clock (from Yx) to Output Delay Output Latch or Register Clock (from I/O pin) to Output Delay Input Latch or Register Clock (from I/O pin) to Output Delay Input to Output Enable Input to Output Disable Test OE Output Enable Test OE Output Disable Clock Pulse Duration, High Clock Pulse Duration, Low Register Reset Delay from RESET Low Reset Pulse Width Output Delay Adder for Output Timings Using Slow Slew Rate Output Skew (tgco1 Across Chip) External Timing Parameters Over Recommended Operating Conditions ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 143 111 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 3.5 3.5 10.0 A A A A A A B C B C D A tpd2 tsel2 fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco12 tgco22 tco12 tco22 ten2 tdis2 ttoeen2 ttoedis2 twh twl trst trw tsl tsk DESCRIPTIONPARAMETER ( )1 tsu3+tgco1 UNITS-5 MIN. MAX. 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. 3.5 3.5 3.5 6.0 4.0 7.0 5.0 5.0 6.0 6.0 8.0 3.5 0.5 250 166.7 3.0 2.5 2.5 2.0 2.5 1.5 3.0 0.0 0.5 0.0 1.0 0.0 1.0 0.0 2.0 2.0 5.0 MIN. MAX. TEST1 COND.

Specifications ispGDX160VA 9.0 9.0 9.0 13.5 11.5 15.7 10.5 10.5 10.5 10.5 22.0 9.0 1.0 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX) Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) Clock Frequency, Max. Toggle Clock Frequency with External Feedback Input Latch or Register Setup Time Before Y x Input Latch or Register Setup Time Before I/O Clock Output Latch or Register Setup Time Before Y x Output Latch or Register Setup Time Before I/O Clock Global Clock Enable Setup Time Before Y x Global Clock Enable Setup Time Before I/O Clock I/O Clock Enable Setup Time Before Y x Input Latch or Reg. Hold Time (Yx) Input Latch or Reg. Hold Time (I/O Clock) Output Latch or Reg. Hold Time (Y Output Latch or Reg. Hold Time (I/O Clock) Global Clock Enable Hold Time (Y Global Clock Enable Hold Time (I/O Clock) I/O Clock Enable Hold Time (Y Output Latch or Reg. Clock (from Yx) to Output Delay Input Latch or Register Clock (from Yx) to Output Delay Output Latch or Register Clock (from I/O pin) to Output Delay Input Latch or Register Clock (from I/O pin) to Output Delay Input to Output Enable Input to Output Disable Test OE Output Enable Test OE Output Disable Clock Pulse Duration, High Clock Pulse Duration, Low Register Reset Delay from RESET Low Reset Pulse Width Output Delay Adder for Output Timings Using Slow Slew Rate Output Skew (tgco1 Across Chip) External Timing Parameters Over Recommended Operating Conditions ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 62.5 7.0 6.0 7.0 6.0 4.0 3.0 8.5 0.0 3.0 0.0 3.0 0.0 3.0 0.0 6.0 6.0 18.0 A A A A A A B C B C D A tpd2 tsel2 fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco12 tgco22 tco12 tco22 ten2 tdis2 ttoeen2 ttoedis2 twh twl trst trw tsl tsk DESCRIPTIONPARAMETER ( )1 tsu3+tgco1 UNITS-9 MIN. MAX. 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. MIN. MAX. TEST1 COND. 100 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 5.0 5.0 14.0 7.0 7.0 7.0 11.0 9.0 13.0 8.5 8.5 8.5 8.5 18.0 7.0 0.5

Specifications ispGDX160VA External Timing Parameters (Continued) 1.0 0.0 0 4 10 20 30 40 50 60 70 0.2 0.4 0.6 0.8 1.2 1.4 1.6 ∆ GRP Delay (ns) I/O Cell Fanout ispGDX160VA Maximum ∆ GRP Delay vs. I/O Cell Fanout ispGDX160VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder.

Specifications ispGDX160VA -3 -5 PARAMETER # DESCRIPTION 1 MIN. MAX. MIN. MAX. UNITS Inputs tio 32 Input Buffer Delay — 0.4 — 0.9 ns GRP tgrp 33 GRP Delay — 1.1 — 1.1 ns MUX tmuxd 34 I/O Cell MUX A/B/C/D Data Delay — 1.0 — 1.5 ns tmuxexp 35 I/O Cell MUX A/B/C/D Expander Delay — 1.5 — 2.0 ns tmuxs 36 I/O Cell Data Select — 1.0 — 1.5 ns tmuxsio 37 I/O Cell Data Select (I/O Clock) — 1.5 — 3.0 ns tmuxsg 38 I/O Cell Data Select (Yx Clock) — 1.5 — 2.0 ns tmuxselexp 39 I/O Cell MUX Data Select Expander Delay — 1.5 — 2.0 ns Register tiolat 40 I/O Latch Delay — 1.0 — 1.0 ns tiosu 41 I/O Register Setup Time Before Clock — 0.8 — 2.0 ns tioh 42 I/O Register Hold Time After Clock — 1.7 — 1.5 ns tioco 43 I/O Register Clock to Output Delay — 1.2 — 0.5 ns tior 44 I/O Reset to Output Delay — 1.0 — 1.5 ns tcesu 45 I/O Clock Enable Setup Time Before Clock — 2.3 — 2.0 ns tceh 46 I/O Clock Enable Hold Time After Clock — 0.2 — 0.5 ns Data Path tfdbk 47 I/O Register Feedback Delay — 0.6 — 0.9 ns tiobp 48 I/O Register Bypass Delay — 0.0 — 0.0 ns tioob 49 I/O Register Output Buffer Delay — 0.0 — 0.0 ns tmuxcg 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 1.5 — 2.0 ns tmuxcio 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 1.5 — 3.0 ns tiodg 52 I/O Register I/O MUX Delay (Yx Clock) — 3.5 — 4.0 ns tiodio 53 I/O Register I/O MUX Delay (I/O Clock) — 3.5 — 5.0 ns Outputs tob 54 Output Buffer Delay — 1.0 — 1.5 ns tobs 55 Output Buffer Delay (Slow Slew Option) — 4.5 — 6.5 ns toeen 56 I/O Cell OE to Output Enable — 3.5 — 4.0 ns toedis 57 I/O Cell OE to Output Disable — 3.5 — 4.0 ns tgoe 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns ttoe 59 Test OE Enable and Disable Delay — 2.5 — 2.0 ns Clocks tioclk 60 I/O Clock Delay — 0.3 — 2.0 ns tgclk 61 Global Clock Delay — 1.3 — 2.0 ns tgclkeng 62 Global Clock Enable (Yx Clock) — 1.5 — 2.5 ns tgclkenio 63 Global Clock Enable (I/O Clock) — 1.0 — 3.5 ns tioclkeng 64 I/O Clock Enable (Yx Clock) — 0.5 — 2.5 ns Global Reset tgr 65 Global Reset to I/O Register Latch — 6.0 — 11.0 ns Internal Timing Parameters1 Over Recommended Operating Conditions 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details.

Specifications ispGDX160VA -7 -9 PARAMETER # DESCRIPTION 1 MIN. MAX. MIN. MAX. UNITS Inputs tio 32 Input Buffer Delay — 1.4 — 1.9 ns GRP tgrp 33 GRP Delay — 1.1 — 1.1 ns MUX tmuxd 34 I/O Cell MUX A/B/C/D Data Delay — 2.0 — 2.5 ns tmuxexp 35 I/O Cell MUX A/B/C/D Expander Delay — 2.5 — 3.0 ns tmuxs 36 I/O Cell Data Select — 2.0 — 2.5 ns tmuxsio 37 I/O Cell Data Select (I/O Clock) — 4.5 — 6.0 ns tmuxsg 38 I/O Cell Data Select (Yx Clock) — 2.5 — 3.0 ns tmuxselexp 39 I/O Cell MUX Data Select Expander Delay — 2.5 — 3.0 ns Register tiolat 40 I/O Latch Delay — 1.0 — 1.0 ns tiosu 41 I/O Register Setup Time Before Clock — 3.2 — 4.4 ns tioh 42 I/O Register Hold Time After Clock — 2.3 — 2.6 ns tioco 43 I/O Register Clock to Output Delay — 0.5 — 0.5 ns tior 44 I/O Reset to Output Delay — 1.5 — 1.5 ns tcesu 45 I/O Clock Enable Setup Time Before Clock — 2.5 — 2.0 ns tceh 46 I/O Clock Enable Hold Time After Clock — 1.0 — 2.0 ns Data Path tfdbk 47 I/O Register Feedback Delay — 1.2 — 1.3 ns tiobp 48 I/O Register Bypass Delay — 0.3 — 0.6 ns tioob 49 I/O Register Output Buffer Delay — 0.6 — 0.7 ns tmuxcg 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) — 2.5 — 3.0 ns tmuxcio 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) — 4.5 — 6.0 ns tiodg 52 I/O Register I/O MUX Delay (Yx Clock) — 5.0 — 6.0 ns tiodio 53 I/O Register I/O MUX Delay (I/O Clock) — 7.0 — 9.0 ns Outputs tob 54 Output Buffer Delay — 2.2 — 2.9 ns tobs 55 Output Buffer Delay (Slow Slew Option) — 9.2 — 11.9 ns toeen 56 I/O Cell OE to Output Enable — 6.0 — 7.5 ns toedis 57 I/O Cell OE to Output Disable — 6.0 — 7.5 ns tgoe 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns ttoe 59 Test OE Enable and Disable Delay — 2.5 — 3.0 ns Clocks tioclk 60 I/O Clock Delay — 3.2 — 4.4 ns tgclk 61 Global Clock Delay — 2.7 — 3.4 ns tgclkeng 62 Global Clock Enable (Yx Clock) — 3.7 — 5.4 ns tgclkenio 63 Global Clock Enable (I/O Clock) — 5.7 — 8.4 ns tioclkeng 64 I/O Clock Enable (Yx Clock) — 4.2 — 6.4 ns Global Reset tgr 65 Global Reset to I/O Register Latch — 13.7 — 16.4 ns Internal Timing Parameters1 Over Recommended Operating Conditions 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details.

Absolute Maximum Ratings 1,2 Max. Junction Temp. (T J) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Conditions C SYMBOL Table 2 - 0006 C PARAMETER Dedicated Clock Capacitance 10 UNITSTYPICAL TEST CONDITIONS 8I/O Capacitance pf pf V = 3.3V, V = 2.0V V = 3.3V, V = 2.0VCC CC Y I/O Capacitance (TA =25oC, f=1.0 MHz) TA = 0°C to +70°C TA = -40°C to +85°C SYMBOL Table 2-0005/gdxv VCC VIH1 VIL1 PARAMETER Supply Voltage Input High Voltage 1. Typical 100mV of input hysteresis. Input Low Voltage MIN. MAX. UNITS 3.0 3.0 2.0 -0.3 3.6 3.6 5.25 0.8 V V V V Commercial Industrial PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 10,000 — Cycles Erase/Reprogram Specifications

Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pull-Up Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points Output Short Circuit Current Quiescent Power Supply Current Dynamic Power Supply Current per Input Switching Maximum Continuous I/O Pin Sink Current Through Any GND Pin I OL =24 mA IOH =-12 mA 0V ≤ VIN ≤ VIL (Max.) VCC ≤ VIN ≤ 5.25V 0V ≤ VIN ≤ VIL VIN = VIL (Max.) VIN = VIH (Min.) 0V ≤ VIN ≤ VCC 0V ≤ VIN ≤ VCC VCC = 3.3V, VOUT = 0.5V, TA = 25˚C VIL = 0.5V, VIH = VCC One input toggling @ 50% duty cycle, outputs open. 2.4 -50 V IL 0.55 -10 -150 550 -550 V IH -250 Switching Test Conditions Over Recommended Operating Conditions V V µA µA µA µA µA µA µA V mA mA mA/MHz mA VOL VOH IIL IIH IIL-PU IBHLS IBHHS IBHLO IBHHO IBHT IOS 1 ICCQ 4 ICC 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Typical values are at VCC = 3.3V and TA = 25oC. 3. ICC / MHz = (0.01 x I/O cell fanout) + 0.04 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bidirectionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin. SYMBOL MIN. MAX.TYP. 2PARAMETER CONDITION UNITS Input Pulse Levels GND to 3.0V Input Rise and Fall Time ≤ 1.5ns 10% to 90% Input Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See figure at right 3-state levels are measured 0.5V from steady-state active level. + 3.3V R 1 R 2 C L* Device Output Test Point *C L includes Test Fixture and Probe Capacitance. See Note 3 ICONT 5 Output Load Conditions TEST CONDITION R1 R2 CL A 153 Ω 134Ω 35pF B ∞ 134Ω 35pF 153Ω ∞ 35pF Active High Slow Slew Active Low C D 153Ω ∞ 5pF 35pF 134Ω 5pF Active Low to Z at V +0.5VOL Active High to Z at V -0.5VOH Table 2-0004A

Data Prop. Delay from Any I/O pin to Any I/O pin (4:1 MUX) Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) Clock Frequency, Max. Toggle Clock Frequency with External Feedback Input Latch or Register Setup Time Before Y x Input Latch or Register Setup Time Before I/O Clock Output Latch or Register Setup Time Before Y x Output Latch or Register Setup Time Before I/O Clock Global Clock Enable Setup Time Before Y x Global Clock Enable Setup Time Before I/O Clock I/O Clock Enable Setup Time Before Y x Input Latch or Register Hold Time (Yx) Input Latch or Register Hold Time (I/O Clock) Output Latch or Register Hold Time (Y Output Latch or Register Hold Time (I/O Clock) Global Clock Enable Hold Time (Y Global Clock Enable Hold Time (I/O Clock) I/O Clock Enable Hold Time (Y Output Latch or Register Clock (from Yx) to Output Delay Input Latch or Register Clock (from Yx) to Output Delay Output Latch or Register Clock (from I/O pin) to Output Delay Input Latch or Register Clock (from I/O pin) to Output Delay Input to Output Enable Input to Output Disable Test OE Output Enable Test OE Output Disable Clock Pulse Duration, High Clock Pulse Duration, Low Register Reset Delay from RESET Low Reset Pulse Width Output Delay Adder for Output Timings Using Slow Slew Rate Output Skew (tgco1 Across Chip) External Timing Parameters Over Recommended Operating Conditions ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 143 110 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 3.5 3.5 10.0 5.0 6.5 5.0 8.5 6.0 9.5 6.0 6.0 9.0 9.0 14.0 8.0 0.5 100 80.0 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 5.0 5.0 14.0 7.0 9.0 7.0 11.0 9.0 13.0 8.5 8.5 12.0 12.0 18.0 12.0 0.5 A A A A A A B C B C D A tpd tsel fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco1 tgco2 tco1 tco2 ten tdis ttoeen ttoedis twh twl trst trw tsl tsk DESCRIPTIONPARAMETER TEST1 COND. ( )1 tsu3+tgco1 UNITS-5 MIN. MAX. MIN. MAX. 1. All timings measured with one output switching, fast output slew rate setting, except tsl.

External Timing Parameters (Continued) 01 04 2 03 04 05 06 07 0 I/O Cell Fanout ∆ GRP Delay (ns) ispGDX160V Maximum ∆ GRP Delay vs. I/O Cell Fanout ispGDX160V timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the ∆ GRP Delay with increased GRP loads. These deltas apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder.

-5 -7 PARAMETER # DESCRIPTION 1 MIN. MAX. MIN. MAX. UNITS Inputs tio 32 Input Buffer Delay — 0.9 — 1.4 ns GRP tgrp 33 GRP Delay — 1.1 — 1.1 ns MUX tmuxd 34 I/O Cell MUX A/B/C/D Data Delay — 1.5 — 2.0 ns tmuxexp 35 I/O Cell MUX A/B/C/D Expander Delay — 2.0 — 2.5 ns tmuxs 36 I/O Cell Data Select — 3.0 — 4.0 ns tmuxsio 37 I/O Cell Data Select (I/O Clk) — 4.5 — 6.5 ns tmuxsg 38 I/O Cell Data Select (Yx Clk) — 3.5 — 4.5 ns tmuxselexp 39 I/O Cell MUX Data Select Expander Delay — 3.5 — 4.5 ns Register tiolat 40 I/O Latch Delay — 1.0 — 1.0 ns tiosu 41 I/O Register Setup Time Before Clock — 2.0 — 3.2 ns tioh 42 I/O Register Hold Time After Clock — 1.5 — 2.3 ns tioco 43 I/O Register Clock to Output Delay — 0.5 — 0.5 ns tior 44 I/O Reset to Output Delay — 1.5 — 1.5 ns tcesu 45 I/O Clock Enable Setup Time Before Clock — 2.0 — 2.5 ns tceh 46 I/O Clock Enable Hold Time After Clock — 0.5 — 1.0 ns Data Path tfdbk 47 I/O Register Feedback Delay — 0.9 — 1.2 ns tiobp 48 I/O Register Bypass Delay — 0.0 — 0.3 ns tioob 49 I/O Register Output Buffer Delay — 0.0 — 0.6 ns tmuxcg 50 I/O Register A/B/C/D Data Input MUX Delay (Yx Clk) — 2.0 — 2.5 ns tmuxcio 51 I/O Register A/B/C/D Data Input MUX Delay (I/O Clk) — 3.0 — 4.5 ns tiodg 52 I/O Register I/O MUX Delay (Yx Clk) — 4.0 — 5.0 ns tiodio 53 I/O Register I/O MUX Delay (I/O Clk) — 5.0 — 7.0 ns Outputs tob 54 Output Buffer Delay — 1.5 — 2.2 ns tobs 55 Output Buffer Delay (Slow Slew Option) — 9.5 — 14.2 ns toeen 56 I/O Cell OE to Output Enable — 4.0 — 6.0 ns toedis 57 I/O Cell OE to Output Disable — 4.0 — 6.0 ns tgoe 58 GRP Output Enable and Disable Delay — 0.0 — 0.0 ns ttoe 59 Test OE Enable and Disable Delay — 5.0 — 6.0 ns Clocks tioclk 60 I/O Clock Delay — 2.0 — 3.2 ns tgclk 61 Global Clock Delay — 2.0 — 2.7 ns tgclkeng 62 Global Clock Enable (Yx Clk) — 2.5 — 3.7 ns tgclkenio 63 Global Clock Enable (I/O Clk) — 3.5 — 5.7 ns tioclkeng 64 I/O Clock Enable (Yx Clk) — 2.5 — 4.2 ns Global Reset tgr 65 Global Reset to I/O Register Latch — 11.0 — 13.7 ns Internal Timing Parameters1 Over Recommended Operating Conditions 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details.

Specifications ispGDX160V/VA Switching Waveforms Clock Width CLK (I/O INPUT) twltwh COMBINATORIAL I/O OUTPUT VALID INPUTDATA (I/O INPUT) tpd tsel VALID INPUTMUXSEL (I/O INPUT) Combinatorial Output COMBINATORIAL I/O OUTPUT OE (I/O INPUT) tentdis I/O Output Enable/Disable Registered Output Reset REGISTERED I/O OUTPUT trst RESET trw I/O Pin RESET TOE Y0,1,2,3 Y0,1,2,3, Enable tgclk #61 tgclkeng #62 tgclkenio #63 MUX0 MUX1 tgrp #33 MUX Expander Input GRP A B C D OE tgoe #58 tmuxexp #35 tmuxselexp #39 tiobp #48 CLK CLKEN MUX Expander Output tioob #49 tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 tmuxcg #50 tmuxcio #51 tiod #52, #53 tgr #65 0902/gdx160v/va tio #32 tfdbk #47 tioclk #60 tioclkeg #64 tiolat #40 tiosu #41 tioh #42 tioco #43 tior #44 tcesu #45 tceh #46 tob #54 tobs #55 toeen #56 toedis #57 ttoe #59 CLK CLKEN DQ DATA (I/O INPUT) REGISTERED I/O OUTPUT CLK CLKEN VALID INPUT tt h tsuce tceh tco 1/fmax (external fdbk) tgco su ispGDXV Timing Model

Specifications ispGDX160V/VA ispGDX Development System Lattice’s ispGDX Development System Interface The ispGDX Development System supports ispGDX design using a simple language syntax and an easy-to- use Graphical User Interface (GUI) called Design Manager. From creation to In-System Programming, the ispGDX system is an easy-to-use, self-contained design tool delivered on CD-ROM media.

Features

• Easy-to-use Text Entry System
• ispGDX Design Compiler - Design Rule Checker - I/O Connectivity Checker - Automatic Compiler Function
• Industry Standard JEDEC File for Programming
• Min / Max Timing Report
• Interfaces To Popular Timing Simulators
• User Electronic Signature (UES) Support
• Detailed Log and Report Files For Easy Design Debug
• On-Line Help
• Windows ® 3.1x, Windows 95, Windows 98 and Win- dows NT® Compatible Graphical User Interface
• SUN O/S, Command Line Driven version available PC Version With the ispGDX GUI for the PC, command line entry is not required. The tools run under Microsoft Windows 3.1, Windows 95, Windows 98 and Windows NT. When the ispGDX software is invoked, the Design Manager and an accompanying message window are displayed. The Design Manager consists of the Menu Bar, Tool Bar, Status Bar and the work area. The figure below shows these elements of the ispGDX GUI. The Menu Bar displays topics related to functions used in the design process. Access the various drop-down menus and submenus by using the mouse or “hot” keys. The menu items available in the ispGDX system are FILE, EDIT, DEVICE, INVOKE, INTERFACES, VIEW, WIN- DOW and HELP. The Tool Bar is a quick and easy way to perform many of the functions found in the menus with a single click of the mouse. File, Edit, Undo, Redo, Find, Print Download and Compiler are just some of the Icons found in the ispGDX Tool Bar. For instance, the Compiler Icon performs the same function as the Invoke => Compiler menu com- mands, including design analysis and rule checking and the fitting operation. The Status Bar displays action prompts and the line and column numbers reflect the location of the cursor within the message window or the work area. Workstation Version The ispGDX software is also available for use under the ispGDX software is invoked from the command line under the UNIX operating system. A GUI is not supported in this environment. In the UNIX environment, the ispGDX Design File (GDF) must be created using a text editor. Once the GDF has been created, invoke the ispGDX workstation software from the UNIX command line. The following is an ex- ample of how to invoke ispGDX software. Usage: ispGDX [-i input_file] [-of[edif|orcad|viewlogic|verilog|vhdl]] [-p part name] [-r par_file] Where: -i input_file ispGDX design file -of [edif | orcad | viewlogic | Output format verilog | vhdl] -p part_name ispGDX part number -r par_file Read parameters from parameter file

Specifications ispGDX160V/VA The GDF File The GDF file is a simple text description of the design function, device and pin parameters. The file has four parts: device selection, set and constant statements, a pin section and a connection section. A sample file looks like this: // 32-Bit Data 3 to 1 Mux DESIGN datamux; PART ispGDX160V-7Q208; PARAM SECURITY ON; PARAM OPENDRAIN ON; // USE OPEN DRAIN // OPTION PARAM PULL HOLD; // USE BUS HOLD // LATCH OPTION SET BUS_A [dataA31..dataA0]; SET BUS_B [dataB31..dataB0]; SET BUS_C [dataC31..dataC0]; SET BUS_D [dataD31..dataD0]; INPUT BUS_A {A31..A0}; INPUT BUS_B {B31..B0}; INPUT BUS_C {C31..C0}; OUTPUT BUS_D {D31..D0}; INPUT [oe] {B37}; INPUT [clk] {B36}; INPUT [sel1] {B38}; INPUT [sel0] {B39}; BEGIN BUS_D.m0 = BUS_A; BUS_D.m1 = BUS_B; BUS_D.m2 = BUS_C; BUS_D.m3 = VCC; // Default all // outputs to VCC BUS_D.s1 = sel1; BUS_D.s0 = sel0; BUS_D.oe = oe; BUS_D.clk = clk; END This example shows a simple, but complete, 32-bit 3:1 MUX design. Once completed, the compiler takes over. Powerful Syntax Lattice’s ispGDX Design System uses simple, but power- ful, syntax to easily define a design. The !(bang) operator controls pin polarity and can be used in both the pin and connection sections of the design definition. Dot exten- sions define data inputs, select controls for the 4:1 multiplexor, and control inputs of sequential elements and tri-state buffers. Dot extensions are .M# (MUX Input), .S# (MUX Select), and control functions, such as .CLK, .EN, .OE and .A (shown in adjacent table). Pin Attributes are assigned in the pin section of the GDF as well. SLOWSLEW selects the slow slew rate for an output buffer. The Pull parameter can be used to select the internal pull-up or bus hold latch. OPEN drain can be used to select open drain operation. The COMB attribute distinguishes the structure for bidirectional pins. If COMB is used, the input register, or latch, of an output buffer will be applied to bidirectional pins. Please consult the ispGDX Development System Manual for full details. Type Dot Ext. Description MUX Input MUX Selection Control MUX Output .M0 MUXA Data input to 4:1 MUX .M1 MUXB Data input to 4:1 MUX MUX0 Selection input to 4:1 MUX MUX1 Selection input to 4:1 MUX .M2 MUXC Data Input to 4:1 MUX .M3 .S0 .S1 MUXD Data input to 4:1 MUX .CLK Clock for a register .CE Clock enable for register clock .A Adjacent MUX output of an I/O cell .EN Latch enable for a latch signal .OE Output enable for 3-state output or bidirectional signal ispGDXV Dot Ext ispGDX GDF File Dot Extensions ispGDX Development System (Continued)

Specifications ispGDX160V/VA The ispGDX Design System Compiler After the GDF file is created, the compiler checks the syntax and provides helpful hints and the location of any syntax errors. The compiler performs design rule checks, such as, clock and enable designations, the use of input/ output/BIDI usage, and the proper use of attributes. I/O connectivity is also checked to ensure polarity, MUX selection controls, and connections are properly made. Compilation is completed automatically and report and programming files are saved. Reports Generated When the ispGDX system compiles a design and gener- ates the specified netlists, the following output files are created: Report Files: .log Compiler History .rpt Compiler Report .mfr Maximum Frequency Timing Report .tsu Set-up and Hold Timing Report .tco Clock to Out Timing Report .tpt Timing Report Simulation File: .sim Post-Route Simulation With LAC Format Netlists: .edo EDIF Output .vlo Verilog Output .ifo OrCAD Output .vho VHDL non-VITAL with Maximum Delays Output .vhn VHDL non-VITAL with Maximum Delays Output .vto VHDL VITAL Output Download: .jed JEDEC Device Programming File Third-Party Timing Simulation The ispGDX Design System will generate simulation netlists as specified by a user. The simulation netlist formats available are: EDIF, Verilog (OVI compliant), VHDL (VITAL compliant), Viewlogic, and OrCAD. For In-System Programming, Lattice’s ispGDX devices may be programmed, alone or in a chain with up to 100 other Lattice ISP devices, using Lattice’s ISP Daisy Chain Download software. This powerful Windows-based tool can be launched from the Tool Bar or by Invoking the Download option from the drop down menu within the ispGDX Design System. ISP Daisy Chain Download version 7.1 or above supports the ispGDX Family de- vices. ispGDX Development System (Continued)

Figure 9. ispJTAG Device Programming Interface where a state machine controls the programming. specified by the Instruction Table.

Boundary Scan Test Access Port (TAP) interface. test capability with only a single BSDL file. Table 3. I/O Shift Register Order Figure 10. Boundary Scan Register Circuit for I/O Pins Table 4. ispGDX160V/VA Device ID Codes

Figure 13. Boundary Scan Waveforms and Timing Specifications

Specifications ispGDX160V/VA I/O Input/Output Pins – These are the general purpose bidirectional data pins. When used as outputs, each may be independently latched, registered or tristated. They can also each assume one other control function (OE, CLK/CLKEN, and MUXsel as described in the text). TOE Test Output Enable Pin – This pin tristates all I/P pins when a logic low is driven. RESET Active LOW Input Pin – Resets all I/O register outputs when LOW. Yx/CLKENx Input Pins –These can be either Global Clocks or Clock Enables. EPEN Input Pin – JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low, JTAG TAP controller is driven to reset. TDI Input Pin – Serial data input during ISP programming or Boundary Scan mode. TCK Input Pin – Serial data clock during ISP programming or Boundary Scan mode. TMS Input Pin – Control input during ISP programming or Boundary Scan mode. TDO Output Pin – Serial data output during ISP programming or Boundary Scan mode. GND Ground (GND) VCC Vcc – Supply voltage (3.3V). VCCIO 2 Input – This pin is used if optional 2.5V output is to be used. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. NC 1 No Connect. Signal Descriptions Signal Name Description 1. NC pins are not to be connected to any active signals, VCC or GND. 2. “VA ” version only.

Specifications ispGDX160V/VA Signal Locations: ispGDX160V/VA Signal 208-Pin PQFP 208-Ball fpBGA 272-Ball BGA TOE 178 D9 A12 RESET 185 A8 D10 Y0/CLKEN0 75 N8 V10 Y1/CLKEN1 76 R8 Y10 Y2/CLKEN2 180 B9 C11 Y3/CLKEN3 181 C9 A11 EPEN 183 A9 B10 TDI 81 P9 Y12 TCK 80 T9 U11 TMS 79 T8 V11 TDO 78 P8 W11 GND 6, 15, 25, 35, 44, 54, 63, D4, D13, G7, G8, G9, A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, 77, 91, 100, 110, 119, 129, G10, H7, H8, H9, H10, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, 139, 148, 159, 168, 182, J7, J8, J9, J10, K7, K8, M11, M12, N4, N17, U4, U8, U13, U17 195, 204 K9, K10, N4, N13 VCC 1, 17, 33, 49, 65, 89, 105, E13 1, F4, F13, L4, L13, C181, D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, 121, 137, 153, 1561, 170, M4, M13, N5, N11, N12 U10, U15 184, 193 D5, D6, D12, E4 VCCIO 156 1 E131 C18 1 NC 73, 74, 179 A10, P7, T7 A2, A6, A7, A10, A15, A19, A20, B1, B2, B4, B11, B14, B18, B19, B20, C2, C3, C10, D2, D3, D16, E2, E17, E19, H1, H3, H18, H20, K20, L1, N1, N3, N18 N20, T2, T4, T19, U5, U18, U19, V3, V14, V18, V19, W1, W2, W3, W7, W10, W14, W19, W20, Y1, Y2, Y6, Y9, Y11, Y18, Y20 1. VCC on ispGDX160V, VCCIO on ispGDX160VA.

Specifications ispGDX160V/VA I/O Locations: ispGDX160V/VA (Ordered by I/O Signal Name and 208-Pin PQFP Location) I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA VCC I/O A0 CLK/CLKEN 2 B2 E4 I/O A1 OE 3 B1 C1 I/O A2 MUXsel1 4 C2 D1 I/O A3 MUXsel2 5 A1 E3 GND I/O A4 CLK/CLKEN 7 C1 E1 I/O A5 OE 8 D3 F3 I/O A6 MUXsel1 9 D2 G4 I/O A7 MUXsel2 10 D1 F2 I/O A8 CLK/CLKEN 11 E3 F1 I/O A9 OE 12 E2 G3 I/O A10 MUXsel1 13 E1 G2 I/O A11 MUXsel2 14 F3 G1 GND I/O A12 CLK/CLKEN 16 F2 H2 VCC I/O A13 OE 18 F1 J4 I/O A14 MUXsel1 19 G4 J3 I/O A15 MUXsel2 20 G2 J2 I/O A16 CLK/CLKEN 21 G3 J1 I/O A17 OE 22 G1 K2 I/O A18 MUXsel1 23 H4 K3 I/O A19 MUXsel2 24 H2 K1 GND I/O A20 CLK/CLKEN 26 H3 L2 I/O A21 OE 27 H1 L3 I/O A22 MUXsel1 28 J1 L4 I/O A23 MUXsel2 29 J3 M1 I/O A24 CLK/CLKEN 30 J2 M2 I/O A25 OE 31 J4 M3 I/O A26 MUXsel1 32 K1 M4 VCC I/O A27 MUXsel2 34 K3 N2 GND I/O A28 CLK/CLKEN 36 K2 P1 I/O A29 OE 37 K4 P2 I/O A30 MUXsel1 38 L1 R1 I/O A31 MUXsel2 39 L2 P3 I/O A32 CLK/CLKEN 40 L3 R2 I/O A33 OE 41 M1 T1 I/O A34 MUXsel1 42 M2 P4 I/O A35 MUXsel2 43 M3 R3 GND I/O A36 CLK/CLKEN 45 N1 U1 I/O A37 OE 46 N2 T3 I/O A38 MUXsel1 47 N3 U2 I/O A39 MUXsel2 48 P1 V1 VCC I/O B0 CLK/CLKEN 50 P2 U3 I/O B1 OE 51 R1 V2 I/O B2 MUXsel1 52 R2 W4 I/O B3 MUXsel2 53 T1 V4 GND I/O B4 CLK/CLKEN 55 P3 Y3 I/O B5 OE 56 T2 Y4 I/O B6 MUXsel1 57 R3 V5 I/O B7 MUXsel2 58 P4 W5 I/O B8 CLK/CLKEN 59 T3 Y5 I/O B9 OE 60 R4 V6 I/O B10 MUXsel1 61 T4 U7 I/O B11 MUXsel2 62 P5 W6 GND I/O B12 CLK/CLKEN 64 R5 V7 VCC I/O B13 OE 66 N6 Y7 I/O B14 MUXsel1 67 T5 V8 I/O B15 MUXsel2 68 R6 W8 I/O B16 CLK/CLKEN 69 P6 Y8 I/O B17 OE 70 T6 U9 I/O B18 MUXsel1 71 N7 V9 I/O B19 MUXsel2 72 R7 W9 GND I/O B20 CLK/CLKEN 82 R9 W12 I/O B21 OE 83 N9 V12 I/O B22 MUXsel1 84 T10 U12 I/O B23 MUXsel2 85 P10 Y13 I/O B24 CLK/CLKEN 86 R10 W13 I/O B25 OE 87 N10 V13 I/O B26 MUXsel1 88 T11 Y14 VCC I/O B27 MUXsel2 90 P11 Y15 GND I/O B28 CLK/CLKEN 92 R11 W15 I/O B29 OE 93 T12 Y16 I/O B30 MUXsel1 94 P12 U14 I/O B31 MUXsel2 95 R12 V15 I/O B32 CLK/CLKEN 96 T13 W16 I/O B33 OE 97 R13 Y17 I/O B34 MUXsel1 98 T14 V16 I/O B35 MUXsel2 99 P13 W17 GND I/O B36 CLK/CLKEN 101 R14 U16 I/O B37 OE 102 T15 V17 I/O B38 MUXsel1 103 T16 W18 I/O B39 MUXsel2 104 R15 Y19 VCC I/O C0 CLK/CLKEN 106 P14 T17 I/O C1 OE 107 P15 V20 I/O C2 MUXsel1 108 R16 U20 I/O C3 MUXsel2 109 N14 T18 GND I/O C4 CLK/CLKEN 111 P16 T20 I/O C5 OE 112 N15 R18 I/O C6 MUXsel1 113 N16 P17 I/O C7 MUXsel2 114 M14 R19 I/O C8 CLK 115 M15 R20 I/O C9 OE 116 M16 P18 I/O C10 MUXsel1 117 L15 P19 I/O C11 MUXsel2 118 L14 P20 GND I/O C12 CLK/CLKEN 120 L16 N19 VCC I/O C13 OE 122 K13 M17 I/O C14 MUXsel1 123 K15 M18 I/O C15 MUXsel2 124 K14 M19 I/O C16 CLK/CLKEN 125 K16 M20 I/O C17 OE 126 J13 L19 I/O C18 MUXsel1 127 J15 L18 I/O C19 MUXsel2 128 J14 L20 GND I/O C20 CLK/CLKEN 130 J16 K19 I/O C21 OE 131 H14 K18 I/O C22 MUXsel1 132 H16 K17 I/O C23 MUXsel2 133 H15 J20 I/O C24 CLK/CLKEN 134 H13 J19 I/O C25 OE 135 G16 J18 I/O C26 MUXsel1 136 G14 J17 VCC I/O C27 MUXsel2 138 G15 H19 I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA GND I/O C28 CLK/CLKEN 140 G13 G20 I/O C29 OE 141 F16 G19 I/O C30 MUXsel1 142 F14 F20 I/O C31 MUXsel2 143 F15 G18 I/O C32 CLK/CLKEN 144 E16 F19 I/O C33 OE 145 E14 E20 I/O C34 MUXsel1 146 E15 G17 I/O C35 MUXsel2 147 D16 F18 GND I/O C36 CLK/CLKEN 149 C16 D20 I/O C37 OE 150 D15 E18 I/O C38 MUXsel1 151 D14 D19 I/O C39 MUXsel2 152 C15 C20 VCC I/O D0 CLK/CLKEN 154 B16 D18 I/O D1 OE 155 A16 C19 VCC/VCCIO I/O D2 MUXsel1 157 B15 B17 I/O D3 MUXsel2 158 A15 C17 GND I/O D4 CLK/CLKEN 160 C14 A18 I/O D5 OE 161 B14 A17 I/O D6 MUXsel1 162 A14 C16 I/O D7 MUXsel2 163 C13 B16 I/O D8 CLK/CLKEN 164 B13 A16 I/O D9 OE 165 A13 C15 I/O D10 MUXsel1 166 C12 D14 I/O D11 MUXsel2 167 B12 B15 GND I/O D12 CLK/CLKEN 169 D11 C14 VCC I/O D13 OE 171 A12 A14 I/O D14 MUXsel1 172 C11 C13 I/O D15 MUXsel2 173 B11 B13 I/O D16 CLK/CLKEN 174 D10 A13 I/O D17 OE 175 A11 D12 I/O D18 MUXsel1 176 B10 C12 I/O D19 MUXsel2 177 C10 B12 GND VCC I/O D20 CLK/CLKEN 186 C8 A9 I/O D21 OE 187 B8 B9 I/O D22 MUXsel1 188 D8 C9 I/O D23 MUXsel2 189 A7 D9 I/O D24 CLK/CLKEN 190 C7 A8 I/O D25 OE 191 B7 B8 I/O D26 MUXsel1 192 D7 C8 VCC I/O D27 MUXsel2 194 A6 B7 GND I/O D28 CLK/CLKEN 196 C6 C7 I/O D29 OE 197 B6 B6 I/O D30 MUXsel1 198 A5 A5 I/O D31 MUXsel2 199 C5 D7 I/O D32 CLK/CLKEN 200 B5 C6 I/O D33 OE 201 A4 B5 I/O D34 MUXsel1 202 B4 A4 I/O D35 MUXsel2 203 C4 C5 GND I/O D36 CLK/CLKEN 205 A3 A3 I/O D37 OE 206 C3 D5 I/O D38 MUXsel1 207 B3 C4 I/O D39 MUXsel2 208 A2 B3 NOTE: VCC and GND Pads Shown for Reference, 1VCC in ispGDX160V

Specifications ispGDX160V/VA I/O A3 MUXsel2 5 A1 E3 I/O D39 MUXsel2 208 A2 B3 I/O D36 CLK/CLKEN 205 A3 A3 I/O D33 OE 201 A4 B5 I/O D30 MUXsel1 198 A5 A5 I/O D27 MUXsel2 194 A6 B7 I/O D23 MUXsel2 189 A7 D9 I/O D17 OE 175 A11 D12 I/O D13 OE 171 A12 A14 I/O D9 OE 165 A13 C15 I/O D6 MUXsel1 162 A14 C16 I/O D3 MUXsel2 158 A15 C17 I/O D1 OE 155 A16 C19 I/O A1 OE 3 B1 C1 I/O A0 CLK/CLKEN 2 B2 E4 I/O D38 MUXsel1 207 B3 C4 I/O D34 MUXsel1 202 B4 A4 I/O D32 CLK/CLKEN 200 B5 C6 I/O D29 OE 197 B6 B6 I/O D25 OE 191 B7 B8 I/O D21 OE 187 B8 B9 I/O D18 MUXsel1 176 B10 C12 I/O D15 MUXsel2 173 B11 B13 I/O D11 MUXsel2 167 B12 B15 I/O D8 CLK/CLKEN 164 B13 A16 I/O D5 OE 161 B14 A17 I/O D2 MUXsel1 157 B15 B17 I/O D0 CLK/CLKEN 154 B16 D18 I/O A4 CLK/CLKEN 7 C1 E1 I/O A2 MUXsel1 4 C2 D1 I/O D37 OE 206 C3 D5 I/O D35 MUXsel2 203 C4 C5 I/O D31 MUXsel2 199 C5 D7 I/O D28 CLK/CLKEN 196 C6 C7 I/O D24 CLK/CLKEN 190 C7 A8 I/O D20 CLK/CLKEN 186 C8 A9 I/O D19 MUXsel2 177 C10 B12 I/O D14 MUXsel1 172 C11 C13 I/O D10 MUXsel1 166 C12 D14 I/O D7 MUXsel2 163 C13 B16 I/O D4 CLK/CLKEN 160 C14 A18 I/O C39 MUXsel2 152 C15 C20 I/O C36 CLK/CLKEN 149 C16 D20 I/O A7 MUXsel2 10 D1 F2 I/O A6 MUXsel1 9 D2 G4 I/O A5 OE 8 D3 F3 I/O D26 MUXsel1 192 D7 C8 I/O D22 MUXsel1 188 D8 C9 I/O D16 CLK/CLKEN 174 D10 A13 I/O D12 CLK/CLKEN 169 D11 C14 I/O C38 MUXsel1 151 D14 D19 I/O C37 OE 150 D15 E18 I/O C35 MUXsel2 147 D16 F18 I/O A10 MUXsel1 13 E1 G2 I/O A9 OE 12 E2 G3 I/O A8 CLK/CLK_EN 11 E3 F1 I/O C33 OE 145 E14 E20 I/O C34 MUXsel1 146 E15 G17 I/O C32 CLK/CLKEN 144 E16 F19 I/O A13 OE 18 F1 J4 I/O A12 CLK/CLKEN 16 F2 H2 I/O A11 MUXsel2 14 F3 G1 I/O C30 MUXsel1 142 F14 F20 I/O C31 MUXsel2 143 F15 G18 I/O C29 OE 141 F16 G19 I/O A17 OE 22 G1 K2 I/O A15 MUXsel2 20 G2 J2 I/O A16 CLK/CLKEN 21 G3 J1 I/O A14 MUXsel1 19 G4 J3 I/O C28 CLK/CLKEN 140 G13 G20 I/O C26 MUXsel1 136 G14 J17 I/O C27 MUXsel2 138 G15 H19 I/O C25 OE 135 G16 J18 I/O A21 OE 27 H1 L3 I/O A19 MUXsel2 24 H2 K1 I/O A20 CLK/CLKEN 26 H3 L2 I/O A18 MUXsel1 23 H4 K3 I/O C24 CLK/CLKEN 134 H13 J19 I/O C21 OE 131 H14 K18 I/O C23 MUXsel2 133 H15 J20 I/O C22 MUXsel1 132 H16 K17 I/O A22 MUXsel1 28 J1 L4 I/O A24 CLK/CLKEN 30 J2 M2 I/O A23 MUXsel2 29 J3 M1 I/O A25 OE 31 J4 M3 I/O C17 OE 126 J13 L19 I/O C19 MUXsel2 128 J14 L20 I/O C18 MUXsel1 127 J15 L18 I/O C20 CLK/CLKEN 130 J16 K19 I/O A26 MUXsel1 32 K1 M4 I/O A28 CLK/CLKEN 36 K2 P1 I/O A27 MUXsel2 34 K3 N2 I/O A29 OE 37 K4 P2 I/O C13 OE 122 K13 M17 I/O C15 MUXsel2 124 K14 M19 I/O C14 MUXsel1 123 K15 M18 I/O C16 CLK/CLKEN 125 K16 M20 I/O A30 MUXsel1 38 L1 R1 I/O A31 MUXsel2 39 L2 P3 I/O A32 CLK/CLKEN 40 L3 R2 I/O C11 MUXsel2 118 L14 P20 I/O C10 MUXsel1 117 L15 P19 I/O C12 CLK/CLKEN 120 L16 N19 I/O A33 OE 41 M1 T1 I/O A34 MUXsel1 42 M2 P4 I/O A35 MUXsel2 43 M3 R3 I/O C7 MUXsel2 114 M14 R19 I/O Locations: ispGDX160V/VA (Ordered by 208-Ball BGA Location) I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA I/O C8 CLK 115 M15 R20 I/O C9 OE 116 M16 P18 I/O A36 CLK/CLKEN 45 N1 U1 I/O A37 OE 46 N2 T3 I/O A38 MUXsel1 47 N3 U2 I/O B13 OE 66 N6 Y7 I/O B18 MUXsel1 71 N7 V9 I/O B21 OE 83 N9 V12 I/O B25 OE 87 N10 V13 I/O C3 MUXsel2 109 N14 T18 I/O C5 OE 112 N15 R18 I/O C6 MUXsel1 113 N16 P17 I/O A39 MUXsel2 48 P1 V1 I/O B0 CLK/CLKEN 50 P2 U3 I/O B4 CLK/CLKEN 55 P3 Y3 I/O B7 MUXsel2 58 P4 W5 I/O B11 MUXsel2 62 P5 W6 I/O B16 CLK/CLKEN 69 P6 Y8 I/O B23 MUXsel2 85 P10 Y13 I/O B27 MUXsel2 90 P11 Y15 I/O B30 MUXsel1 94 P12 U14 I/O B35 MUXsel2 99 P13 W17 I/O C0 CLK/CLKEN 106 P14 T17 I/O C1 OE 107 P15 V20 I/O C4 CLK/CLKEN 111 P16 T20 I/O B1 OE 51 R1 V2 I/O B2 MUXsel1 52 R2 W4 I/O B6 MUXsel1 57 R3 V5 I/O B9 OE 60 R4 V6 I/O B12 CLK/CLKEN 64 R5 V7 I/O B15 MUXsel2 68 R6 W8 I/O B19 MUXsel2 72 R7 W9 I/O B20 CLK/CLKEN 82 R9 W12 I/O B24 CLK/CLKEN 86 R10 W13 I/O B28 CLK/CLKEN 92 R11 W15 I/O B31 MUXsel2 95 R12 V15 I/O B33 OE 97 R13 Y17 I/O B36 CLK/CLKEN 101 R14 U16 I/O B39 MUXsel2 104 R15 Y19 I/O C2 MUXsel1 108 R16 U20 I/O B3 MUXsel2 53 T1 V4 I/O B5 OE 56 T2 Y4 I/O B8 CLK/CLKEN 59 T3 Y5 I/O B10 MUXsel1 61 T4 U7 I/O B14 MUXsel1 67 T5 V8 I/O B17 OE 70 T6 U9 I/O B22 MUXsel1 84 T10 U12 I/O B26 MUXsel1 88 T11 Y14 I/O B29 OE 93 T12 Y16 I/O B32 CLK/CLKEN 96 T13 W16 I/O B34 MUXsel1 98 T14 V16 I/O B37 OE 102 T15 V17 I/O B38 MUXsel1 103 T16 W18

Specifications ispGDX160V/VA I/O C32 CLK/CLKEN 144 E16 F19 I/O C30 MUXsel1 142 F14 F20 I/O A11 MUXsel2 14 F3 G1 I/O A10 MUXsel1 13 E1 G2 I/O A9 OE 12 E2 G3 I/O A6 MUXsel1 9 D2 G4 I/O C34 MUXsel1 146 E15 G17 I/O C31 MUXsel2 143 F15 G18 I/O C29 OE 141 F16 G19 I/O C28 CLK/CLKEN 140 G13 G20 I/O A12 CLK/CLKEN 16 F2 H2 I/O C27 MUXsel2 138 G15 H19 I/O A16 CLK/CLKEN 21 G3 J1 I/O A15 MUXsel2 20 G2 J2 I/O A14 MUXsel1 19 G4 J3 I/O A13 OE 18 F1 J4 I/O C26 MUXsel1 136 G14 J17 I/O C25 OE 135 G16 J18 I/O C24 CLK/CLKEN 134 H13 J19 I/O C23 MUXsel2 133 H15 J20 I/O A19 MUXsel2 24 H2 K1 I/O A17 OE 22 G1 K2 I/O A18 MUXsel1 23 H4 K3 I/O C22 MUXsel1 132 H16 K17 I/O C21 OE 131 H14 K18 I/O C20 CLK/CLKEN 130 J16 K19 I/O A20 CLK/CLKEN 26 H3 L2 I/O A21 OE 27 H1 L3 I/O A22 MUXsel1 28 J1 L4 I/O C18 MUXsel1 127 J15 L18 I/O C17 OE 126 J13 L19 I/O C19 MUXsel2 128 J14 L20 I/O A23 MUXsel2 29 J3 M1 I/O A24 CLK/CLKEN 30 J2 M2 I/O A25 OE 31 J4 M3 I/O A26 MUXsel1 32 K1 M4 I/O C13 OE 122 K13 M17 I/O C14 MUXsel1 123 K15 M18 I/O C15 MUXsel2 124 K14 M19 I/O C16 CLK/CLKEN 125 K16 M20 I/O A27 MUXsel2 34 K3 N2 I/O C12 CLK/CLKEN 120 L16 N19 I/O A28 CLK/CLKEN 36 K2 P1 I/O A29 OE 37 K4 P2 I/O A31 MUXsel2 39 L2 P3 I/O A34 MUXsel1 42 M2 P4 I/O C6 MUXsel1 113 N16 P17 I/O C9 OE 116 M16 P18 I/O C10 MUXsel1 117 L15 P19 I/O C11 MUXsel2 118 L14 P20 I/O A30 MUXsel1 38 L1 R1 I/O A32 CLK/CLKEN 40 L3 R2 I/O A35 MUXsel2 43 M3 R3 I/O D36 CLK/CLKEN 205 A3 A3 I/O D34 MUXsel1 202 B4 A4 I/O D30 MUXsel1 198 A5 A5 I/O D24 CLK/CLKEN 190 C7 A8 I/O D20 CLK/CLKEN 186 C8 A9 I/O D16 CLK/CLKEN 174 D10 A13 I/O D13 OE 171 A12 A14 I/O D8 CLK/CLKEN 164 B13 A16 I/O D5 OE 161 B14 A17 I/O D4 CLK/CLKEN 160 C14 A18 I/O D39 MUXsel2 208 A2 B3 I/O D33 OE 201 A4 B5 I/O D29 OE 197 B6 B6 I/O D27 MUXsel2 194 A6 B7 I/O D25 OE 191 B7 B8 I/O D21 OE 187 B8 B9 I/O D19 MUXsel2 177 C10 B12 I/O D15 MUXsel2 173 B11 B13 I/O D11 MUXsel2 167 B12 B15 I/O D7 MUXsel2 163 C13 B16 I/O D2 MUXsel1 157 B15 B17 I/O A1 OE 3 B1 C1 I/O D38 MUXsel1 207 B3 C4 I/O D35 MUXsel2 203 C4 C5 I/O D32 CLK/CLKEN 200 B5 C6 I/O D28 CLK/CLKEN 196 C6 C7 I/O D26 MUXsel1 192 D7 C8 I/O D22 MUXsel1 188 D8 C9 I/O D18 MUXsel1 176 B10 C12 I/O D14 MUXsel1 172 C11 C13 I/O D12 CLK/CLKEN 169 D11 C14 I/O D9 OE 165 A13 C15 I/O D6 MUXsel1 162 A14 C16 I/O D3 MUXsel2 158 A15 C17 I/O D1 OE 155 A16 C19 I/O C39 MUXsel2 152 C15 C20 I/O A2 MUXsel1 4 C2 D1 I/O D37 OE 206 C3 D5 I/O D31 MUXsel2 199 C5 D7 I/O D23 MUXsel2 189 A7 D9 I/O D17 OE 175 A11 D12 I/O D10 MUXsel1 166 C12 D14 I/O D0 CLK/CLKEN 154 B16 D18 I/O C38 MUXsel1 151 D14 D19 I/O C36 CLK/CLKEN 149 C16 D20 I/O A4 CLK/CLK_EN 7 C1 E1 I/O A3 MUXsel2 5 A1 E3 I/O A0 CLK/CLKEN 2 B2 E4 I/O C37 OE 150 D15 E18 I/O C33 OE 145 E14 E20 I/O A8 CLK/CLKEN 11 E3 F1 I/O A7 MUXsel2 10 D1 F2 I/O A5 OE 8 D3 F3 I/O C35 MUXsel2 147 D16 F18 I/O Locations: ispGDX160V/VA (Ordered by 272-Ball BGA Location) I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA I/O Control 208 208 272 Signal Signal PQFP f pBGA BGA I/O C5 OE 112 N15 R18 I/O C7 MUXsel2 114 M14 R19 I/O C8 CLK 115 M15 R20 I/O A33 OE 41 M1 T1 I/O A37 OE 46 N2 T3 I/O C0 CLK/CLKEN 106 P14 T17 I/O C3 MUXsel2 109 N14 T18 I/O C4 CLK/CLKEN 111 P16 T20 I/O A36 CLK/CLKEN 45 N1 U1 I/O A38 MUXsel1 47 N3 U2 I/O B0 CLK/CLKEN 50 P2 U3 I/O B10 MUXsel1 61 T4 U7 I/O B17 OE 70 T6 U9 I/O B22 MUXsel1 84 T10 U12 I/O B30 MUXsel1 94 P12 U14 I/O B36 CLK/CLKEN 101 R14 U16 I/O C2 MUXsel1 108 R16 U20 I/O A39 MUXsel2 48 P1 V1 I/O B1 OE 51 R1 V2 I/O B3 MUXsel2 53 T1 V4 I/O B6 MUXsel1 57 R3 V5 I/O B9 OE 60 R4 V6 I/O B12 CLK/CLKEN 64 R5 V7 I/O B14 MUXsel1 67 T5 V8 I/O B18 MUXsel1 71 N7 V9 I/O B21 OE 83 N9 V12 I/O B25 OE 87 N10 V13 I/O B31 MUXsel2 95 R12 V15 I/O B34 MUXsel1 98 T14 V16 I/O B37 OE 102 T15 V17 I/O C1 OE 107 P15 V20 I/O B2 MUXsel1 52 R2 W4 I/O B7 MUXsel2 58 P4 W5 I/O B11 MUXsel2 62 P5 W6 I/O B15 MUXsel2 68 R6 W8 I/O B19 MUXsel2 72 R7 W9 I/O B20 CLK/CLKEN 82 R9 W12 I/O B24 CLK/CLKEN 86 R10 W13 I/O B28 CLK/CLKEN 92 R11 W15 I/O B32 CLK/CLKEN 96 T13 W16 I/O B35 MUXsel2 99 P13 W17 I/O B38 MUXsel1 103 T16 W18 I/O B4 CLK/CLKEN 55 P3 Y3 I/O B5 OE 56 T2 Y4 I/O B8 CLK/CLKEN 59 T3 Y5 I/O B13 OE 66 N6 Y7 I/O B16 CLK/CLKEN 69 P6 Y8 I/O B23 MUXsel2 85 P10 Y13 I/O B26 MUXsel1 88 T11 Y14 I/O B27 MUXsel2 90 P11 Y15 I/O B29 OE 93 T12 Y16 I/O B33 OE 97 R13 Y17 I/O B39 MUXsel2 104 R15 Y19

Specifications ispGDX160V/VA Signal Configuration: ispGDX160V/VA ispGDX160V/VA 272-Ball BGA Signal Diagram 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A NC 1 NC 1 I/O I/O I/O D8 NC 1 I/O D13 I/O D16 TOE Y3/ CLKEN3 NC 1 I/O D20 I/O D24 NC 1 NC 1 I/O D30 I/O D34 I/O D36 NC 1 GND A B NC 1 NC 1 NC 1 I/O I/O I/O D11 NC 1 I/O D15 I/O D19 EPENNC 1 I/O D21 I/O D25 I/O D27 I/O D29 I/O D33 NC 1 I/O D39 NC 1 NC 1 B C I/O C39 I/O VCCIO VCC I/O I/O I/O I/O D12 I/O D14 I/O D18 Y2/ CLKEN2 NC 1 I/O D22 I/O D26 I/O D28 I/O D32 I/O D35 I/O D38 NC 1 NC 1 I/O A1 C D I/O C36 I/O C38 I/O D0 GND NC 1 VCC I/O D10 GND I/O D17 VCC RESET I/O D23 GND I/O D31 VCC I/O D37 GND NC 1 NC 1 I/O A2 D E I/O C33 NC 1 I/O C37 NC 1 I/O I/O A3 NC 1 I/O A4 E F I/O C30 I/O C32 I/O C35 VCC VCC I/O I/O I/O A8 F G I/O C28 I/O C29 I/O C31 I/O C34 I/O I/O I/O A10 I/O A11 G H NC 1 I/O C27 NC 1 GND GND NC 1 I/O A12 NC 1 H J I/O C23 I/O C24 I/O C25 I/O C26 GND GND GND GND I/O A13 I/O A14 I/O A15 I/O A16 J K NC 1 I/O C20 I/O C21 I/O C22 GND GND GND GND VCC I/O A18 I/O A17 I/O A19 K L I/O C19 I/O C17 I/O C18 VCC GND GND GND GND I/O A22 I/O A21 I/O A20 NC 1 L M I/O C16 I/O C15 I/O C14 I/O C13 GND GND GND GND I/O A26 I/O A25 I/O A24 I/O A23 M N NC 1 I/O C12 NC 1 GND GND NC 1 I/O A27 NC 1 N P I/O C11 I/O C10 I/O I/O I/O A34 I/O A31 I/O A29 I/O A28 P R I/O I/O I/O C5 VCC VCC I/O A35 I/O A32 I/O A30 R T I/O C4 NC 1 I/O I/O C0 NC 1 I/O A37 NC 1 I/O A33 T U I/O C2 NC 1 NC 1 GND I/O B36 VCC I/O B30 GND I/O B22 TCK VCC I/O B17 GND I/O B10 VCC NC 1 GND I/O I/O A38 I/O A36 U V I/O C1 NC 1 NC 1 I/O B37 I/O B34 I/O B31 NC 1 I/O B25 I/O B21 TMS Y0/ CLKEN0 I/O B18 I/O B14 I/O B12 I/O I/O I/O B3 NC 1 I/O I/O A39 V W NC 1 NC 1 I/O B38 I/O B35 I/O B32 I/O B28 NC 1 I/O B24 I/O B20 TDO NC 1 I/O B19 I/O B15 NC 1 I/O B11 I/O I/O B2 NC 1 NC 1 NC 1 W Y NC 1 I/O B39 NC 1 I/O B33 I/O B29 I/O B27 I/O B26 I/O B23 TDI NC 1 Y1/ CLKEN1 NC 1 I/O B16 I/O B13 NC 1 I/O I/O I/O B4 NC 1 NC 1 Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1. NCs are not to be connected to any active signals, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. ispGDX160V/VA Bottom View

Specifications ispGDX160V/VA Signal Configuration: ispGDX160V/VA ispGDX160V/VA 208-Ball fpBGA Signal Diagram 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 I/O I/O I/O I/O I/O D13 I/O D17 NC 1 EPEN RESET I/O D23 I/O D27 I/O D30 I/O D33 I/O D36 I/O D39 I/O A3 A B A I/O I/O I/O I/O I/O D11 I/O D15 I/O D18 Y2/ CLKEN2 I/O D21 I/O D25 I/O D29 I/O D32 I/O D34 I/O D38 I/O I/O A1 B C I/O C36 I/O C39 I/O I/O I/O D10 I/O D14 I/O D19 Y3/ CLKEN3 I/O D20 I/O D24 I/O D28 I/O D31 I/O D35 I/O D37 I/O I/O A4 C D I/O C35 I/O C37 I/O C38 GND VCC I/O D12 I/O D16 TOE I/O D22 I/O D26 VCC VCC GND I/O I/O I/O A7 D E I/O C32 I/O C34 I/O C33 VCCIO/ VCC 2 VCC I/O I/O I/O A10 E F I/O C29 I/O C31 I/O C30 VCC VCC I/O A11 I/O A12 I/O A13 F G I/O C25 I/O C27 I/O C26 I/O C28 GND GND GND GND I/O A14 I/O A16 I/O A15 I/O A17 G H I/O C22 I/O C23 I/O C21 I/O C24 GND GND GND GND I/O A18 I/O A20 I/O A19 I/O A21 H J I/O C20 I/O C18 I/O C19 I/O C17 GND GND GND GND I/O A25 I/O A23 I/O A24 I/O A22 J K I/O C16 I/O C14 I/O C15 I/O C13 GND GND GND GND I/O A29 I/O A27 I/O A28 I/O A26 K L I/O C12 I/O C10 I/O C11 VCC VCC I/O A32 I/O A31 I/O A30 L M I/O I/O I/O C7 VCC VCC I/O A35 I/O A34 I/O A33 M N I/O I/O I/O C3 GND VCC VCC I/O B25 I/O B21 Y0/ CLKEN0 I/O B18 I/O B13 VCC GND I/O A38 I/O A37 I/O A36 N P I/O I/O I/O I/O B35 I/O B30 I/O B27 I/O B23 TDI TDO NC 1 I/O B16 I/O B11 I/O I/O I/O I/O A39 P R I/O I/O B39 I/O B36 I/O B33 I/O B31 I/O B28 I/O B24 I/O B20 Y1/ CLKEN1 I/O B19 I/O B15 I/O B12 I/O I/O I/O I/O B1 R T I/O B38 I/O B37 I/O B34 I/O B32 I/O B29 I/O B26 I/O B22 TCK TMS NC 1 I/O B17 I/O B14 I/O B10 I/O I/O I/O B3 T 16 15 14 13 12 11 10 1. NCs are not to be connected to any active signals, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. 9 876 54321 ispGDX160V/VA Bottom View

Specifications ispGDX160V/VA Pin Configuration: ispGDX160V/VA ispGDX160V/VA 208-Pin PQFP Pinout Diagram 1. No Connect Pins (NC) are not to be connected to any active signal, Vcc or GND. 2. VCCIO on ispGDX160VA. VCC on ispGDX160V. ispGDX160V/VA Top View 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VCC I/O A 0 I/O A 1 I/O A 2 I/O A 3 GND I/O A 4 I/O A 5 I/O A 6 I/O A 7 I/O A 8 I/O A 9 I/O A 10 I/O A 11 GND I/O A 12 VCC I/O A 13 I/O A 14 I/O A 15 I/O A 16 I/O A 17 I/O A 18 I/O A 19 GND I/O A 20 I/O A 21 I/O A 22 I/O A 23 I/O A 24 I/O A 25 I/O A 26 VCC I/O A 27 GND I/O A 28 I/O A 29 I/O A 30 I/O A 31 I/O A 32 I/O A 33 I/O A 34 I/O A 35 GND I/O A 36 I/O A 37 I/O A 38 I/O A 39 VCC I/O B 0 I/O B 1 I/O B 2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 VCCIO/VCC I/O D1 I/O D 0 VCC I/O C 39 I/O C 38 I/O C 37 I/O C 36 GND I/O C 35 I/O C 34 I/O C 33 I/O C 32 I/O C 31 I/O C 30 I/O C 29 I/O C 28 GND I/O C 27 VCC I/O C 26 I/O C 25 I/O C 24 I/O C 23 I/O C 22 I/O C 21 I/O C 20 GND I/O C 19 I/O C 18 I/O C 17 I/O C 16 I/O C 15 I/O C 14 I/O C 13 VCC I/O C 12 GND I/O C 11 I/O C 10 I/O C 9 I/O C 8 I/O C 7 I/O C 6 I/O C 5 I/O C 4 GND I/O C 3 I/O C 2 I/O C 1 I/O C 0 VCC DataControl MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 CLK/CLKEN OE MUXsel1 MUXsel2 DataControl I/O B 3 GND I/O B 4 I/O B 5 I/O B 6 I/O B 7 I/O B 8 I/O B 9 I/O B 10 I/O B 11 GND I/O B 12 VCC I/O B 13 I/O B 14 I/O B 15 I/O B 16 I/O B 17 I/O B 18 I/O B 19 1NC 1NC CLK_EN0/Y0 CLK_EN1/Y1 GND TDO TMS TCK TDI I/O B 20 I/O B 21 I/O B 22 I/O B 23 I/O B 24 I/O B 25 I/O B 26 VCC I/O B 27 GND I/O B 28 I/O B 29 I/O B 30 I/O B 31 I/O B 32 I/O B 33 I/O B 34 I/O B 35 GND I/O B 36 I/O B 37 I/O B 38 I/O B 39 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN Data Control I/O D 39 I/O D 38 I/O D 37 I/O D 36 GND I/O D 35 I/O D 34 I/O D 33 I/O D 32 I/O D 31 I/O D 30 I/O D 29 I/O D 28 GND I/O D 27 VCC I/O D 26 I/O D 25 I/O D 24 I/O D 23 I/O D 22 I/O D 21 I/O D 20 RESET VCC EPEN GND Y3/CLK_EN3 Y2/CLK_EN2 NC TOE I/O D 19 I/O D 18 I/O D 17 I/O D 16 I/O D 15 I/O D 14 I/O D 13 VCC I/O D 12 GND I/O D 11 I/O D 10 I/O D 9 I/O D 8 I/O D 7 I/O D 6 I/O D 5 I/O D 4 GND I/O D 3 I/O D 2 MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 OE CLK/CLKEN MUXsel2 MUXsel1 Data Control

Specifications ispGDX160V/VA Part Number Description

Ordering Information

Blank = Commercial I = Industrial ispGDX XXXXX X XXXX X Speed 3 = 3.5ns Tpd 5 = 5ns Tpd 7 = 7ns Tpd 9 = 9ns Tpd Package Q208 = 208-Pin PQFP B208 = 208-Ball fpBGA B272 = 272-Ball BGA Device Family 0212/ispGDXVA Table 2-0041A/ispGDXV/A 208-Pin PQFP 208-Ball fpBGA ispGDX160VA-5Q208 208-Ball fpBGA5 ispGDX160VA-5B208ispGDXVA 272-Ball BGA5 ispGDX160VA-5B272 208-Pin PQFP3.5 ispGDX160VA-3Q208 208-Ball fpBGA3.5 ispGDX160VA-3B208 272-Ball BGA3.5 ispGDX160VA-3B272 208-Pin PQFP7 ispGDX160VA-7Q208 ispGDX160VA-7B208 272-Ball BGA7 ispGDX160VA-7B272 208-Pin PQFP 208-Ball fpBGA ispGDX160V-5Q208 208-Ball fpBGA5 ispGDX160V-5B208 ispGDXV* 272-Ball BGA5 ispGDX160V-5B272 208-Pin PQFP7 ispGDX160V-7Q208 ispGDX160V-7B208 272-Ball BGA7 ispGDX160V-7B272 FAMILY ORDERING NUMBER PACKAGEtpd (ns) COMMERCIAL Table 2-0041C/ispGDXV 208-Pin PQFP 208-Ball fpBGA ispGDX160VA-5Q208I 208-Ball fpBGA5 ispGDX160VA-5B208I ispGDXVA ispGDXV* 272-Ball BGA5 ispGDX160VA-5B272I 208-Pin PQFP7 ispGDX160VA-7Q208I 208-Pin PQFP7 ispGDX160V-7Q208I ispGDX160VA-7B208I 272-Ball BGA7 ispGDX160VA-7B272I 208-Ball fpBGA9 208-Pin PQFP9 ispGDX160VA-9Q208I ispGDX160VA-9B208I 272-Ball BGA9 ispGDX160VA-9B272I FAMILY ORDERING NUMBER PACKAGEtpd (ns) INDUSTRIAL *Use ispGDX160VA for new designs. Note: The ispGDX160VA devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, e.g. ispGDX160VA-3B208-5I.