1048C

1048C LATTICE | Alldatasheet

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Features

• HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 50 MHz Maximum Operating Frequency — tpd = 22 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested at Time of Manufacture
• IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

can source 4 mA or sink 8 mA. connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1048C/883 device contains six Megablocks. GLBs and all of the inputs from the bi-directional I/O cells. Figure 1. ispLSI 1048C/883 Functional Block Diagram

Specifications ispLSI 1048C/883 Absolute Maximum Ratings 1 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions V V PARAMETERSYMBOL MIN. MAX. UNITS 5.5 0.8 Vcc + 1 Supply VoltageVCC VIL VIH 0005A mil.eps 4.5 2.0 Military/883 TC = -55°C to +125°C Input Low Voltage Input High Voltage V Capacitance (TA =25oC, f=1.0 MHz) SYMBOL PARAMETER MAXIMUM 1 UNITS TEST CONDITIONS C 1 10 pf V CC =5.0V, VIN=2.0V C 2 I/O and Clock Capacitance 10 pf V CC =5.0V, VI/O, VY=2.0V 1. Characterized but not 100% tested. Table 2- 0006mil Dedicated Input Capacitance Data Retention Specifications Table 2- 0008B PARAMETER Data Retention MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 10000 Years Cycles

Figure 2. Test Load *C L includes Test Fixture and Probe Capacitance. CONDITIONPARAMETERSYMBOL MIN. MAX.

1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground

degradation. Characterized but not 100% tested.

1. Measured using twelve 16-bit counters.
2. Typical values are at VCC = 5V and TA = 25oC.
3. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-

Specifications ispLSI 1048C/883 External Timing Parameters Over Recommended Operating Conditions tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback Clock Frequency, Max Toggle GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Input to Output Enable Input to Output Disable Global OE Output Enable Global OE Output Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) A A A A A B C B C DESCRIPTION 1PARAMETER # 2 -50 MAX. 22.0 26.0 14.0 16.0 20.5 27.5 27.5 20.5 20.5 ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN. UNITS Table 2- 0030-48C/50 mil 50.3 34.5 58.8 13.0 15.0 13.5 8.5 8.5 3.0 9.0 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit counter using GRP feedback. 4. Reference Switching Test Conditions section. ( )1 twh + tw1 ( )1 tsu2 + tco1 TEST 4 COND.

Specifications ispLSI 1048C/883 Internal Timing Parameters1 4.3 5.5 4.6 5.1 7.4 6.2 6.7 8.0 10.5 22.7 5.5 6.7 7.5 8.9 1.2 2.3 2.8 11.1 9.6 8.2 3.4 1.4 9.1 0.3 3.9 7.3 3.4 tiobp tiolat tiosu tioh tioco tior tdin tgrp1 tgrp4 tgrp8 tgrp16 tgrp48 t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck torp torpbp ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN. MAX. DESCRIPTIONPARAMETER UNITS-50 Inputs I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock I/O Register Hold Time after Clock I/O Register Clock to Out Delay I/O Register Reset to Out Delay Dedicated Input Delay GRP Delay, 1 GLB Load GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 16 GLB Loads GRP Delay, 48 GLB Loads

4 Product Term Bypass Path Delay

1 Product Term/XOR Path Delay

20 Product Term/XOR Path Delay

GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay ORP Delay ORP Bypass Delay GRP GLB ORP Table 2- 0036-48C/50MIL1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.

Specifications ispLSI 1048C/883 Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled Global OE Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers 7.4 6.1 2.6 6.1 2.6 tob toen todis tgoe tgy0 tgy1/2 tgcp tioy2/3 tiocp tgr 2.9 6.9 6.9 13.6 7.4 8.7 7.6 8.7 7.6 11.4 ns ns ns ns ns ns ns ns ns ns MIN. MAX. DESCRIPTIONPARAMETER UNITS-50 Outputs 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. Global Reset Table 2- 0037-48C/50mil Clocks Internal Timing Parameters1

Specifications ispLSI 1048C/883 ispLSI 1048C/883 Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay Feedback

4 PT Bypass

(Input) Y1,2,3 D Q GRP 4 GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Reg Bypass I/O CellORPGLBGRPI/O Cell #25 - 29 #32 #36 #37, 38, 39 #55, 56, 57, 58 #45, 46, #54 #48 #49 Reset Ded. In #30 #24 RST #59 #59 #40 #41, 42, 43, 44 #51, 52 #50 GOE0, 1 0491A/48 #53 #31, 33, 34, 35 Derivations of tsu, th and tco from the Product Term Clock1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) th = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco = Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) Derivations of tsu, th and tco from the Clock GLB1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) th = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco = Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) 1. Calculations are based upon timing specifications for the ispLSI 1048C-50

Figure 3. Typical Device Power Consumption vs fmax conditions and the program in the device, the actual ICC should be verified.

Specifications ispLSI 1048C/883 GND B2, B8, B13, C8, H3, H12, M8, N2, N8 VCC C7, G2, G3, G12, G13, M7, I/O 0 - I/O 5 J2, J3, K1, L1, K2, M1, I/O 6 - I/O 11 L2, K3, N1, M2, L3, P1, I/O 12 - I/O 17 M3, P2, N3, M4, P3, N4, I/O 18 - I/O 23 P4, M5, N5, P5, M6, N6, I/O 24 - I/O 29 N9, M9, P10, P11, N10, P12, I/O 30 - I/O 35 N11, M10, P13, N12, M11, P14, I/O 36 - I/O 41 M12, N14, M13, L12, M14, L13, I/O 42 - I/O 47 L14, K12, K13, K14, J12, J13, I/O 48 - I/O 53 F13, F12, E14, D14, E13, C14, I/O 54 - I/O 59 D13, E12, B14, C13, D12, A14, I/O 60 - I/O 65 C12, A13, B12, C11, A12, B11, I/O 66 - I/O 71 A11, C10, B10, A10, C9, B9, I/O 72 - I/O 77 B6, C6, A5, A4, B5, A3, I/O 78 - I/O 83 B4, C5, A2, B3, C4, A1, I/O 84 - I/O 89 C3, B1, C2, D3, C1, D2, I/O 90 - I/O 95 D1, E3, E2, E1, F3, F2 RESET H1 Y0 G1 Y1 G14 Y2 H13 Y3 H14 IN 2, IN 4 P7, P9 IN 6 - IN 11 F14, A9, A8, A7, A6, F1 GOE0, GOE1 N13, B7, Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input – This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Input/Output Pins - These are the general purpose I/O pins used by the logic array. Ground (GND) VCC Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/ or any I/O cell on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. Dedicated input pins to the device. Global output enables for all I/Os. Table 2- 0002C-48C/CPGA DESCRIPTIONNAME CPGA PIN NUMBERS ispEN H2 SDI/IN 01 J1 MODE/IN 11 P6 SDO/IN 31 P8 SCLK/IN 51 J14 1. Pins have dual function capability. Pin Description

Specifications ispLSI 1048C/883 Pin Configuration ispLSI 1048C/883 133-Pin CPGA Pinout Diagram I/O59 I/O56 I/O53 I/O51 I/O50 IN6 I/O40 I/O37 I/O35 I/O61 GND I/O57 I/O54 I/O52 I/O48 Vcc I/O38 GOE0 I/O32 I/O64 I/O62 I/O55 I/O49 Vcc I/O33 I/O29 IN8 GND GND SDO/ IN31 IN9 GOE1 Vcc Vcc Vcc IN2 IN10 I/O72 I/O73 I/O22 I/O23 MODE/ IN11 I/O74 I/O76 I/O79 I/O19 I/O20 I/O21 I/O75 I/O78 I/O17 I/O18 I/O77 I/O81 I/O84 I/O91 I/O94 Vcc I/O14 I/O16 I/O80 GND I/O86 I/O89 I/O92 I/O95 Vcc I/O9 GND I/O13 I/O83 I/O85 I/O88 I/O90 I/O93 IN11 I/O5 I/O8 I/O11 ispLSI 1048C/883 Bottom View A B C D E F G H J K L M N P 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN A1 133 CPGA Pinout.eps I/O66 I/O65 I/O69 I/O68 IN7 I/O71 I/O30 I/O27 I/O28 I/O26 I/O24 IN4 I/O15 I/O12 I/O67 I/O70 GNDI/O60 I/O63 I/O82 I/O87I/O58 GND I/O1 I/O7 I/O10 I/O0 I/O4 I/O6 SDI/ IN01 I/O2 I/O3 SCLK/ IN51 I/O45 I/O42 I/O47 I/O44 I/O41 I/O46 I/O43 I/O39 I/O36 I/O34 I/O31 I/O25 GND INDEX GND RESETispEN 1. Pins have dual function capability.

Specifications ispLSI 1048C/883 MILITARY tpd (ns)fmax (MHz) Ordering Number Package 50 22 ispLSI 1048C-50LG/883 133-Pin CPGAispLSI Family SMD Number 5962-9558701MXC Table 2- 0041A-48C-ispmil

Ordering Information

/883 = 883 Military Process Device Number 1048C XX X X X Speed 50 = 50 MHz fmax Power L = Low Package G = CPGA Device Family 0212-80B-isp1048C mil ispLSI