10321111

10321111 LATTICE | Alldatasheet

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• HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Fast Random Logic — Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 90 MHz Maximum Operating Frequency — fmax = 60 MHz for Industrial and Military/883 Devices — tpd = 12 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity
• ispLSI AND pLSI DEVELOPMENT TOOLS pDS® Software — Easy to Use PC Windows™ Interface — Boolean Logic Compiler — Manual Partitioning — Automatic Place and Route — Static Timing Table ispDS+™ Software — Industry Standard, Third Party Design Environments — Schematic Capture, State Machine, HDL — Automatic Partitioning and Place and Route — Comprehensive Logic and Timing Simulation — PC and Workstation Platforms ispLSI and pLSI 1032 High-Density Programmable Logic Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com 1996 ISP Encyclopedia

Specifications ispLSI and pLSI 1032 3 1996 ISP Encyclopedia Absolute Maximum Ratings 1 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions V V PARAMETERSYMBOL MIN. MAX. UNITS 5.25 5.5 5.5 0.8 Vcc + 1 Supply VoltageVCC VIL VIH Table 2- 0005Aisp w/mil.eps 4.75 4.5 4.5 2.0 Commercial T A = 0°C to +70°C Industrial TA = -40°C to +85°C Military/883 TC = -55°C to +125°C Input Low Voltage Input High Voltage V Capacitance (TA =25oC, f=1.0 MHz) SYMBOL PARAMETER MAXIMUM 1 UNITS TEST CONDITIONS C 1 Commercial/Industrial 8 pf VCC =5.0V, VIN=2.0V Military 10 pf V CC =5.0V, VIN=2.0V C 2 I/O and Clock Capacitance 10 pf V CC =5.0V, VI/O, VY=2.0V 1. Guaranteed but not 100% tested. Table 2- 0006 Dedicated Input Capacitance Data Retention Specifications Table 2- 0008B PARAMETER pLSI Erase/Reprogram Cycles 100 Data Retention MINIMUM MAXIMUM UNITS ispLSI Erase/Reprogram Cycles 10000 Cycles Years Cycles

Figure 2. Test Load *C L includes Test Fixture and Probe Capacitance.

1. One output at a time for a maximum duration of one second.
2. Measured using eight 16-bit counters.
3. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-

Specifications ispLSI and pLSI 1032 5 1996 ISP Encyclopedia USE 1032E-80 FOR NEW DESIGNS USE 1032E-70 FOR NEW DESIGNS External Timing Parameters Over Recommended Operating Conditions 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions section. MIN. MAX. Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback Clock Frequency, Max Toggle GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Input to Output Enable Input to Output Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5 A A A A A B C DESCRIPTION 1PARAMETER # 2 UNITS TEST 5 COND. tsu2 + tco1( ) MIN. MAX. 100 6.5 2.5 8.5 22.5 -80 -60 MIN. MAX. 90.9 58.8 125 6.5 -90 Table 2-0030-32/90,80,60C

Specifications ispLSI and pLSI 1032 6 1996 ISP Encyclopedia USE 1032E-80 FOR NEW DESIGNSUSE 1032E-70 FOR NEW DESIGNS Internal Timing Parameters1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7.3 1.3 1.3 6.0 4.6 2.7 4.0 4.0 3.3 5.3 2.0 2.7 4.0 5.0 6.0 10.6 8.6 9.3 10.6 12.7 1.3 2.7 3.3 13.3 12.0 9.9 3.3 0.7 MIN. MAX. DESCRIPTIONPARAMETER UNITS -60 Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP t grp1 tgrp4 tgrp8 tgrp12 tgrp16 tgrp32 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock I/O Register Hold Time after Clock I/O Register Clock to Out Delay I/O Register Reset to Out Delay Dedicated Input Delay GRP Delay, 1 GLB Load GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 12 GLB Loads GRP Delay, 16 GLB Loads GRP Delay, 32 GLB Loads

4 Product Term Bypass Path Delay

1 Product Term/XOR Path Delay

20 Product Term/XOR Path Delay

GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay ORP Delay ORP Bypass Delay 5.5 1.0 1.0 4.5 3.5 2.0 3.0 3.0 2.5 4.0 1.5 2.0 3.0 3.8 4.5 8.0 6.5 7.0 8.0 9.5 1.0 2.0 2.5 10.0 9.0 7.5 2.5 0.5 MIN. MAX. -80 4.8 2.1 1.2 3.6 2.8 1.6 2.4 2.4 2.8 3.2 1.2 1.6 2.4 3.0 3.6 6.4 5.2 5.7 7.0 8.2 0.8 1.6 2.0 8.0 7.8 6.0 2.4 0.4 MIN. MAX. -90 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.

Specifications ispLSI and pLSI 1032 7 1996 ISP Encyclopedia USE 1032E-80 FOR NEW DESIGNS USE 1032E-70 FOR NEW DESIGNS Internal Timing Parameters1 ns ns ns ns ns ns ns ns ns 6.0 4.6 1.3 4.6 1.3 4.0 6.7 6.7 6.0 7.3 6.6 7.3 6.6 12.0 Outputs tob toen todis Clocks t gy0 tgy1/2 tgcp tioy2/3 tiocp Global Reset t gr Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers MIN. MAX. DESCRIPTIONPARAMETER UNITS -60 4.5 3.5 1.0 3.5 1.0 3.0 5.0 5.0 4.5 5.5 5.0 5.5 5.0 9.0 MIN. MAX. -80 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3.6 2.8 0.8 2.8 0.8 2.4 4.0 4.0 3.6 4.4 4.0 4.4 4.0 8.2 MIN. MAX. -90

Specifications ispLSI and pLSI 1032 8 1996 ISP Encyclopedia ispLSI and pLSI 1032 Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay Feedback

4 PT Bypass

(Input) Y1,2,3 D Q GRP 4 GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Reg Bypass I/O CellORPGLBGRPI/O Cell #21 - 25 #27, 29, 30, 31, 32 #28 #33 #34, 35, 36 #51, 52, 53, 54 #42, 43, #50 #45 #46 Reset Ded. In #26 #20 RST #55 #55 #37 #38, 39, 40, 41 #48, 49 #47 Derivations of tsu, th and tco from the Product Term Clock1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) th = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco = Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) Derivations of tsu, th and tco from the Clock GLB1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) th = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco = Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) 1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032-80.

Figure 3. Typical Device Power Consumption vs fmax program in the device, the actual ICC should be verified.

Specifications ispLSI and pLSI 1032 11 1996 ISP Encyclopedia ispLSI 1032 Shift Register Layout E2CMOS Cell Array High Order Shift Register Low Order Shift Register 159... 319... ...0 ...160 D A T A D A T A Data In (SDI) SDO 107. .Address Shift Register SDO SDI Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification. A logic "0" disables it.

Specifications ispLSI and pLSI 1032 12 1996 ISP Encyclopedia Pin Description Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input – This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. * For ispLSI 1032 Only Name PLCC Pin Numbers Description Input/Output Pins - These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 3 26, 27, 28, 29, I/O 4 - I/O 7 30, 31, 32, 33, I/O 8 - I/O 11 34, 35, 36, 37, I/O 12 - I/O 15 38, 39, 40, 41, I/O 16 - I/O 19 45, 46, 47, 48, I/O 20 - I/O 23 49, 50, 51, 52, I/O 24 - I/O 27 53, 54, 55, 56, I/O 28 - I/O 31 57, 58, 59, 60, I/O 32 - I/O 35 68, 69, 70, 71, I/O 36 - I/O 39 72, 73, 74, 75, I/O 40 - I/O 43 76, 77, 78, 79, I/O 44 - I/O 47 80, 81, 82, 83, I/O 52 - I/O 55 7, 8, 9, 10, I/O 56 - I/O 59 11, 12, 13, 14, I/O 60 - I/O 63 15, 16, 17, 18 IN 4 - IN 7 67, 84, 2, 19 Dedicated input pins to the device. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. ispEN*/NC 23 SDI*/IN 0 25 MODE*/IN 1 42 SDO*/IN 2 44 SCLK*/IN 3 61 GND 1, 22, 43, 64 VCC 21, 65 Ground (GND) VCC RESET 24 Y0 20 Y1 66 Y2 63 Y3 62 Table 2-0002A-32-isp

Specifications ispLSI and pLSI 1032 13 1996 ISP Encyclopedia Pin Description Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input – This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. These pins are not used. DescriptionTQFP Pin NumbersName Input/Output Pins - These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 3 17, 18, 19, 20, I/O 4 - I/O 7 21, 22, 23, 28, I/O 8 - I/O 11 29, 30, 31, 32, I/O 12 - I/O 15 33, 34, 35, 36, I/O 16 - I/O 19 40, 41, 42, 43, I/O 20 - I/O 23 44, 45, 46, 47, I/O 24 - I/O 27 48, 53, 54, 55, I/O 28 - I/O 31 56, 57, 58, 59, I/O 32 - I/O 35 67, 68, 69, 70, I/O 36 - I/O 39 71, 72, 73, 78, I/O 40 - I/O 43 79, 80, 81, 82, I/O 44 - I/O 47 83, 84, 85, 86, I/O 48 - I/O 51 90, 91, 92, 93, I/O 52 - I/O 55 94, 95, 96, 97, I/O 56 - I/O 59 98, 3, 4, 5, I/O 60 - I/O 63 6, 7, 8, 9 IN 4 - IN 7 66, 87, 89, 10 Dedicated input pins to the device. ispEN*/NC 14 SDI*/IN 0 16 MODE*/IN 1 37 SDO*/IN 2 39 SCLK*/IN 3 60 NC 1, 2, 24, 25, 26, 27, 49, 50, 51, 52, 74, 75 76, 77, 99, 100 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. RESET 15 Y0 11 Y1 65 Y2 62 Y3 61 GND 13, 38, 63, 88 VCC 12, 64 Ground (GND) VCC Table 2- 0002B-32-isp* For ispLSI 1032 Only

Specifications ispLSI and pLSI 1032 14 1996 ISP Encyclopedia Pin Description RESET G1 Y0 E1 Y1 E11 Y2 G9 Y3 G11 NC G3 GND C6, F3, F9, J6 VCC F2, F11 I/O 0 - I/O 3 F1, H1, H2, J1, I/O 4 - I/O 7 K1, J2, L1, K2, I/O 8 - I/O 11 K3, L2, L3, K4, I/O 12 - I/O 15 L4, J5, K5, L5, I/O 16 - I/O 19 L7, K7, L6, L8, I/O 20 - I/O 23 K8, L9, L10, K9, I/O 24 - I/O 27 L11, K10, J10, K11, I/O 28 - I/O 31 J11, H10, H11, F10, I/O 32 - I/O 35 E9, D11, D10, C11, I/O 36 - I/O 39 B11, C10, A11, B10, I/O 40 - I/O 43 B9, A10, A9, B8, I/O 44 - I/O 47 A8, B6, B7, A7, I/O 48 - I/O 51 A5, B5, C5, A4, I/O 52 - I/O 55 B4, A3, A2, B3, I/O 56 - I/O 59 A1, B2, C2, B1, I/O 60 - I/O 63 C1, D2, D1, E3 IN 4 - IN 7 E10, C7, A6, E2 Dedicated input pins to the device. Input/Output Pins - These are the general purpose I/O pins used by the logic array. Name CPGA Pin Numbers Description Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input – This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. ispEN*/NC G3 SDI*/IN 0 G2 MODE*/IN 1 K6 SDO*/IN 2 J7 SCLK*/IN 3 G10 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. This pin should be left floating or tied to V CC. This pin should never be tied to GND. Ground (GND) VCC Table 2-0002-32/883

Specifications ispLSI and pLSI 1032 15 1996 ISP Encyclopedia Pin Configuration ispLSI and pLSI 1032 84-Pin PLCC Pinout Diagram I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 IN 4 VCC GND IN 3/SCLK* I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 VCC GND *ispEN/NC RESET *SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 *MODE/IN 1 GND *SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 ispLSI 1032 pLSI 1032 Top View *Pins have dual function capability for ispLSI 1032 only (except pin 23, which is ispEN only). 0123-32-isp

Specifications ispLSI and pLSI 1032 16 1996 ISP Encyclopedia NC NC I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 VCC GND *ispEN/NC RESET *SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 NC NC NC NC I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 IN 4 VCC GND IN 3/SCLK* I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 NC NC NC NC I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 NC NC NC NC I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 *MODE/IN1 GND *SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 NC NC 100 ispLSI 1032 pLSI 1032 Top View *Pins have dual function capability for ispLSI 1032 only (except pin 14, which is ispEN only). 0766A-32-isp Pin Configuration ispLSI and pLSI 1032 100-pin TQFP Pinout Diagram

Specifications ispLSI and pLSI 1032 17 1996 ISP Encyclopedia I/O38 I/O36 I/O35 I/O33 Vcc I/O30 I/O28 I/O27 I/O24 I/O41 I/O39 I/O37 I/O34 IN4 I/O31 *SCLK/ IN3 I/O29 I/O26 I/O25 I/O22 I/O42 I/O40 I/O32 GND I/O23 I/O21 I/O44 I/O43 I/O20 I/O19 I/O47 I/O46 IN5 *SDO/ IN2 I/O17 I/O16 IN6 I/O45 GND GND *MODE/ IN1 I/O18 I/O48 I/O49 I/O50 I/O13 I/O14 I/O15 I/O51 I/O52 I/O11 I/O12 I/O53 I/O55 INDEX I/O63 GND *ispEN /NC I/O8 I/O10 I/O54 I/O57 I/O58 I/O61 IN7 Vcc *SDI/ IN0 I/O2 I/O5 I/O7 I/O9 I/O56 I/O59 I/O60 I/O62 I/O0 RESET I/O1 I/O3 I/O4 I/O6 ispLSI 1032/883 pLSI 1032/883 Bottom View A B C D E F G H J K L 11 10 9 8 7 6 5 4 3 2 1 PIN A1 *Pins have dual function capability for ispLSI 1032/883 only (except pin G3, which is ispEN only). 0488A-32-isp/883 Pin Configuration ispLSI and pLSI 1032/883 84-Pin CPGA Pinout Diagram

Specifications ispLSI and pLSI 1032 18 1996 ISP Encyclopedia ispLSI and pLSI 1032 Ordering Information Part Number Description Device Number Grade Blank = Commercial I = Industrial /883 = 883 Military Process

1032 XX X X X

90 = 90 MHz fmax 80 = 80 MHz fmax 60 = 60 MHz fmax Power L = Low Package J = PLCC T = TQFP G = CPGA Device Family 0212-80B-isp1032 (is)pLSI tpd (ns)fmax (MHz) Ordering Number Package 90 12 ispLSI 1032-90LT 100-Pin TQFP 80 15 ispLSI 1032-80LJ 84-Pin PLCC COMMERCIAL 90 12 ispLSI 1032-90LJ 84-Pin PLCC 80 15 ispLSI 1032-80LT 100-Pin TQFP 60 20 ispLSI 1032-60LJ 84-Pin PLCC 60 20 ispLSI 1032-60LT 100-Pin TQFPINDUSTRIAL tpd (ns)fmax (MHz) Ordering Number Package 60 20 ispLSI 1032-60LJI 84-Pin PLCC Family ispLSI 90 12 pLSI 1032-90LT 100-Pin TQFP 80 15 pLSI 1032-80LJ 84-Pin PLCC 90 12 pLSI 1032-90LJ 84-Pin PLCC 80 15 pLSI 1032-80LT 100-Pin TQFP 60 20 pLSI 1032-60LJ 84-Pin PLCC 60 20 pLSI 1032-60LT 100-Pin TQFP pLSI ispLSI pLSI 60 20 pLSI 1032-60LJI 84-Pin PLCC Family Table 2- 0041A-32-isp MILITARY/883 tpd (ns)fmax (MHz) Ordering Number Package 60 20 ispLSI 1032-60LG/883 84-Pin CPGAispLSI pLSI 60 20 pLSI 1032-60LG/883 84-Pin CPGA Family SMD Number 5962-9308501MXC 5962-9466801MXC Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended. 60 20 ispLSI 1032-60LTI 100-Pin TQFP

Copyright © 1997 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispGDS, ispDS, ispDS+, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders. Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US, 5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US, 5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US, 0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not represent that products described herein are free from patent infringement or from any third-party right. The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. LSC warrants performance of its products to current and applicable specifications in accordance with LSC’s standard warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements. LSC assumes no liability for applications assistance, customer’s product design, software performance, or infringements of patents or services arising from the use of the products and services described herein. LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such applications is prohibited. LATTICE SEMICONDUCTOR CORPORATION

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