1032

1032 LATTICE | Alldatasheet

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Technical content

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Fast Random Logic — Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 60 MHz Maximum Operating Frequency — tpd = 20 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested
• IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms 1032MIL_01 Functional Block Diagram Output Routing Pool Output Routing Pool D7 D6 D5 D4 D3 D2 D1 D0 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool CLK Output Routing Pool Global Routing Pool (GRP) Logic Array DQ DQ DQ DQ GLB

Description

The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD- 883. This military grade device contains 192 Registers,

64 Universal I/O pins, eight Dedicated Input pins, four

Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032/883 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1032/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see figure 1). There are a total of 32 GLBs in the ispLSI 1032/883 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications ispLSI 1032/883 Absolute Maximum Ratings 1 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions V V PARAMETERSYMBOL MIN. MAX. UNITS 5.5 0.8 Vcc + 1 Supply VoltageVCC VIL VIH 0005A mil.eps 4.5 2.0 Military/883 TC = -55°C to +125°C Input Low Voltage Input High Voltage V Capacitance (TA =25oC, f=1.0 MHz) SYMBOL PARAMETER MAXIMUM 1 UNITS TEST CONDITIONS C 1 10 pf V CC =5.0V, VIN=2.0V C 2 I/O and Clock Capacitance 10 pf V CC =5.0V, VI/O, VY=2.0V 1. Characterized but not 100% tested. Table 2- 0006mil Dedicated Input Capacitance Data Retention Specifications Table 2- 0008B PARAMETER Data Retention MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 10000 Years Cycles

Figure 2. Test Load *C L includes Test Fixture and Probe Capacitance. CONDITIONPARAMETERSYMBOL MIN. MAX.

1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground

degradation. Characterized but not 100% tested.

1. Measured using six 16-bit counters.
2. Typical values are at VCC = 5V and TA = 25oC.
3. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-

Specifications ispLSI 1032/883 External Timing Parameters Over Recommended Operating Conditions 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions section. MIN. MAX. Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback Clock Frequency, Max Toggle GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Input to Output Enable Input to Output Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5 A A A A A B C DESCRIPTION 1PARAMETER # 2 UNITS TEST 5 COND. tsu2 + tco1( ) 2.5 8.5 22.5 -60 Table 2-0030-32/60C

Specifications ispLSI 1032/883 Internal Timing Parameters1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7.3 1.3 1.3 6.0 4.6 2.7 4.0 4.0 3.3 5.3 2.0 2.7 4.0 5.0 6.0 10.6 8.6 9.3 10.6 12.7 1.3 2.7 3.3 13.3 12.0 9.9 3.3 0.7 MIN. MAX. DESCRIPTIONPARAMETER UNITS -60 Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP t grp1 tgrp4 tgrp8 tgrp12 tgrp16 tgrp32 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock I/O Register Hold Time after Clock I/O Register Clock to Out Delay I/O Register Reset to Out Delay Dedicated Input Delay GRP Delay, 1 GLB Load GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 12 GLB Loads GRP Delay, 16 GLB Loads GRP Delay, 32 GLB Loads

4 Product Term Bypass Path Delay

1 Product Term/XOR Path Delay

20 Product Term/XOR Path Delay

GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay ORP Delay ORP Bypass Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice Hard Macros.

Specifications ispLSI 1032/883 Internal Timing Parameters1 ns ns ns ns ns ns ns ns ns 6.0 4.6 1.3 4.6 1.3 4.0 6.7 6.7 6.0 7.3 6.6 7.3 6.6 12.0 Outputs tob toen todis Clocks t gy0 tgy1/2 tgcp tioy2/3 tiocp Global Reset t gr Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line Global Reset to GLB and I/O Registers MIN. MAX. DESCRIPTIONPARAMETER UNITS -60 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.

Specifications ispLSI 1032/883 ispLSI 1032/883 Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay Feedback

4 PT Bypass

(Input) Y1,2,3 D Q GRP 4 GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Reg Bypass I/O CellORPGLBGRPI/O Cell #21 - 25 #27, 29, 30, 31, 32 #28 #33 #34, 35, 36 #51, 52, 53, 54 #42, 43, #50 #45 #46 Reset Ded. In #26 #20 RST #55 #55 #37 #38, 39, 40, 41 #48, 49 #47 1. Calculations are based upon timing specifications for the ispLSI 1032-60. Derivations of tsu, th and tco from the Product Term Clock1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) th = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco = Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) Derivations of tsu, th and tco from the Clock GLB1 tsu = Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) th = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco = Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

Figure 3. Typical Device Power Consumption vs fmax program in the device, the actual ICC should be verified.

Specifications ispLSI 1032/883 Pin Description RESET G1 Y0 E1 Y1 E11 Y2 G9 Y3 G11 NC 2 G3 GND C6, F3, F9, J6 VCC F2, F11 I/O 0 - I/O 3 F1, H1, H2, J1, I/O 4 - I/O 7 K1, J2, L1, K2, I/O 8 - I/O 11 K3, L2, L3, K4, I/O 12 - I/O 15 L4, J5, K5, L5, I/O 16 - I/O 19 L7, K7, L6, L8, I/O 20 - I/O 23 K8, L9, L10, K9, I/O 24 - I/O 27 L11, K10, J10, K11, I/O 28 - I/O 31 J11, H10, H11, F10, I/O 32 - I/O 35 E9, D11, D10, C11, I/O 36 - I/O 39 B11, C10, A11, B10, I/O 40 - I/O 43 B9, A10, A9, B8, I/O 44 - I/O 47 A8, B6, B7, A7, I/O 48 - I/O 51 A5, B5, C5, A4, I/O 52 - I/O 55 B4, A3, A2, B3, I/O 56 - I/O 59 A1, B2, C2, B1, I/O 60 - I/O 63 C1, D2, D1, E3 IN 4 - IN 7 E10, C7, A6, E2 Dedicated input pins to the device. Input/Output Pins - These are the general purpose I/O pins used by the logic array. Name CPGA Pin Numbers Description Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input – This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. ispEN G3 SDI/IN 01 G2 MODE/IN 11 K6 SDO/IN 21 J7 SCLK/IN 31 G10 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. No Connect Ground (GND) VCC Table 2-0002-32/8831. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, Vcc or GND.

Specifications ispLSI 1032/883 I/O38 I/O36 I/O35 I/O33 Vcc I/O30 I/O28 I/O27 I/O24 I/O41 I/O39 I/O37 I/O34 IN4 I/O31 *SCLK/ IN3 I/O29 I/O26 I/O25 I/O22 I/O42 I/O40 I/O32 GND I/O23 I/O21 I/O44 I/O43 I/O20 I/O19 I/O47 I/O46 IN5 *SDO/ IN2 I/O17 I/O16 IN6 I/O45 GND GND *MODE/ IN1 I/O18 I/O48 I/O49 I/O50 I/O13 I/O14 I/O15 I/O51 I/O52 I/O11 I/O12 I/O53 I/O55 INDEX I/O63 GND ispEN I/O8 I/O10 I/O54 I/O57 I/O58 I/O61 IN7 Vcc *SDI/ IN0 I/O2 I/O5 I/O7 I/O9 I/O56 I/O59 I/O60 I/O62 I/O0 RESET I/O1 I/O3 I/O4 I/O6 ispLSI 1032/883 Bottom View A B C D E F G H J K L 11 10 9 8 7 6 5 4 3 2 1 PIN A1 *Pins have dual function capability. 0488A-32-isp/883 Pin Configuration ispLSI 1032/883/883 84-Pin CPGA Pinout Diagram

Specifications ispLSI 1032/883 Table 2- 0041A-32-ispmil MILITARY/883 tpd (ns)fmax (MHz) Ordering Number Package 60 20 ispLSI 1032-60LG/883 84-Pin CPGAispLSI Family SMD Number 5962-9308501MXC Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended.

Ordering Information

/883 = 883 Military Process

1032 XX X X X

60 = 60 MHz fmax Power L = Low Package G = CPGA Device Family 0212-80B-isp1032 ispLSI