1024EA

1024EA LATTICE | Alldatasheet

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In-System Programmable High Density PLD 1024ea_01 1 Functional Block DiagramFeatures

• HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 48 I/O Pins, Two Dedicated Inputs — 144 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic
• NEW FEATURES — 100% IEEE 1149.1 Boundary Scan Testable — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems (V CCIO Pin) — Open-Drain Output Option
• HIGH PERFORMANCE E 2CMOS ® TECHNOLOGY — fmax = 200 MHz Maximum Operating Frequency — tpd = 4.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Output Routing Pool B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool Output Routing Pool CLK Global Routing Pool (GRP) 0139/1024EA Logic Array DQ DQ DQ DQ GLB

Description

The ispLSI 1024EA is a High Density Programmable Logic Device containing 144 Registers, 48 Universal I/O pins, two Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1024EA features 5V in-system diagnostic capabilities via IEEE 1149.1 Test Access Port. The ispLSI 1024EA device offers non-volatile reprogrammability of the logic, as well as the intercon- nects to provide truly reconfigurable systems. A functional superset of the ispLSI 1024 architecture, the ispLSI 1024EA device adds user selectable 3.3V or 5V I/O and open-drain output options. The basic unit of logic on the ispLSI 1024EA device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1… D7 (Figure 1). There are a total of 24 GLBs in the ispLSI 1024EA device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinato- rial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Figure 1. ispLSI 1024EA Functional Block Diagram connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1024EA device contains three Megablocks. GLBs and all of the inputs from the bi-directional I/O cells. device is in bulk erased state is totem-pole configuration. the ispDesignEXPERT software tools.

Figure 2. Boundary Scan Waveforms and Timing Specifications

Specifications ispLSI 1024EA Absolute Maximum Ratings 1 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Conditions TA = 0°C to + 70°C SYMBOL Table 2-0005/1024EA VCC VCCIO VIH VIL PARAMETER Supply Voltage Supply Voltage: Output Drivers Input High Voltage Input Low Voltage MIN. MAX. UNITS 4.75 4.75 3.0 2.0 5.25 5.25 3.6 Vcc+1 0.8 V V V V V Commercial 3.3V Capacitance (TA =25oC, f=1.0 MHz) Erase/Reprogram Specifications Table 2-0008/1024EA PARAMETER Erase/Reprogram Cycles MINIMUM MAXIMUM UNITS 10000 — Cycles C SYMBOL Table 2-0006/1024EA C PARAMETER Y0 Clock Capacitance 10 UNITSTYPICAL TEST CONDITIONS 8Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) pf pf V = 5.0V, V = 2.0V V = 5.0V, V = 2.0VCC CC PIN PIN

Figure 3. Test Load *C L includes Test Fixture and Probe Capacitance.

1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.

1. Measured using eight 16-bit counters.
2. Unused inputs held at 0.0V.

Specifications ispLSI 1024EA tpd1 UNITSTEST COND. 1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030A/1024EA v.2.5 tsu2 + tco1( ) DESCRIPTION#2PARAMETER A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd2 A 2 Data Propagation Delay, Worst Case Path ns fmax (Int.) A 3 Clock Frequency with Internal Feedback MHz fmax (Ext.) — 4 Clock Frequency with External Feedback MHz fmax (Tog.) — 5 Clock Frequency, Max. Toggle MHz tsu1 — 6 GLB Reg. Setup Time before Clock,4 PT Bypass ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu2 — 9 GLB Reg. Setup Time before Clock ns tco2 — 10 GLB Reg. Clock to Output Delay ns th2 — 11 GLB Reg. Hold Time after Clock ns tr1 A 12 Ext. Reset Pin to Output Delay ns trw1 — 13 Ext. Reset Pulse Duration ns tptoeen B 14 Input to Output Enable ns tptoedis C 15 Input to Output Disable ns twh — 18 External Synchronous Clock Pulse Duration, High ns twl — 19 External Synchronous Clock Pulse Duration, Low ns tsu3 — 20 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) ns th3 — 21 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) ns ( ) twh + twl tgoeen B 16 Global OE Output Enable ns tgoedis C 17 Global OE Output Disable ns -200 MIN. MAX. — 4.5 200 — 2.0 2.0 143 250 3.0 0.0 3.5 0.0 3.5 3.0 0.0 6.0 3.5 4.0 5.5 7.0 7.0 — 4.5 — 4.5 -100 MIN. MAX. — 10.0 100 — 4.0 4.0 125 6.0 0.0 7.0 0.0 6.5 3.5 0.0 12.5 6.0 7.0 13.5 15.0 15.0 — 9.0 — 9.0 -125 MIN. MAX. — 7.5 125 — 3.0 3.0 100 167 4.5 0.0 5.5 0.0 5.0 3.0 0.0 10.0 4.5 5.5 10.0 12.0 12.0 — 7.0 — 7.0 External Timing Parameters Over Recommended Operating Conditions

Specifications ispLSI 1024EA Internal Timing Parameters1 GRP Delay, 24 GLB Loads tiobp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036A/1024EA v.2.5 Inputs UNITSDESCRIPTION#2PARAM.

22 I/O Register Bypass ns

tiolat 23 I/O Latch Delay ns tgrp24 33 ns GLB t1ptxor 36 1 ProductTerm/XOR Path Delay ns t20ptxor 37 20 Product Term/XOR Path Delay ns txoradj 38 XOR Adjacent Path Delay ns tgbp 39 GLB Register Bypass Delay ns tgsu 40 GLB Register Setup Time before Clock ns tgh 41 GLB Register Hold Time after Clock ns tgco 42 GLB Register Clock to Output Delay ns tgro 43 GLB Register Reset to Output Delay ns tptre 44 GLB Product Term Reset to Register Delay ns tptoe 45 GLB Product Term Output Enable to I/O Cell Delay ns tptck 46 GLB Product Term Clock Delay ns ORP GRP t4ptbpc 34 4 ProductTerm Bypass Path Delay (Combinatorial) ns t4ptbpr 35 4 Product Term Bypass Path Delay (Registered) ns torp 48 ORP Delay ns torpbp 49 ORP Bypass Delay ns tiosu 24 I/O Register Setup Time before Clock ns tioh 25 I/O Register Hold Time after Clock ns tioco 26 I/O Register Clock to Out Delay ns tior 27 I/O Register Reset to Out Delay ns tdin 28 Dedicated Input Delay ns tgrp16 32 GRP Delay, 16 GLB Loads ns tgrp8 31 GRP Delay, 8 GLB Loads ns tgrp4 30 GRP Delay, 4 GLB Loads ns tgrp1 29 GRP Delay, 1 GLB Load ns tgfb 47 GLB Feedback Delay ns MIN. MAX. -200 0.2 1.0 1.5 3.0 0.0 0.3 4.0 2.5 1.9 1.9 1.9 0.6 1.4 3.8 2.5 2.1 1.7 1.8 2.5 0.8 0.1 4.0 4.0 1.1 2.1 1.7 1.5 1.3 — 0.0 -100 MIN. MIN.MAX. MAX. -125 1.4 4.0 3.5 3.4 0.0 0.3 4.0 2.9 3.6 3.6 3.6 1.2 1.4 4.9 3.8 5.7 3.4 3.1 3.9 1.3 0.2 4.6 4.6 1.9 2.5 2.1 1.9 1.7 0.3 3.5 2.8 3.0 0.0 0.4 4.0 3.3 4.3 4.3 4.3 2.1 1.7 5.0 4.5 7.2 4.9 3.8 4.7 —0.3— 0.3 1.4 0.4 5.0 5.0 2.2 2.9 2.5 2.3 2.1

Specifications ispLSI 1024EA Internal Timing Parameters1 tob 1. Internal Timing Parameters are not tested and are for reference only. Table 2-0037A/1024EA v.2.5 Outputs UNITSDESCRIPTION#PARAM.

50 Output Buffer Delay ns

toen 52 I/O Cell OE to Output Enabled ns tgy0 55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk) ns Global Reset Clocks tgr 60 Global Reset to GLB and I/O Registers ns todis 53 I/O Cell OE to Output Disabled ns tgy1/2 56 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns tgcp 57 Clock Delay, Clock GLB to Global GLB Clock Line ns tioy2/3 58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line ns tiocp 59 Clock Delay, Clock GLB to I/O Cell Global Clock Line ns tgoe 54 Global OE ns tsl 51 Output Buffer Delay, Slew Limited Adder ns MIN. MAX. -200 0.9 0.9 0.8 0.0 0.8 0.9 3.1 0.9 0.0 3.1 0.9 1.8 0.0 1.4 5.0 -100 MIN. MIN.MAX. MAX. -125 1.1 0.9 0.8 0.0 0.8 2.0 5.1 1.9 5.1 1.5 1.8 0.0 2.8 3.9 5.0 5.1 1.9 1.5 0.8 0.0 0.8 1.7 4.0 1.1 4.0 0.9 1.8 0.0 2.82.8 3.0 5.0 2.1

Specifications ispLSI 1024EA ispLSI 1024EA Timing Model GLB Reg Delay I/O Pin (Output) ORP Delay 0491/1032EA Feedback#47 Reg 4 PT Bypass 20 PT XOR Delays Control PTs Input Register Clock Distribution I/O Pin (Input) Y1,2,3 D Q GRP4 GLB Reg Bypass ORP Bypass DQ RST RE OE CK I/O Reg Bypass I/O CellORPGLBGRPI/O Cell #23 - 27 #30 #35 #34 Comb 4 PT Bypass #36 - 38 #56 - 59 #44 - 46 #55 #54 #48 #49 Reset Ded. In GOE 0,1 #28 #22 RST #60 #60 #39 #40 - 43 #52, 53 #50, 51 GRP Loading Delay #29, 31 - 33 Derivations of tsu, th and tco from the Product Term Clock1 tsu Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) 1.6 7.4 0.8 1.4 7.2 th Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) Table 2-0042a/1024EA v.2.5 Derivations of tsu, th and tco from the Clock GLB1 tsu Logic + Reg (setup) - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) th Clock (max) + Reg (hold) - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) tco Clock (max) + Reg (clock-to-out) + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) 1. Calculations are based upon timing specifications for the ispLSI 1024EA-200.

conditions and the program in the device, the actual Icc should be verified. Figure 4. Typical Device Power Consumption vs fmax

Specifications ispLSI 1024EA Pin Description Input - Controls the operation of the ISP state machine. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Input/Output Pins - These are the general purpose I/O pins used by the logic array. NAME Table 2-0002A/1024EA Ground (GND)GND GOE 0/IN 41 GOE 1/IN 51 Input - Functions as an input pin to load programming data into the device and also used as one of the two control pins for the ispJTAG state machine. TDI TDO Output - Functions as an output pin to read serial shift register data. TCK Input - Functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.RESET Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. 1. Pins have dual function capability which is software selectable. 2. NC pins are not to be connected to any active signals, Vcc or GND. TQFP PIN NUMBERS VccVCC 25, 39, 52, 75, 88, 20, 28, 32, 43, 47, 55, 70, 78, 82, 93, 97, 15, 62, 11, 66, 12, 26, 49, 63, 76, 99, 21, 29, 33, 44, 48, 56, 71, 79, 83, 94, 98, 36, 89, 40, 85, 13, 27, 50, 64, 77, 100 22, 30, 34, 45, 53, 57, 72, 80, 84, 95, 37, 41, NC 2 No Connect Supply voltage for output drivers, 5V or 3.3V. VCCIO 24, 38, 51, 74, 87, 19, 23, 31, 42, 46, 54, 69, 73, 81, 92, 96, 14, 61, 10, 65,

Specifications ispLSI 1024EA 2NC 2NC I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 1GOE 1/IN 5 VCC VCC 2NC 2NC GND GND VCCIO RESET TDI I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 2NC 2NC NC 2 NC 2 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 TMS VCC VCC NC NC 2 GND GND TCK I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 NC NC 2 NC 2 NC 2 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GOE 0/IN 4 GND GND NC NC 2 VCC VCC I/O 35 I/O 34 I/O 33 I/O 32 I/O 31 I/O 30 I/O 29 NC NC 2 2NC 2NC I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 TDO GND GND 2NC 2NC VCC VCC I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 2NC 2NC 100 ispLSI 1024EA Top View 1. Pins have dual function capability which is software selectable. 2. NC pins are not to be connected to any active signal, VCC or GND. 100-TQFP/1024EA ispLSI 1024EA 100-Pin TQFP Pinout Diagram Pin Configurations

Specifications ispLSI 1024EA Part Number Description Device Number Grade Blank = Commercial 1024EA - XXX X XXXX X Speed Power L = Low Package T100 = 100-Pin TQFP Device Family 0212/1024EA ispLSI 200 = 200 MHz fmax 125 = 125 MHz fmax 100 = 100 MHz fmax ispLSI 1024EA Ordering Information 100 10 100-Pin TQFP ispLSI 1024EA-100LT100 Table 2-0041A/1024EA FAMILY fmax (MHz) ORDERING NUMBER PACKAGEtpd (ns) ispLSI 125 100-Pin TQFP7.5 ispLSI 1024EA-125LT100 200 100-Pin TQFP4.5 ispLSI 1024EA-200LT100 COMMERCIAL