XCVU37P

XCVU13P-1FHGB2104E AMD | Alldatasheet

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The Xilinx® Virtex® UltraScale+™ FPGAs are available in -3, -2, -1 speed grades, with -3E devices having the highest performance. The -2LE devices can operate at a VCCINT voltage at 0.85V or 0.72V and provide lower maximum static power. When operated at VCCINT = 0.85V, using -2LE devices, the speed specification for the L devices is the same as the -2I speed grade. When operated at VCCINT = 0.72V, the -2LE performance and static and dynamic power is reduced. DC and AC char act eristics are specified in extended (E), industrial (I), and military (M) temperature ranges. Except the oper ating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing char act eristics of a -1 speed grade extended device are the same as for a -1 speed grade industrial device). However, only selected speed grades and/or devices are available in each temperature range. The XQ references in this data sheet are specific to the devices available in XQ Ruggedized packages. See the Defense-Grade UltraScale Architecture Data Sheet: Overview (DS895) for further in f ormation on XQ Defense- grade part numbers, packages, and ordering in f ormation. All supply voltage and junction temperature specifications are r epr esen tativ e of worst-case c onditions. The parameters included are common to popular designs and typical applications. This data sheet, part of an overall set of documen tation on the Virtex UltraScale+ FPGAs, is available on the Xilinx website at www .xilinx.c om/ documen tation . DC Characteristics Absolute Maximum Ratings Table 1: Absolute Maximum Ratings Symbol Description1 Min Max Units FPGA Logic VCCINT Internal supply voltage –0.500 1.000 V VCCINT_IO2 Internal supply voltage for the I/O banks –0.500 1.000 V VCCAUX Auxiliary supply voltage –0.500 2.000 V Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 Product Specification © Copyright 2016–2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 1 Send Feedback

Table 1: Absolute Maximum Ratings (cont'd) Symbol Description1 Min Max Units VCCBRAM Supply voltage for the block RAM memories –0.500 1.000 V VCCO Output drivers supply voltage for HP I/O banks –0.500 2.000 V VCCAUX_IO3 Auxiliary supply voltage for the I/O banks –0.500 2.000 V VREF Input reference voltage –0.500 2.000 V VIN4, 5, 6 I/O input voltage for HP I/O banks –0.550 VCCO + 0.550 V VBATT Key memory battery backup supply –0.500 2.000 V IDC Available output current at the pad –20 20 mA IRMS Available RMS output current at the pad –20 20 mA High Bandwidth Memory (HBM) VCC_HBM Supply voltage for the high-bandwidth memory –0.300 1.500 V VCC_IO_HBM I/O supply voltage for the high-bandwidth memory –0.300 1.500 V VCCAUX_HBM Auxiliary supply voltage for the high-bandwidth memory –0.300 3.000 V GTY or GTM Transceiver7 VCCINT_GT Digital supply voltage for select modules in the GTM transceivers –0.500 1.000 V VMGTAVCC Analog supply voltage for transceiver circuits –0.500 1.000 V VMGTAVTT Analog supply voltage for transceiver termination circuits –0.500 1.300 V VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for transceivers –0.500 1.900 V VMGTREFCLK Transceiver reference clock absolute input voltage –0.500 1.300 V VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the transceiver column –0.500 1.300 V VIN Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage –0.500 1.200 V IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating8 – 10 mA IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT – 10 mA IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND9 – 0 mA IDCIN-PROG DC input current for receiver input pins DC coupled RX termination = programmable10 – 0 mA IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating – 6 mA IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT – 6 mA System Monitor VCCADC System Monitor supply relative to GNDADC –0.500 2.000 V VREFP System Monitor reference input relative to GNDADC –0.500 2.000 V Temperature11 TSTG Storage temperature for XCVU31P, XCVU33P, XCVU35P, XCVU37P12 –55 120 °C Storage temperature (ambient) for all other devices –65 150 °C TSOL Maximum dry rework soldering temperature – 260 °C Maximum reflow soldering temperature for FFVC1517, FLGF1924, FHGA2104, FHGB2104, FHGC2104, FLGA2104, FLGB2104, FLGC2104, FLVA2104, FLVB2104, FLVC2104, FLGA2577 – 245 °C Maximum reflow soldering temperature for lidless packages with stiffener ring (FIGD2104, FSGD2104, FSVH1924, FSVH2104, FSGA2577, FSVH2892) – 240 °C Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 2 Send Feedback

Table 1: Absolute Maximum Ratings (cont'd) Symbol Description1 Min Max Units Tj Maximum junction temperature for XCVU31P, XCVU33P, XCVU35P, XCVU37P – 120 °C Maximum junction temperature for all other devices – 125 °C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. V CCINT_IO must be connected to VCCBRAM. 3. V CCAUX_IO must be connected to VCCAUX. 4. The lower absolute voltage specification always applies. 5. For I/O operation, see the UltraScale Architecture SelectIO Resources User Guide (UG571). 6. When operating outside of the recommended operating conditions, refer to Table 4 for maximum overshoot and undershoot specifications. 7. For more information on supported GTY transceiver terminations see the UltraScale Architecture GTY Transceivers User Guide (UG578) or Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581). 8. AC coupled operation is not supported for RX termination = floating. 9. For GTY transceivers, DC coupled operation is not supported for RX termination = GND. 10. DC coupled operation is not supported for RX termination = programmable. 11. For soldering guidelines and thermal considerations, see the UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575). 12. For devices with high-bandwidth memory (HBM), the storage temperature is the case surface temperature on the center/top side of the device. For the measurement conditions, refer to the JESD51-2 standard. Recommended Operating Conditions Table 2: Recommended Operating Conditions Symbol Description1, 2 Min Typ Max Units FPGA Logic VCCINT Internal supply voltage 0.825 0.850 0.876 V For -2LE (VCCINT = 0.72V) devices: internal supply voltage 0.698 0.720 0.742 V For -3E devices: internal supply voltage 0.873 0.900 0.927 V VCCINT_IO3 Internal supply voltage for the I/O banks 0.825 0.850 0.876 V For -2LE (VCCINT = 0.72V) devices: internal supply voltage for the I/O banks 0.825 0.850 0.876 V For -3E devices: internal supply voltage for the I/O banks 0.873 0.900 0.927 V VCCBRAM Block RAM supply voltage 0.825 0.850 0.876 V For -3E devices: block RAM supply voltage 0.873 0.900 0.927 V VCCAUX Auxiliary supply voltage 1.746 1.800 1.854 V VCCO4, 5 Supply voltage for I/O banks 0.950 – 1.900 V VCCAUX_IO6 Auxiliary I/O supply voltage 1.746 1.800 1.854 V VIN7 I/O input voltage –0.200 – VCCO + 0.200 V IIN8 Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode – – 10 mA VBATT9 Battery voltage 1.000 – 1.890 V High Bandwidth Memory VCC_HBM Supply voltage for the high-bandwidth memory (HBM) 1.164 1.200 1.236 V Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 3 Send Feedback

Table 2: Recommended Operating Conditions (cont'd) Symbol Description1, 2 Min Typ Max Units VCC_IO_HBM I/O supply voltage for the high-bandwidth memory 1.164 1.200 1.236 V VCCAUX_HBM Auxiliary supply voltage for the high-bandwidth memory 2.425 2.500 2.575 V GTY or GTM Transceiver VCCINT_GT Digital supply voltage for select modules in the GTM transceivers 0.825 0.850 0.876 V For -3E devices: Digital supply voltage for select modules in the GTM transceivers supply voltage 0.873 0.900 0.927 V VMGTAVCC10 Analog supply voltage for the GTY or GTM transceiver 0.873 0.900 0.927 V VMGTAVTT10 Analog supply voltage for the GTY or GTM transmitter and receiver termination circuits 1.164 1.200 1.236 V VMGTVCCAUX10 Auxiliary analog QPLL voltage supply for the transceivers 1.746 1.800 1.854 V VMGTAVTTRCAL10 Analog supply voltage for the resistor calibration circuit of the GTY or GTM transceiver column 1.164 1.200 1.236 V System Monitor VCCADC System Monitor supply relative to GNDADC 1.746 1.800 1.854 V VREFP System Monitor externally supplied reference voltage relative to GNDADC 1.200 1.250 1.300 V Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 4 Send Feedback

Table 2: Recommended Operating Conditions (cont'd) Symbol Description1, 2 Min Typ Max Units Temperature Tj11 Junction temperature operating range for XCVU31P, XCVU33P, XCVU35P, and XCVU37P extended (E) temperature devices12, 13, 0 – 100 °C Junction temperature operating range for all other extended (E) temperature devices12 0 – 100 °C Junction temperature operating range for industrial (I) temperature devices –40 – 100 °C Junction temperature operating range for eFUSE programming15 –40 – 125 °C Notes: 1. All voltages are relative to GND. 2. For the design of the power distribution system consult the UltraScale Architecture PCB Design User Guide (UG583). 3. V CCINT_IO must be connected to VCCBRAM. 4. For V CCO_0, the minimum recommended operating voltage for power on and during configuration is 1.425V. After configuration, data is retained even if VCCO drops to 0V. 6. V CCAUX_IO must be connected to VCCAUX. 7. The lower absolute voltage specification always applies. 8. A total of 200 mA per bank should not be exceeded. 9. If battery is not used, connect V BATT to either GND or VCCAUX. 10. Each voltage listed requires filtering as described in the UltraScale Architecture GTY Transceivers User Guide (UG578) or the Virtex UltraScale + FPGAs GTM Transceivers User Guide (UG581). 11. Xilinx recommends measuring the T j of a device using the system monitor as described in the UltraScale Architecture System Monitor User Guide (UG580). The system monitor temperature measurement errors (that are described in Table 74) must be accounted for in your design. For example, when using the system monitor with an external reference of 1.25V, and when the system monitor reports 97°C, there is a measurement error ±3°C. A reading of 97°C is considered the maximum adjusted Tj (100°C – 3°C = 97°C). 12. Devices labeled with the speed/temperature grade of -2LE can operate for a limited time at a junction temperature between 100°C and 110°C. Timing parameters adhere to the same speed file at 110°C as they do below 110°C, regardless of operating voltage (nominal voltage of 0.85V or a low-voltage of 0.72V). Operation up to Tj = 110°C is limited to 1% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does not exceed 1% of the device lifetime. 13. The recommended maximum operating temperature for high-bandwidth memory is 95°C. 14. Devices with HBM and labeled with the speed/temperature grade of -2LE can operate for a limited time at a junction temperature between 95°C and 105°C. HBM operation up to Tj = 105°C is limited to 4.1% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does not exceed 4.1% of the device lifetime, and for no longer than 96 hours at a time. While operating the HBM above 95°C, the refresh rate must be at least 4x the refresh rate at 95°C. 15. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is active). DC Characteristics Over Recommended Operating Conditions Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ1 Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.68 – – V VDRAUX Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 – – V IREF VREF leakage current per pin – – 15 µA IL Input or output leakage current per pin (sample-tested)2 – – 15 µA CIN3 Die input capacitance at the pad – – 3.1 pF Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 5 Send Feedback

Table 3: DC Characteristics Over Recommended Operating Conditions (cont'd) Symbol Description Min Typ1 Max Units IRPU Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V 60 – 120 µA Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V 30 – 120 µA Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V 10 – 100 µA IRPD Pad pull-down (when selected) at VIN = 1.8V 29 – 120 µA ICCADCON Analog supply current for the SYSMON circuits in the power-up state – – 8 mA ICCADCOFF Analog supply current for the SYSMON circuits in the power-down state – – 1.5 mA IBATT4, 5 Battery supply current at VBATT = 1.89V – – 650 nA Battery supply current at VBATT = 1.20V – – 150 nA IPFS6 VCCAUX additional supply current during eFUSE programming – – 115 mA Calibrated programmable on-die termination (DCI) in I/O banks7 (measured per JEDEC specification) R9 Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_40 –10%8 40 +10%8 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –10%8 48 +10%8 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_60 –10%8 60 +10%8 Ω Programmable input termination to VCCO where ODT = RTT_40 –10%8 40 +10%8 Ω Programmable input termination to VCCO where ODT = RTT_48 –10%8 48 +10%8 Ω Programmable input termination to VCCO where ODT = RTT_60 –10%8 60 +10%8 Ω Programmable input termination to VCCO where ODT = RTT_120 –10%8 120 +10%8 Ω Programmable input termination to VCCOwhere ODT = RTT_240 –10%8 240 +10%8 Ω Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification) R9 Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_40 –50% 40 +50% Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –50% 48 +50% Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_60 –50% 60 +50% Ω Programmable input termination to VCCO where ODT = RTT_40 –50% 40 +50% Ω Programmable input termination to VCCO where ODT = RTT_48 –50% 48 +50% Ω Programmable input termination to VCCO where ODT = RTT_60 –50% 60 +50% Ω Programmable input termination to VCCO where ODT = RTT_120 –50% 120 +50% Ω Programmable input termination to VCCO where ODT = RTT_240 –50% 240 +50% Ω Internal VREF 50% VCCO VCCO x 0.49 VCCO x 0.50 VCCO x 0.51 V 70% VCCO VCCO x 0.69 VCCO x 0.70 VCCO x 0.71 V Differential termination Programmable differential termination (TERM_100) for HP I/O banks –35% 100 +35% Ω n Temperature diode ideality factor – 1.026 – – Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 6 Send Feedback

Table 3: DC Characteristics Over Recommended Operating Conditions (cont'd) Symbol Description Min Typ1 Max Units r Temperature diode series resistance – 2 – Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. For the I/O banks with a V CCO of 1.8V and separated VCCO and VCCAUX_IO power supplies, the IL maximum current is 70 µA. 3. This measurement represents the die capacitance at the pad, not including the package. 4. Maximum value specified for worst case process at 25°C. For the XCVU5P, XCVU7P, XCVU9P, XCVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU35P, and XCVU37P devices, multiply the value by the number of super-logic regions (SLRs) in the device. 5. I BATT is measured when the battery-backed RAM (BBRAM) is enabled. 6. Do not program eFUSE during device configuration (e.g., during configuration, during configuration readback, or when readback CRC is active). 7. VRP resistor tolerance is (240Ω ±1%). 8. If VRP resides at a different bank (DCI cascade), the range increases to ±15%. 9. On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide (UG571). VIN Maximum Allowed AC Voltage Overshoot and Undershoot Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks AC Voltage Overshoot1 % of UI2 at –40°C to 100°C AC Voltage Undershoot1 % of UI2 at –40°C to 100°C VCCO + 0.30 100% –0.30 100% VCCO + 0.35 100% –0.35 100% VCCO + 0.40 92% –0.40 92% VCCO + 0.45 50% –0.45 50% VCCO + 0.50 20% –0.50 20% VCCO + 0.55 10% –0.55 10% Notes: 1. A total of 200 mA per bank should not be exceeded. 2. For UI smaller than 20 µs. 3. For the -1M devices, the temperature limits are –55°C to 125°C. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 7 Send Feedback

Table 5: Typical Quiescent Supply Current Symbol Description1, 2, 3 Device Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 ICCINTQ Quiescent VCCINT supply current XCVU3P 2384 2276 2276 2017 mA XCVU5P 4769 4552 4552 4034 mA XCVU7P 4769 4552 4552 4034 mA XCVU9P 7153 6828 6828 6050 mA XCVU11P 7567 7202 7202 6332 mA XCVU13P 10090 9602 9602 8442 mA XCVU31P 2528 2406 2406 2115 mA XCVU33P 2528 2406 2406 2115 mA XCVU35P 5051 4807 4807 4226 mA XCVU37P 7573 7207 7207 6336 mA XCVU27P 9962 9516 9516 8449 mA XCVU29P 9962 9516 9516 8449 mA ICCINT_IOQ Quiescent VCCINT_IO supply current XCVU3P 149 144 144 144 mA XCVU5P 298 287 287 287 mA XCVU7P 298 287 287 287 mA XCVU9P 447 431 431 431 mA XCVU11P 182 176 176 176 mA XCVU13P 243 234 234 234 mA XCVU31P 747 723 723 723 mA XCVU33P 747 723 723 723 mA XCVU35P 776 750 750 750 mA XCVU37P 804 778 778 778 mA XCVU27P 241 232 232 232 mA XCVU29P 241 232 232 232 mA ICCOQ Quiescent VCCO supply current All devices 1 1 1 1 mA ICCAUXQ Quiescent VCCAUX supply current XCVU3P 268 268 268 268 mA XCVU5P 535 535 535 535 mA XCVU7P 535 535 535 535 mA XCVU9P 1015 1015 1015 1015 mA XCVU11P 819 819 819 819 mA XCVU13P 1091 1091 1091 1091 mA XCVU31P 223 223 223 223 mA XCVU33P 223 223 223 223 mA XCVU35P 444 444 444 444 mA XCVU37P 665 665 665 665 mA XCVU27P 1091 1091 1091 1091 mA XCVU29P 1091 1091 1091 1091 mA Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 8 Send Feedback

Table 5: Typical Quiescent Supply Current (cont'd) Symbol Description1, 2, 3 Device Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 ICCAUX_IOQ Quiescent VCCAUX_IO supply current XCVU3P 62 62 62 62 mA XCVU5P 124 124 124 124 mA XCVU7P 124 124 124 124 mA XCVU9P 187 187 187 187 mA XCVU11P 79 79 79 79 mA XCVU13P 105 105 105 105 mA XCVU31P 27 27 27 27 mA XCVU33P 27 27 27 27 mA XCVU35P 53 53 53 53 mA XCVU37P 80 80 80 80 mA XCVU27P 105 105 105 105 mA XCVU29P 105 105 105 105 mA ICCBRAMQ Quiescent VCCBRAM supply current XCVU3P 45 43 43 43 mA XCVU5P 90 85 85 85 mA XCVU7P 90 85 85 85 mA XCVU9P 134 128 128 128 mA XCVU11P 130 124 124 124 mA XCVU13P 174 165 165 165 mA XCVU31P 43 41 41 41 mA XCVU33P 43 41 41 41 mA XCVU35P 87 83 83 83 mA XCVU37P 130 124 124 124 mA XCVU27P 174 165 165 165 mA XCVU29P 174 165 165 165 mA Notes: 1. Typical values are specified at nominal voltage, 85°C junction temperatures (T j) with single-ended SelectIO™ resources. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, and all I/O pins are 3-state and floating. 3. Use the Xilinx ® Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for conditions or supplies other than those specified. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 9 Send Feedback

Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, VCCINT_IO/VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended po w er -o ff sequence is the reverse of the power-on sequence. If VCCINT and VCCINT_IO/VCCBRAM have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCINT_IO must be connected to VCCBRAM. If VCCAUX/VCCAUX_IO and VCCO have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. VCCAUX and VCCAUX_IO must be connected together. VCCADC and VREF can be powered at any time and have no power-up sequencing requirements. For devices with HBM, the HBM power supplies can be powered on/ o ff after or in-parallel with the core power supplies. The required power-on sequence is VCCAUX_HBM and VCCINT_IO followed by VCC_HBM/VCC_IO_HBM. VCC_IO_HBM must be connected to VCC_HBM. VCCAUX_HBM must be equal to or higher than VCC_HBM at all times. The recommended po w er -o ff sequence is the reverse of the power-on sequence. The recommended power-on sequence to achieve minimum current draw for the GTY or GTM transceivers is VCCINT, VCCINT_GT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VCCINT_GT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended po w er -o ff sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power-up and power-down. Power Supply Requirements Table 6 shows the minimum current, in addition to ICCQ maximum, required by each Virtex UltraScale+ FPGA for proper power-on and c on figur ation. If these current minimums are met, the device powers on after all supplies have passed through their power-on reset threshold voltages. The device must not be c on figur ed un til after VCCINT is applied. Once initializ ed and c on figur ed, use the Xilinx Power E stimat or (XPE) tools to estimat e current drain on these supplies. The XPE spreadsheet tool (download at h ttp:/ /www .xilinx.c om/ po w er ) is also used to estimat e power-on current for all supplies. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 10 Send Feedback

Table 6: Power-on Current by Device Device ICCINTMIN ICCINT_IOMIN + ICCBRAMMIN ICCOMIN ICCAUXMIN + ICCAUX_IOMIN Units XCVU3P, XQVU3P ICCINTQ + 2000 ICCBRAMQ + ICCINT_IOQ + 670 ICCOQ + 50 ICCAUXQ + ICCAUX_IOQ + 350 mA XCVU5P ICCINTQ + 4000 ICCBRAMQ + ICCINT_IOQ + 1340 ICCOQ + 100 ICCAUXQ + ICCAUX_IOQ + 700 mA XCVU7P, XQVU7P ICCINTQ + 4000 ICCBRAMQ + ICCINT_IOQ + 1340 ICCOQ + 100 ICCAUXQ + ICCAUX_IOQ + 700 mA XCVU9P ICCINTQ + 6000 ICCBRAMQ + ICCINT_IOQ + 2010 ICCOQ + 150 ICCAUXQ + ICCAUX_IOQ + 1050 mA XCVU11P, XQVU11P ICCINTQ + 6549 ICCBRAMQ + ICCINT_IOQ + 2194 ICCOQ + 164 ICCAUXQ + ICCAUX_IOQ + 1146 mA XCVU13P ICCINTQ + 8731 ICCBRAMQ + ICCINT_IOQ + 2925 ICCOQ + 219 ICCAUXQ + ICCAUX_IOQ + 1528 mA XCVU27P mA XCVU29P mA XCVU31P ICCINTQ + 2232 ICCBRAMQ + ICCINT_IOQ + 2500 ICCOQ + 56 ICCAUXQ + ICCAUX_IOQ + 500 mA XCVU33P ICCINTQ + 2232 ICCBRAMQ + ICCINT_IOQ + 2500 ICCOQ + 56 ICCAUXQ + ICCAUX_IOQ + 500 mA XCVU35P ICCINTQ + 4424 ICCBRAMQ + ICCINT_IOQ + 3537 ICCOQ + 111 ICCAUXQ + ICCAUX_IOQ + 882 mA XCVU37P ICCINTQ + 6617 ICCBRAMQ + ICCINT_IOQ + 4574 ICCOQ + 166 ICCAUXQ + ICCAUX_IOQ + 1264 mA Table 7: Power Supply Ramp Time Symbol Description Min Max Units TVCCINT Ramp time from GND to 95% of VCCINT 0.2 40 ms TVCCINT_IO Ramp time from GND to 95% of VCCINT_IO 0.2 40 ms TVCCO Ramp time from GND to 95% of VCCO 0.2 40 ms TVCCAUX Ramp time from GND to 95% of VCCAUX 0.2 40 ms TVCCBRAM Ramp time from GND to 95% of VCCBRAM 0.2 40 ms TVCC_HBM Ramp time from GND to 95% of VCC_HBM 0.2 40 ms TVCC_IO_HBM Ramp time from GND to 95% of VCC_IO_HBM 0.2 40 ms TVCCAUX_HBM Ramp time from GND to 95% of VCCAUX_HBM 0.2 40 ms TMGTAVCC Ramp time from GND to 95% of VMGTAVCC 0.2 40 ms TMGTAVTT Ramp time from GND to 95% of VMGTAVTT 0.2 40 ms TMGTVCCAUX Ramp time from GND to 95% of VMGTVCCAUX 0.2 40 ms DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended oper ating c onditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the r espectiv e VOL and VOH voltage levels shown. Other standards are sample tested. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 11 Send Feedback

Table 8: SelectIO DC Input and Output Levels for I/O Banks I/O Standard1, 2, 3 VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 4 Note 4 LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5 LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5 Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). 3. POD10 and POD12 DC input and output levels are shown in Table 9, Table 13, and Table 14. 4. Supported drive strengths of 2, 4, 6, or 8 mA in I/O banks. 5. Supported drive strengths of 2, 4, 6, 8, or 12 mA in I/O banks. 6. Low-power option for MIPI_DPHY_DCI. Table 9: DC Input Levels for Single-ended POD10 and POD12 I/O Standards I/O Standard1, 2 VIL VIH V, Min V, Max V, Min V, Max POD10 –0.300 VREF – 0.068 VREF + 0.068 VCCO + 0.300 POD12 –0.300 VREF – 0.068 VREF + 0.068 VCCO + 0.300 Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 12 Send Feedback

Table 10: Differential SelectIO DC Input and Output Levels I/O Standard VICM (V)1 VID (V)2 VILHS3 VIHHS3 VOCM (V)4 VOD (V)5 Min Typ Max Min Typ Max Min Max Min Typ Max Min Typ Max MIPI_DPHY_ DCI_HS7 Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage (Q – Q). 3. V IHHS and VILHS are the single-ended input high and low voltages, respectively. 4. V OCM is the output common mode voltage. 5. V OD is the output differential voltage (Q – Q). 6. LVDS is specified in Table 15. 7. High-speed option for MIPI_DPHY_DCI. The V ID maximum is aligned with the standard’s specification. A higher VID is acceptable as long as the VIN specification is also met. Table 11: Complementary Differential SelectIO DC Input and Output Levels for I/O Banks I/O Standard1 VICM (V)2 VID (V)3 VOL (V)4 VOH (V)5 IOL IOH Min Typ Max Min Max Max Min mA mA Notes: 1. DIFF_POD10 and DIFF_POD12 HP I/O bank specifications are shown in Table 12, Table 13, Table 14. 2. V ICM is the input common mode voltage. 3. V ID is the input differential voltage. 4. V OL is the single-ended low-output voltage. 5. V OH is the single-ended high-output voltage. Table 12: DC Input Levels for Differential POD10 and POD12 I/O Standards I/O Standard1, 2 VICM (V) VID (V) Min Typ Max Min Max DIFF_POD10 0.63 0.70 0.77 0.14 – DIFF_POD12 0.76 0.84 0.92 0.16 – Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 13 Send Feedback

Table 13: DC Output Levels for Single-ended and Differential POD10 and POD12 Standards Symbol Description1, 2 VOUT Min Typ Max Units ROL Pull-down resistance VOM_DC (as described in Table 14) 36 40 44 Ω ROH Pull-up resistance VOM_DC (as described in Table 14) 36 40 44 Ω Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O standard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). Table 14: Definitions for DC Output Levels for Single-ended and Differential POD10 and POD12 Standards Symbol Description All Speed Grades Units VOM_DC DC output Mid measurement level (for IV curve linearity) 0.8 x VCCO V LVDS DC Specifications (LVDS) Table 15: LVDS DC Specifications Symbol DC Parameter Conditions Min Typ Max Units VCCO1 Supply voltage 1.710 1.800 1.890 V VODIFF2 Differential output voltage: (Q – Q), Q = High (Q – Q), Q = High RT = 100Ω across Q and Q signals 247 350 454 mV VOCM2 Output common-mode voltage RT = 100Ω across Q and Q signals 1.000 1.250 1.425 V VIDIFF3 Differential input voltage: (Q – Q), Q = High (Q – Q), Q = High 100 350 6003 mV VICM_DC4 Input common-mode voltage (DC coupling) 0.300 1.200 1.425 V VICM_AC5 Input common-mode voltage (AC coupling) 0.600 – 1.100 V Notes: 1. In I/O banks, when LVDS is used with input-only functionality, it can be placed in a bank where the V CCO levels are different from the specified level only if internal differential termination is not used. In this scenario, VCCO must be chosen to ensure the input pin voltage levels do not violate the Recommended Operating Condition (Table 2) specification for the VIN I/O pin voltage. 2. V OCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE. 3. Maximum V IDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained. 4. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default). 5. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4. AC Switching Characteristics All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite as outlined in the following table. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 14 Send Feedback

Table 16: Speed Specification Version By Device

2018.3.1 Device

1.23 XCVU3P, XCVU7P, XCVU9P, XCVU5P, XCVU11P, XCVU13P

XQVU3P, XQVU7P, XQVU11P

1.01 XCVU27P, XCVU29P

1.24 XCVU31P, XCVU33P, XCVU35P, XCVU37P

Switching char act eristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or P r oduction. Each designation is de fined as follows:

• Advance Product S pecification: These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered r elativ ely stable and c onserv ativ e, some under -r eporting might still occur.
• Preliminary Product S pecification: These specifications are based on complete ES (engineering sample) silicon char act erization. Devices and speed grades with this designation are intended to give a be tter indication of the expected performance of pr oduction silicon. The probability of under -r eporting delays is greatly reduced as compared to Advance data.
• Product S pecification: These specifications are released once enough pr oduction silicon of a particular device family member has been characterized to provide full c orr elation between specifications and devices over numerous pr oduction lots. There is no under -r eporting of delays, and customers receive formal no tification of any subsequent changes. Typically, the slowest speed grades tr ansition to pr oduction before faster speed grades. Testing of AC Switching Characteristics Internal timing parameters are derived from measuring internal test patterns. All AC switching char act eristics are r epr esen tativ e of worst-case supply voltage and junction temperature c onditions. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex UltraScale+ FPGAs. Speed Grade Designations Because individual family members are produced at differ en t times, the migr ation from one category to another depends completely on the status of the f abrication process for each device. Table 17 correlates the current status of the Virtex UltraScale+ FPGA on a per speed grade basis. Table 17: Speed Grade Designations by Device Device Speed Grade, Temperature Ranges, and VCCINT Operating Voltages Advance Preliminary Production XCVU3P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V) -1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 15 Send Feedback

Table 17: Speed Grade Designations by Device (cont'd) Device Speed Grade, Temperature Ranges, and VCCINT Operating Voltages Advance Preliminary Production XCVU5P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V) -1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 XCVU7P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V) -1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 XCVU9P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V) -1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 XCVU11P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V) -1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 XCVU13P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V), -2I (VCCINT = 0.85V) -1E (VCCINT = 0.85V), -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 XCVU27P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V) -2I (VCCINT = 0.85V) -1E (VCCINT = 0.85V) -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V) -2LE (VCCINT = 0.72V)1 XCVU29P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V) -2I (VCCINT = 0.85V) -1E (VCCINT = 0.85V) -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V) -2LE (VCCINT = 0.72V)1 XCVU31P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V) -2LE (VCCINT = 0.85V) -1E (VCCINT = 0.85V) -2LE (VCCINT = 0.72V)1 XCVU33P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V) -2LE (VCCINT = 0.85V) -1E (VCCINT = 0.85V) -2LE (VCCINT = 0.72V)1 XCVU35P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V) -2LE (VCCINT = 0.85V) -1E (VCCINT = 0.85V) -2LE (VCCINT = 0.72V)1 Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 16 Send Feedback

Table 17: Speed Grade Designations by Device (cont'd) Device Speed Grade, Temperature Ranges, and VCCINT Operating Voltages Advance Preliminary Production XCVU37P -3E (VCCINT = 0.90V) -2E (VCCINT = 0.85V) -2LE (VCCINT = 0.85V) -1E (VCCINT = 0.85V) -2LE (VCCINT = 0.72V)1 XQVU3P -2I (VCCINT = 0.85V) -1I (VCCINT = 0.85V), -1M (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 XQVU7P -2I (VCCINT = 0.85V) -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 XQVU11P -2I (VCCINT = 0.85V) -1I (VCCINT = 0.85V) -2LE (VCCINT = 0.85V), -2LE (VCCINT = 0.72V)1 Notes: 1. The lowest power -2L devices, where V CCINT = 0.72V, are listed in the Vivado Design Suite as -2LV. Production Silicon and Software Status In some cases, a particular family member (and speed grade) is released to pr oduction before a speed specification is released with the correct label (Advance, Preliminary, P r oduction ). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 18 lists the pr oduction released Virtex UltraScale+ FPGA, speed grade, and the minimum corresponding supported speed specification version and Vivado so ftw ar e revisions. The Vivado so ftw ar e and speed specifications listed are the minimum releases required for pr oduction. All subsequent releases of so ftw ar e and speed specifications are valid. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 17 Send Feedback

Table 18: Virtex UltraScale+ FPGA Device Production Software and Speed Specification Release Device Speed Grade and VCCINT Operating Voltages1 0.90V 0.85V 0.72V -3 -2 -1 -2L -2L XCVU3P Vivado tools 2018.1 v1.19 XCVU5P Vivado tools 2018.1 v1.19 XCVU7P Vivado tools 2018.1 v1.19 XCVU9P Vivado tools 2018.1 v1.19 XCVU11P Vivado tools 2017.4.1 v1.18 XCVU13P Vivado tools 2017.4.1 v1.18 XCVU27P XCVU29P XQVU3P N/A Vivado tools 2018.3 v1.23 Vivado tools 2018.3 v1.23 Notes: 1. Blank entries indicate a device and/or speed grade in Advance or Preliminary status. FPGA Logic Performance Characteristics This section provides the performance char act eristics of some common functions and designs implemented in the Virtex UltraScale+ FPGAs. These values are subject to the same guidelines as the AC Switching Char act eristics section. In LVDS component mode:

• For the input/output registers in HP I/O banks, the Vivado tools limit clock frequencies to 312.9 MHz for all speed grades.
• For IDDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.
• For ODDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 18 Send Feedback

Table 19: LVDS Component Mode Performance

Description

Speed Grade and VCCINT Operating Voltages Units 0.90V 0.85V 0.72V -3 -2 -1 -2 Min Max Min Max Min Max Min Max LVDS TX DDR (OSERDES 4:1, 8:1) 0 1250 0 1250 0 1250 0 1250 Mb/s LVDS TX SDR (OSERDES 2:1, 4:1) 0 625 0 625 0 625 0 625 Mb/s LVDS RX DDR (ISERDES 1:4, 1:8)1 0 1250 0 1250 0 1250 0 1250 Mb/s LVDS RX SDR (ISERDES 1:2, 1:4)1 0 625 0 625 0 625 0 625 Mb/s Notes: 1. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing. Table 20: LVDS Native Mode Performance Description1, 2 DATA_WIDTH Speed Grade and VCCINT Operating Voltages Units 0.90V 0.85V 0.72V -3 -2 -1 -2 Min Max Min Max Min Max Min Max LVDS TX DDR (TX_BITSLICE) 4 375 1600 375 1600 375 1600 375 1400 Mb/s 8 375 1600 375 1600 375 1600 375 1600 Mb/s LVDS TX SDR (TX_BITSLICE) 4 187.5 800 187.5 800 187.5 800 187.5 700 Mb/s 8 187.5 800 187.5 800 187.5 800 187.5 800 Mb/s LVDS RX DDR (RX_BITSLICE)3 4 375 16004 375 16004 375 16004 375 14004 Mb/s 8 375 16004 375 16004 375 16004 375 16004 Mb/s LVDS RX SDR (RX_BITSLICE)3 4 187.5 800 187.5 800 187.5 800 187.5 700 Mb/s 8 187.5 800 187.5 800 187.5 800 187.5 800 Mb/s Notes: 1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. The performance values assume a source-synchronous interface. 2. PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the minimum frequency is PLL_FVCOMIN/2. 3. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing. 4. Asynchronous receiver performance is limited to 1300 Mb/s for -3/-2 speed grades and to 1250 Mb/s for -1 speed grades. Table 21: MIPI D-PHY Performance Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 MIPI D-PHY transmitter or receiver 1500 1500 1260 1260 Mb/s Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 19 Send Feedback

Table 22: LVDS Native-Mode 1000BASE-X Support Description1 Speed Grade and VCCINT Operating Voltages 0.90V 0.85V 0.72V -3 -2 -1 -2 1000BASE-X Yes Notes: 1. 1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE Std 802.3-2008). The following table provides the maximum data rates for applicable memory standards using the Virtex UltraScale+ FPGA memory PHY. Refer to Memory Interfaces for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale Architecture PCB Design User Guide (UG583), electrical analysis, and char act erization of the system. Table 23: Maximum Physical Interface (PHY) Rate for Memory Interfaces Memory Standard DRAM Type Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 DDR4 Single rank component 2666 2666 2400 2400 Mb/s 1 rank DIMM1, 2, 3 2400 2400 2133 2133 Mb/s 2 rank DIMM1, 4 2133 2133 1866 1866 Mb/s 4 rank DIMM1, 5 1600 1600 1333 1333 Mb/s DDR3 Single rank component 2133 2133 2133 2133 Mb/s 1 rank DIMM1, 2 1866 1866 1866 1866 Mb/s 2 rank DIMM1, 4 1600 1600 1600 1600 Mb/s 4 rank DIMM1, 5 1066 1066 1066 1066 Mb/s DDR3L Single rank component 1866 1866 1866 1866 Mb/s 1 rank DIMM1, 2 1600 1600 1600 1600 Mb/s 2 rank DIMM1, 4 1333 1333 1333 1333 Mb/s 4 rank DIMM1, 5 800 800 800 800 Mb/s QDR II+ Single rank component6 633 633 600 600 MHz RLDRAM 3 Single rank component 1200 1200 1066 1066 MHz QDR IV XP Single rank component 1066 1066 1066 933 MHz LPDDR3 Single rank component 1600 1600 1600 1600 Mb/s Notes: 1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM. 2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot. 3. For the DDR4 DDP components at -3 and -2 (V CCINT = 0.85V) speed grades, the maximum data rate is 2133 Mb/s for six or more DDP devices. For five or less DDP devices, use the single rank DIMM data rates for the -3 and -2 (VCCINT = 0.85V) speed grades. 4. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot. 5. Includes: 2 rank 2 slot, 4 rank 1 slot. 6. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 20 Send Feedback

FPGA Logic Switching Characteristics The following IOB high-performance (HP) table summarizes the values of standar d-specific data input delay adjustments, output delays t erminating at pads (based on standard) and 3-state delays.

• TINBUF_DELAY_PAD_I is the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer .
• TOUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer .
• TOUTBUF_DELAY_TD_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer . In I/O banks, the internal DCI t ermination turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the DCITERMDISABLE pin is used. IOB High Performance (HP) Switching Characteristics Table 24: IOB High Performance (HP) Switching Characteristics I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 21 Send Feedback

Table 24: IOB High Performance (HP) Switching Characteristics (cont'd) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 22 Send Feedback

Table 24: IOB High Performance (HP) Switching Characteristics (cont'd) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 23 Send Feedback

Table 24: IOB High Performance (HP) Switching Characteristics (cont'd) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 24 Send Feedback

Table 24: IOB High Performance (HP) Switching Characteristics (cont'd) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD SLVS_400_18 0.492 0.539 0.620 0.539 N/A N/A N/A N/A N/A N/A N/A N/A ns IOB 3-state Output Switching Characteristics Table 25 specifies the values of TOUTBUF_DELAY_TE_PAD and TINBUF_DELAY_IBUFDIS_O. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 25 Send Feedback

• TOUTBUF_DELAY_TE_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
• TINBUF_DELAY_IBUFDIS_O is the IOB delay from IBUFDISABLE to O output.
• In I/O banks, the internal DCI t ermination turn-o ff time is always faster than TOUTBUF_DELAY_TE_PAD when the DCITERMDISABLE pin is used. Table 25: IOB 3-state Output Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 TOUTBUF_DELAY_TE_PAD T input to pad high-impedance for the I/O banks 5.330 5.330 5.341 5.330 ns TINBUF_DELAY_IBUFDIS_O IBUF turn-on time from IBUFDISABLE to O output for the I/O banks 0.873 0.936 1.037 0.936 ns Input Delay Measurement Methodology The following table shows the test setup parameters used for measuring input delay. Table 26: Input Delay Measurement Methodology Description I/O Standard Attribute VL1, 2 VH1, 2 VMEAS 1, 4 VREF 1, 3, 5 LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 – LVCMOS, LVDCI, HSLVDCI, 1.5V LVCMOS15, LVDCI_15, HSLVDCI_15 0.1 1.4 0.75 – LVCMOS, LVDCI, HSLVDCI, 1.8V LVCMOS18, LVDCI_18, HSLVDCI_18 0.1 1.7 0.9 – HSTL (high-speed transceiver logic), class I, 1.2V HSTL_I_12 VREF – 0.25 VREF + 0.25 VREF 0.6 HSTL, class I, 1.5V HSTL_I VREF – 0.325 VREF + 0.325 VREF 0.75 HSTL, class I, 1.8V HSTL_I_18 VREF – 0.4 VREF + 0.4 VREF 0.9 HSUL (high-speed unterminated logic), 1.2V HSUL_12 VREF – 0.25 VREF + 0.25 VREF 0.6 SSTL12 (stub series terminated logic), 1.2V SSTL12 VREF – 0.25 VREF + 0.25 VREF 0.6 SSTL135, 1.35V SSTL135 VREF – 0.2875 VREF + 0.2875 VREF 0.675 SSTL15, 1.5V SSTL15 VREF – 0.325 VREF + 0.325 VREF 0.75 SSTL18, class I, 1.8V SSTL18_I VREF – 0.4 VREF + 0.4 VREF 0.9 POD10, 1.0V POD10 VREF – 0.2 VREF + 0.2 VREF 0.7 POD12, 1.2V POD12 VREF – 0.24 VREF + 0.24 VREF 0.84 Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 26 Send Feedback

Parameters VREF, RREF, CREF, and VMEAS fully describe the test c onditions for each I/O standard. The most accurate pr ediction of pr opagation delay in any given application can be obtained through IBIS simulation, using this method: 1. Simulate the output driver of choice into the generalized test setup using values from Table 27. 2. Record the time to VMEAS. 3. Simulate the output driver of choice into the actual PCB trace and load using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS. 5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual pr opagation delay of the PCB trace. Table 27: Output Delay Measurement Methodology Description I/O Standard Attribute RREF (Ω) CREF1 (pF) VMEAS (V) VREF (V) LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0 LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0 LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0 LVDCI, HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 50 0 VREF 0.75 LVDCI, HSLVDCI, 1.8V LVDCI_15, HSLVDCI_18 50 0 VREF 0.9 HSTL (high-speed transceiver logic), class I, 1.2V HSTL_I_12 50 0 VREF 0.6 HSTL, class I, 1.5V HSTL_I 50 0 VREF 0.75 HSTL, class I, 1.8V HSTL_I_18 50 0 VREF 0.9 HSUL (high-speed unterminated logic), 1.2V HSUL_12 50 0 VREF 0.6 SSTL12 (stub series terminated logic), 1.2V SSTL12 50 0 VREF 0.6 SSTL135, 1.35V SSTL135 50 0 VREF 0.675 SSTL15, 1.5V SSTL15 50 0 VREF 0.75 SSTL18, class I, 1.8V SSTL18_I 50 0 VREF 0.9 POD10, 1.0V POD10 50 0 VREF 1.0 POD12, 1.2V POD12 50 0 VREF 1.2 DIFF_HSTL, class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6 DIFF_HSTL, class I, 1.5V DIFF_HSTL_I 50 0 VREF 0.75 DIFF_HSTL, class I, 1.8V DIFF_HSTL_I_18 50 0 VREF 0.9 DIFF_HSUL, 1.2V DIFF_HSUL_12 50 0 VREF 0.6 DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 VREF 0.6 DIFF_SSTL135, 1.35V DIFF_SSTL135 50 0 VREF 0.675 DIFF_SSTL15, 1.5V DIFF_SSTL15 50 0 VREF 0.75 DIFF_SSTL18, 1.8V DIFF_SSTL18_I 50 0 VREF 0.9 DIFF_POD10, 1.0V DIFF_POD10 50 0 VREF 1.0 DIFF_POD12, 1.2V DIFF_POD12 50 0 VREF 1.2 LVDS (low-voltage differential signaling), 1.8V LVDS 100 0 02 0 SUB_LVDS, 1.8V SUB_LVDS 100 0 02 0 MIPI D-PHY (high speed) 1.2V MIPI_DPHY_DCI_HS 100 0 02 0 Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 28 Send Feedback

Table 27: Output Delay Measurement Methodology (cont'd) Description I/O Standard Attribute RREF (Ω) CREF1 (pF) VMEAS (V) VREF (V) MIPI D-PHY (low power) 1.2V MIPI_DPHY_DCI_LP 1M 0 0.6 0 Notes: 1. C REF is the capacitance of the probe, nominally 0 pF. 2. The value given is the differential output voltage. Block RAM and FIFO Switching Characteristics Table 28: Block RAM and FIFO Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 Maximum Frequency FMAX_WF_NC Block RAM (WRITE_FIRST and NO_CHANGE modes) 825 737 645 585 MHz FMAX_RF Block RAM (READ_FIRST mode) 718 637 575 510 MHz FMAX_FIFO FIFO in all modes without ECC 825 737 645 585 MHz FMAX_ECC Block RAM and FIFO in ECC configuration without PIPELINE 718 637 575 510 MHz Block RAM and FIFO in ECC configuration with PIPELINE and Block RAM in WRITE_FIRST or NO_CHANGE mode 825 737 645 585 MHz TPW1 Minimum pulse width 495 542 543 577 ps Block RAM and FIFO Clock-to-Out Delays TRCKO_DO Clock CLK to DOUT output (without output register) 0.91 1.02 1.11 1.46 ns, Max TRCKO_DO_REG Clock CLK to DOUT output (with output register) 0.27 0.29 0.30 0.42 ns, Max Notes: 1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies. UltraRAM Switching Characteristics The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Virtex UltraScale+ FPGAs that include this memory. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 29 Send Feedback

Table 29: UltraRAM Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 Maximum Frequency FMAX UltraRAM maximum frequency with OREG_B = True 650 600 575 500 MHz FMAX_ECC_NOPIPELINE UltraRAM maximum frequency with OREG_B = False and EN_ECC_RD_B = True 435 400 386 312 MHz FMAX_NOPIPELINE UltraRAM maximum frequency with OREG_B = False and EN_ECC_RD_B = False 528 500 478 404 MHz TPW1 Minimum pulse width 650 700 730 800 ps TRSTPW Asynchronous reset minimum pulse width. One cycle required 1 clock cycle Notes: 1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies. Input/Output Delay Switching Characteristics Table 30: Input/Output Delay Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FREFCLK Reference clock frequency for IDELAYCTRL (component mode) 300 to 800 MHz Reference clock frequency when using BITSLICE_CONTROL with REFCLK (in native mode (for RX_BITSLICE only)) 300 to 800 MHz Reference clock frequency for BITSLICE_CONTROL with PLL_CLK (in native mode)1 300 to 2666.67 300 to 2666.67 300 to 2400 300 to 2400 MHz TMINPER_CLK Minimum period for IODELAY clock 3.195 3.195 3.195 3.195 ns TMINPER_RST Minimum reset pulse width 52.00 ns TIDELAY_RESOLUTION/ TODELAY_RESOLUTION IDELAY/ODELAY chain resolution 2.1 to 12 ps Notes: 1. PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY_MODE = VCO_HALF, the minimum frequency is PLL_FVCOMIN/2. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 30 Send Feedback

DSP48 Slice Switching Characteristics Table 31: DSP48 Slice Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V1 -3 -2 -1 -2 Maximum Frequency FMAX With all registers used 891 775 645 644 MHz FMAX_PATDET With pattern detector 794 687 571 562 MHz FMAX_MULT_NOMREG Two register multiply without MREG 635 544 456 440 MHz FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect 577 492 410 395 MHz FMAX_PREADD_NOADREG Without ADREG 655 565 468 453 MHz FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG) 483 410 338 323 MHz FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect 448 379 314 299 MHz Notes: 1. For devices operating at the lower power V CCINT = 0.72V voltages, DSP cascades that cross the clock region center might operate below the specified FMAX. Clock Buffers and Networks Table 32: Clock Buffers Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 Global Clock Switching Characteristics (Including BUFGCTRL) FMAX Maximum frequency of a global clock tree (BUFG) 891 775 667 725 MHz Global Clock Buffer with Input Divide Capability (BUFGCE_DIV) FMAX Maximum frequency of a global clock buffer with input divide capability (BUFGCE_DIV) 891 775 667 725 MHz Global Clock Buffer with Clock Enable (BUFGCE) FMAX Maximum frequency of a global clock buffer with clock enable (BUFGCE) 891 775 667 725 MHz Leaf Clock Buffer with Clock Enable (BUFCE_LEAF) FMAX Maximum frequency of a leaf clock buffer with clock enable (BUFCE_LEAF) 891 775 667 725 MHz GTY or GTM Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT) FMAX Maximum frequency of a serial transceiver clock buffer with clock enable and clock input divide capability 512 512 512 512 MHz Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 31 Send Feedback

MMCM Switching Characteristics Table 33: MMCM Specification Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 MMCM_FINMAX Maximum input clock frequency 1066 933 800 933 MHz MMCM_FINMIN Minimum input clock frequency 10 10 10 10 MHz MMCM_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max MMCM_FINDUTY Input duty cycle range: 10–49 MHz 25–75 % Input duty cycle range: 50–199 MHz 30–70 % Input duty cycle range: 200–399 MHz 35–65 % Input duty cycle range: 400–499 MHz 40–60 % Input duty cycle range: >500 MHz 45–55 % MMCM_FMIN_PSCLK Minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 MHz MMCM_FMAX_PSCLK Maximum dynamic phase shift clock frequency 550 500 450 500 MHz MMCM_FVCOMIN Minimum MMCM VCO frequency 800 800 800 800 MHz MMCM_FVCOMAX Maximum MMCM VCO frequency 1600 1600 1600 1600 MHz MMCM_FBANDWIDTH Low MMCM bandwidth at typical1 1.00 1.00 1.00 1.00 MHz High MMCM bandwidth at typical1 4.00 4.00 4.00 4.00 MHz MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs2 0.12 0.12 0.12 0.12 ns MMCM_TOUTJITTER MMCM output jitter Note 3 MMCM_TOUTDUTY MMCM output clock duty cycle precision4 0.165 0.20 0.20 0.20 ns MMCM_TLOCKMAX MMCM maximum lock time for MMCM_FPFDMIN 100 100 100 100 µs MMCM_FOUTMAX MMCM maximum output frequency 891 775 667 725 MHz MMCM_FOUTMIN MMCM minimum output frequency4, 5 6.25 6.25 6.25 6.25 MHz MMCM_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max MMCM_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 ns MMCM_FPFDMAX Maximum frequency at the phase frequency detector 550 500 450 500 MHz MMCM_FPFDMIN Minimum frequency at the phase frequency detector 10 10 10 10 MHz MMCM_TFBDELAY Maximum delay in the feedback path 5 ns Max or one clock cycle MMCM_FDPRCLK_MAX Maximum DRP clock frequency 250 250 250 250 MHz Notes: 1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any MMCM outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 32 Send Feedback

PLL Switching Characteristics Table 34: PLL Specification Symbol Description1 Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 PLL_FINMAX Maximum input clock frequency 1066 933 800 933 MHz PLL_FINMIN Minimum input clock frequency 70 70 70 70 MHz PLL_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max PLL_FINDUTY Input duty cycle range: 70–399 MHz 35–65 % Input duty cycle range: 400–499 MHz 40–60 % Input duty cycle range: >500 MHz 45–55 % PLL_FVCOMIN Minimum PLL VCO frequency 750 750 750 750 MHz PLL_FVCOMAX Maximum PLL VCO frequency 1500 1500 1500 1500 MHz PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs2 0.12 0.12 0.12 0.12 ns PLL_TOUTJITTER PLL output jitter Note 3 PLL_TOUTDUTY PLL CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B duty-cycle precision4 0.165 0.20 0.20 0.20 ns PLL_TLOCKMAX PLL maximum lock time 100 µs PLL_FOUTMAX PLL maximum output frequency at CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B 891 775 667 725 MHz PLL maximum output frequency at CLKOUTPHY 2667 2667 2400 2400 MHz PLL_FOUTMIN PLL minimum output frequency at CLKOUT0, CLKOUT0B, CLKOUT1, CLKOUT1B5 5.86 5.86 5.86 5.86 MHz PLL minimum output frequency at CLKOUTPHY 2 x VCO mode: 1500, 1 x VCO mode: 750, 0.5 x VCO mode: 375 MHz PLL_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 ns PLL_FPFDMAX Maximum frequency at the phase frequency detector 667.5 667.5 667.5 667.5 MHz PLL_FPFDMIN Minimum frequency at the phase frequency detector 70 70 70 70 MHz PLL_FBANDWIDTH PLL bandwidth at typical 14 14 14 14 MHz PLL_FDPRCLK_MAX Maximum DRP clock frequency 250 250 250 250 MHz Notes: 1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the loop filter frequencies. 2. The static offset is measured between any PLL outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 33 Send Feedback

Device Pin-to-Pin Output Parameter Guidelines The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is differ en t. Consult the Vivado Design Suite timing report for the actual pin-to-pin values. Table 35: Global Clock Input to Output Delay Without MMCM (Near Clock Region) Symbol Description1 Device Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM TICKOF Global clock input and output flip-flop without MMCM (near clock region) XCVU3P 4.41 4.77 5.09 5.48 ns XCVU5P 4.41 4.77 5.09 5.48 ns XCVU7P 4.41 4.77 5.09 5.48 ns XCVU9P 4.41 4.77 5.09 5.48 ns XCVU11P 4.22 4.59 4.90 5.27 ns XCVU13P 4.22 4.59 4.90 5.27 ns XCVU27P 4.22 4.59 4.90 5.27 ns XCVU29P 4.22 4.59 4.90 5.27 ns XCVU31P 4.22 4.59 4.90 5.27 ns XCVU33P 4.22 4.59 4.90 5.27 ns XCVU35P 4.22 4.59 4.90 5.27 ns XCVU37P 4.22 4.59 4.90 5.27 ns XQVU3P N/A 4.77 5.09 5.48 ns XQVU7P N/A 4.77 5.09 5.48 ns XQVU11P N/A 4.59 4.90 5.27 ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 34 Send Feedback

Table 36: Global Clock Input to Output Delay Without MMCM (Far Clock Region) Symbol Description1 Device Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM TICKOF_FAR Global clock input and output flip-flop without MMCM (far clock region) XCVU3P 4.90 5.33 5.69 6.24 ns XCVU5P 4.90 5.33 5.69 6.24 ns XCVU7P 4.90 5.33 5.69 6.24 ns XCVU9P 4.90 5.33 5.69 6.24 ns XCVU11P 4.40 4.79 5.11 5.54 ns XCVU13P 4.40 4.79 5.11 5.54 ns XCVU27P 4.40 4.79 5.11 5.54 ns XCVU29P 4.40 4.79 5.11 5.54 ns XCVU31P 4.40 4.79 5.11 5.54 ns XCVU33P 4.40 4.79 5.11 5.54 ns XCVU35P 4.40 4.79 5.11 5.54 ns XCVU37P 4.40 4.79 5.11 5.54 ns XQVU3P N/A 5.33 5.69 6.24 ns XQVU7P N/A 5.33 5.69 6.24 ns XQVU11P N/A 4.79 5.11 5.54 ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 35 Send Feedback

Table 37: Global Clock Input to Output Delay With MMCM Symbol Description1, 2 Device Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM TICKOFMMCMCC Global clock input and output flip-flop with MMCM XCVU3P 1.51 1.80 1.94 1.80 ns XCVU5P 1.51 1.80 1.94 1.80 ns XCVU7P 1.51 1.80 1.94 1.80 ns XCVU9P 1.51 1.80 1.94 1.80 ns XCVU11P 1.29 1.56 1.68 1.56 ns XCVU13P 1.29 1.56 1.68 1.56 ns XCVU27P 1.29 1.56 1.68 1.56 ns XCVU29P 1.29 1.56 1.68 1.56 ns XCVU31P 1.29 1.56 1.68 1.56 ns XCVU33P 1.29 1.56 1.68 1.56 ns XCVU35P 1.29 1.56 1.68 1.56 ns XCVU37P 1.29 1.56 1.68 1.56 ns XQVU3P N/A 1.80 1.94 1.80 ns XQVU7P N/A 1.80 1.94 1.80 ns XQVU11P N/A 1.56 1.68 1.56 ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. 2. MMCM output jitter is already included in the timing calculation. Table 38: Source Synchronous Output Characteristics (Component Mode) Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 TOUTPUT_LOGIC_DELAY_VARIATION 1 80 ps Notes: 1. Delay mismatch across a transmit bus when using component mode output logic (ODDRE1, OSERDESE3) within a bank. Device Pin-to-Pin Input Parameter Guidelines The pin-to-pin numbers in the following table are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is differ en t. Consult the Vivado Design Suite timing report for the actual pin-to-pin values. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 36 Send Feedback

Table 39: Global Clock Input Setup and Hold With MMCM Symbol Description Device Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.1, 2, 3 TPSMMCMCC_VU3P Global clock input and input flip-flop (or latch) with MMCM Setup XCVU3P 1.86 1.86 1.99 1.86 ns TPHMMCMCC_VU3P Hold –0.13 –0.13 –0.13 –0.17 ns TPSMMCMCC_VU5P Setup XCVU5P 1.86 1.86 1.99 1.86 ns TPHMMCMCC_VU5P Hold –0.13 –0.13 –0.13 –0.17 ns TPSMMCMCC_VU7P Setup XCVU7P 1.86 1.86 1.99 1.86 ns TPHMMCMCC_VU7P Hold –0.13 –0.13 –0.13 –0.17 ns TPSMMCMCC_VU9P Setup XCVU9P 1.86 1.86 1.99 1.86 ns TPHMMCMCC_VU9P Hold –0.13 –0.13 –0.13 –0.17 ns TPSMMCMCC_VU11P Setup XCVU11P 1.91 1.92 2.05 1.92 ns TPHMMCMCC_VU11P Hold –0.13 –0.13 –0.13 –0.18 ns TPSMMCMCC_VU13P Setup XCVU13P 1.91 1.92 2.05 1.92 ns TPHMMCMCC_VU13P Hold –0.13 –0.13 –0.13 –0.18 ns TPSMMCMCC_VU31P Setup XCVU31P 1.91 1.92 2.05 1.92 ns TPHMMCMCC_VU31P Hold –0.13 –0.13 –0.13 –0.18 ns TPSMMCMCC_VU33P Setup XCVU33P 1.91 1.92 2.05 1.92 ns TPHMMCMCC_VU33P Hold –0.13 –0.13 –0.13 –0.18 ns TPSMMCMCC_VU35P Setup XCVU35P 1.91 1.92 2.05 1.92 ns TPHMMCMCC_VU35P Hold –0.13 –0.13 –0.13 –0.18 ns TPSMMCMCC_VU37P Setup XCVU37P 1.91 1.92 2.05 1.92 ns TPHMMCMCC_VU37P Hold –0.13 –0.13 –0.13 –0.18 ns TPSMMCMCC_VU27P Setup XCVU27P 1.91 1.92 2.05 1.92 ns TPHMMCMCC_VU27P Hold –0.13 –0.13 –0.13 –0.18 ns TPSMMCMCC_VU29P Setup XCVU29P 1.91 1.92 2.05 1.92 ns TPHMMCMCC_VU29P Hold –0.13 –0.13 –0.13 –0.18 ns Notes: 1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage. 2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 37 Send Feedback

Table 40: Sampling Window Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 TSAMP_BUFG1 510 610 610 610 ps TSAMP_NATIVE_DPA2 100 100 125 125 ps TSAMP_NATIVE_BISC3 60 60 85 85 ps Notes: 1. This parameter indicates the total sampling error of the Virtex UltraScale+ FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew. 2. This parameter is the receive sampling error for RX_BITSLICE when using dynamic phase alignment. 3. This parameter is the receive sampling error for RX_BITSLICE when using built-in self-calibration (BISC). Table 41: Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode) Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 TINPUT_LOGIC_UNCERTAINTY1 40 ps TCAL_ERROR2 24 ps Notes: 1. Input_logic_uncertainty accounts for the setup/hold and any pattern dependent jitter for the input logic (input register, IDDRE1, or ISERDESE3). 2. Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin to ensure optimal performance. Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for clock tr ansmitter and receiver data-valid windows. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 38 Send Feedback

Table 42: Package Skew Symbol Description Device Package Value Units XCVU5P FLVA2104 175 ps FLVB2104 225 ps FLVC2104 216 ps XCVU7P FLVA2104 175 ps FLVB2104 225 ps FLVC2104 216 ps XCVU9P FLGA2104 217 ps FLGB2104 275 ps FLGC2104 299 ps FSGD2104 229 ps FLGA2577 149 ps XCVU11P FLGF1924 180 ps FLGB2104 216 ps FLGC2104 175 ps FSGD2104 224 ps FLGA2577 154 ps XCVU13P FHGA2104 215 ps FHGB2104 259 ps FHGC2104 182 ps FIGD2104 198 ps FLGA2577 140 ps XCVU27P FIGD2104 198 ps FSGA2577 139 ps XCVU29P FIGD2104 198 ps FSGA2577 139 ps XCVU31P FSVH1924 165 ps XCVU33P FSVH2104 194 ps XCVU35P FSVH2104 200 ps FSVH2892 241 ps XCVU37P FSVH2892 278 ps XQVU3P FFRC1517 176 ps XQVU7P FLRA2104 175 ps FLRA2104 224 ps XQVU11P FLRC2104 174 ps Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. 2. Package delay information is available for these device/package combinations. This information can be used to deskew the package. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 39 Send Feedback

GTY Transceiver Specifications The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Virtex UltraScale+ FPGAs that include the GTY transceivers. GTY Transceiver DC Input and Output Levels Table 43 summarizes the DC specifications of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further details. Table 43: GTY Transceiver DC Specifications Symbol DC Parameter Conditions Min Typ Max Units DVPPIN Differential peak-to-peak input voltage (external AC coupled) >10.3125 Gb/s 150 – 1250 mV 6.6 Gb/s to 10.3125 Gb/s 150 – 1250 mV ≤ 6.6 Gb/s 150 – 2000 mV VIN Single-ended input voltage. Voltage measured at the pin referenced to GND. DC coupled VMGTAVTT = 1.2V –400 – VMGTAVTT mV VCMIN Common mode input voltage DC coupled VMGTAVTT = 1.2V – 2/3 VMGTAVTT – mV DVPPOUT Differential peak-to-peak output voltage1 Transmitter output swing is set to 11111 800 – – mV VCMOUTDC Common mode output voltage: DC coupled (equation based) When remote RX is terminated to GND VMGTAVTT/2 – DVPPOUT/4 mV When remote RX termination is floating VMGTAVTT – DVPPOUT/2 mV When remote RX is terminated to VRX_TERM2 mV VCMOUTAC Common mode output voltage: AC coupled Equation based VMGTAVTT – DVPPOUT/2 mV RIN Differential input resistance – 100 – Ω ROUT Differential output resistance – 100 – Ω TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew – – 10 ps CEXT Recommended external AC coupling capacitor3 – 100 – nF Notes: 1. The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes discussed in the UltraScale Architecture GTY Transceivers User Guide (UG578) and can result in values lower than reported in this table. 2. V RX_TERM is the remote RX termination voltage. 3. Other values can be used as appropriate to conform to specific protocols and standards. Figure 3: Single-Ended Peak-to-Peak Voltage +V P N Single-Ended Peak-to-Peak Voltage X16653-072117 Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 40 Send Feedback

Figure 4: Differential Peak-to-Peak Voltage –V P–N Differential Peak-to-Peak Voltage Differential peak-to-peak voltage = (Single-ended peak-to-peak voltage) x 2 X16639-072117 The following tables summarize the DC specifications of the clock input/output levels of the GTY transceivers in Virtex UltraScale+ FPGAs. Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further details. Table 44: GTY Transceiver Clock DC Input Level Specification Symbol DC Parameter Min Typ Max Units VIDIFF Differential peak-to-peak input voltage 250 – 2000 mV RIN Differential input resistance – 100 – Ω CEXT Required external AC coupling capacitor – 10 – nF Table 45: GTY Transceiver Clock Output Level Specification Symbol Description Conditions Min Typ Max Units VOL Output Low voltage for P and N RT = 100Ω across P and N signals 100 – 330 mV VOH Output High voltage for P and N RT = 100Ω across P and N signals 500 – 700 mV VDDOUT Differential output voltage (P–N), P = High (N–P), N = High RT = 100Ω across P and N signals 300 – 430 mV VCMOUT Common mode voltage RT = 100Ω across P and N signals 300 – 500 mV GTY Transceiver Switching Characteristics Consult the UltraScale Architecture GTY Transceivers User Guide (UG578) for further in f ormation. Table 46: GTY Transceiver Performance Symbol Description Output Divider Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FGTYMAX GTY maximum line rate 32.751 28.211 25.7851 28.211 Gb/s FGTYMIN GTY minimum line rate 0.5 0.5 0.5 0.5 Gb/s Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 41 Send Feedback

Table 46: GTY Transceiver Performance (cont'd) Symbol Description Output Divider Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 Min Max Min Max Min Max Min Max FGTYCRANGE CPLL line rate range2

16 N/A Gb/s

32 N/A Gb/s

Min Max Min Max Min Max Min Max FGTYQRANGE1 QPLL0 line rate range3 Min Max Min Max Min Max Min Max FGTYQRANGE2 QPLL1 line rate range4 Min Max Min Max Min Max Min Max Notes: 1. XCVU11P devices in the FLGF1924 package have a maximum GTY transceiver line rate of 16.3 Gb/s. 2. The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider. 3. The values listed are the rounded results of the calculated equation (2 × QPLL0_Frequency)/Output_Divider. 4. The values listed are the rounded results of the calculated equation (2 × QPLL1_Frequency)/Output_Divider. Table 47: GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Symbol Description All Speed Grades Units FGTYDRPCLK GTYDRPCLK maximum frequency 250 MHz Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 42 Send Feedback

Table 48: GTY Transceiver Reference Clock Switching Characteristics Symbol Description Conditions All Speed Grades Units Min Typ Max FGCLK Reference clock frequency range 60 – 820 MHz TRCLK Reference clock rise time 20% – 80% – 200 – ps TFCLK Reference clock fall time 80% – 20% – 200 – ps TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 % Table 49: GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask Symbol Description1, 2 Offset Frequency Min Typ Max Units QPLLREFCLKMASK QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 156.25 MHz 10 kHz – – –112 dBc/Hz 100 kHz – – –128

1 MHz – – –145

QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz 10 kHz – – –103 dBc/Hz 100 kHz – – –123

1 MHz – – –143

QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 625 MHz 10 kHz – – –98 dBc/Hz 100 kHz – – –117

1 MHz – – –140

CPLLREFCLKMASK CPLL reference clock select phase noise mask at REFCLK frequency = 156.25 MHz 10 kHz – – –112 dBc/Hz 100 kHz – – –128

50 MHz – – –145

CPLL reference clock select phase noise mask at REFCLK frequency = 312.5 MHz 10 kHz – – –103 dBc/Hz 100 kHz – – –123 CPLL reference clock select phase noise mask at REFCLK frequency = 625 MHz 10 kHz – – –98 dBc/Hz 100 kHz – – –117

50 MHz – – –144

Notes: 1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency. 2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol, e.g., PCIe. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 43 Send Feedback

Table 50: GTY Transceiver PLL/Lock Time Adaptation Symbol Description Conditions All Speed Grades Units Min Typ Max TLOCK Initial PLL lock. – – 1 ms TDLOCK Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE) After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. – 50,000 37 x 106 UI Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled – 50,000 2.3 x 106 UI Table 51: GTY Transceiver User Clock Switching Characteristics Symbol Description1 Data Width Conditions (Bit) Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V Internal Logic Interconnect Logic -3 -2 -12 -2 FTXOUTPMA TXOUTCLK maximum frequency sourced from OUTCLKPMA 511.719 511.719 402.891 402.832 MHz FRXOUTPMA RXOUTCLK maximum frequency sourced from OUTCLKPMA 511.719 511.719 402.891 402.832 MHz FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from TXPROGDIVCLK 511.719 511.719 511.719 511.719 MHz FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from RXPROGDIVCLK 511.719 511.719 511.719 511.719 MHz FTXIN TXUSRCLK3 maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 MHz 32 32, 64 511.719 511.719 390.625 390.625 MHz 64 64, 128 511.719 440.781 402.891 402.832 MHz 20 20, 40 409.375 409.375 312.500 312.500 MHz 40 40, 80 409.375 409.375 312.500 350.000 MHz 80 80, 160 409.375 352.625 322.313 352.625 MHz FRXIN RXUSRCLK3 maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 MHz 32 32, 64 511.719 511.719 390.625 390.625 MHz 64 64, 128 511.719 440.781 402.891 402.832 MHz 20 20, 40 409.375 409.375 312.500 312.500 MHz 40 40, 80 409.375 409.375 312.500 350.000 MHz 80 80, 160 409.375 352.625 322.313 352.625 MHz Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 44 Send Feedback

Table 51: GTY Transceiver User Clock Switching Characteristics (cont'd) Symbol Description1 Data Width Conditions (Bit) Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V Internal Logic Interconnect Logic -3 -2 -12 -2 FTXIN2 TXUSRCLK23 maximum frequency 16 16 511.719 511.719 390.625 390.625 MHz 16 32 255.859 255.859 195.313 195.313 MHz 32 32 511.719 511.719 390.625 390.625 MHz 32 64 255.859 255.859 195.313 195.313 MHz 64 64 511.719 440.781 402.891 402.832 MHz 64 128 255.859 220.391 201.445 201.416 MHz 20 20 409.375 409.375 312.500 312.500 MHz 20 40 204.688 204.688 156.250 156.250 MHz 40 40 409.375 409.375 312.500 350.000 MHz 40 80 204.688 204.688 156.250 175.000 MHz 80 80 409.375 352.625 322.313 352.625 MHz 80 160 204.688 176.313 161.156 176.313 MHz FRXIN2 RXUSRCLK23 maximum frequency 16 16 511.719 511.719 390.625 390.625 MHz 16 32 255.859 255.859 195.313 195.313 MHz 32 32 511.719 511.719 390.625 390.625 MHz 32 64 255.859 255.859 195.313 195.313 MHz 64 64 511.719 440.781 402.891 402.832 MHz 64 128 255.859 220.391 201.445 201.416 MHz 20 20 409.375 409.375 312.500 312.500 MHz 20 40 204.688 204.688 156.250 156.250 MHz 40 40 409.375 409.375 312.500 350.000 MHz 40 80 204.688 204.688 156.250 175.000 MHz 80 80 409.375 352.625 322.313 352.625 MHz 80 160 204.688 176.313 161.156 176.313 MHz Notes: 1. Clocking must be implemented as described in the UltraScale Architecture GTY Transceivers User Guide (UG578). 2. For the speed grades -1E, -1I, and -1M, only a 64- or 80-bit internal data path can be used for line rates above 12.5 Gb/s. 3. When the gearbox is used, these maximums refer to the XCLK. For more information, see the Valid Data Width Combinations for TX Asynchronous Gearbox table in the UltraScale Architecture GTY Transceivers User Guide (UG578). Table 52: GTY Transceiver Transmitter Switching Characteristics Symbol Description Condition Min Typ Max Units FGTYTX Serial data rate range 0.500 – FGTYMAX Gb/s TRTX TX rise time 20%–80% – 21 – ps TFTX TX fall time 80%–20% – 21 – ps TLLSKEW TX lane-to-lane skew1 – – 500.00 ps TJ32.75 Total jitter2, 4 32.75 Gb/s – – 0.35 UI DJ32.75 Deterministic jitter2, 4 – – 0.19 UI Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 45 Send Feedback

Table 52: GTY Transceiver Transmitter Switching Characteristics (cont'd) Symbol Description Condition Min Typ Max Units TJ28.21 Total jitter2, 4 28.21 Gb/s – – 0.28 UI DJ28.21 Deterministic jitter2, 4 – – 0.17 UI TJ16.375 Total jitter2, 4 16.375 Gb/s – – 0.28 UI DJ16.375 Deterministic jitter2, 4 – – 0.17 UI TJ15.0 Total jitter2, 4 15.0 Gb/s – – 0.28 UI DJ15.0 Deterministic jitter2, 4 – – 0.17 UI TJ14.1 Total jitter2, 4 14.1 Gb/s – – 0.28 UI DJ14.1 Deterministic jitter2, 4 – – 0.17 UI TJ14.1 Total jitter2, 4 14.025 Gb/s – – 0.28 UI DJ14.1 Deterministic jitter2, 4 – – 0.17 UI TJ13.1 Total jitter2, 4 13.1 Gb/s – – 0.28 UI DJ13.1 Deterministic jitter2, 4 – – 0.17 UI TJ12.5_QPLL Total jitter2, 4 12.5 Gb/s – – 0.28 UI DJ12.5_QPLL Deterministic jitter2, 4 – – 0.17 UI TJ12.5_CPLL Total jitter3, 4 12.5 Gb/s – – 0.33 UI DJ12.5_CPLL Deterministic jitter3, 4 – – 0.17 UI TJ11.3_QPLL Total jitter2, 4 11.3 Gb/s – – 0.28 UI DJ11.3_QPLL Deterministic jitter2, 4 – – 0.17 UI TJ10.3125_QPLL Total jitter2, 4 10.3125 Gb/s – – 0.28 UI DJ10.3125_QPLL Deterministic jitter2, 4 – – 0.17 UI TJ10.3125_CPLL Total jitter3, 4 10.3125 Gb/s – – 0.33 UI DJ10.3125_CPLL Deterministic jitter3, 4 – – 0.17 UI TJ9.953_QPLL Total jitter2, 4 9.953 Gb/s – – 0.28 UI DJ9.953_QPLL Deterministic jitter2, 4 – – 0.17 UI TJ9.953_CPLL Total jitter3, 4 9.953 Gb/s – – 0.33 UI DJ9.953_CPLL Deterministic jitter3, 4 – – 0.17 UI TJ8.0 Total jitter3, 4 8.0 Gb/s – – 0.32 UI DJ8.0 Deterministic jitter3, 4 – – 0.17 UI TJ6.6 Total jitter3, 4 6.6 Gb/s – – 0.30 UI DJ6.6 Deterministic jitter3, 4 – – 0.15 UI TJ5.0 Total jitter3, 4 5.0 Gb/s – – 0.30 UI DJ5.0 Deterministic jitter3, 4 – – 0.15 UI TJ4.25 Total jitter3, 4 4.25 Gb/s – – 0.30 UI DJ4.25 Deterministic jitter3, 4 – – 0.15 UI TJ3.20 Total jitter3, 4 3.20 Gb/s5 – – 0.20 UI DJ3.20 Deterministic jitter3, 4 – – 0.10 UI TJ2.5 Total jitter3, 4 2.5 Gb/s6 – – 0.20 UI DJ2.5 Deterministic jitter3, 4 – – 0.10 UI TJ1.25 Total jitter3, 4 1.25 Gb/s7 – – 0.15 UI DJ1.25 Deterministic jitter3, 4 – – 0.06 UI Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 46 Send Feedback

Table 52: GTY Transceiver Transmitter Switching Characteristics (cont'd) Symbol Description Condition Min Typ Max Units TJ500 Total jitter3, 4 500 Mb/s8 – – 0.10 UI DJ500 Deterministic jitter3, 4 – – 0.03 UI Notes: 1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTY Quad) at maximum line rate. 2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 4. All jitter values are based on a bit-error ratio of 10 –12. 5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. 6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. 7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4. 8. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8. Table 53: GTY Transceiver Receiver Switching Characteristics Symbol Description Condition Min Typ Max Units FGTYRX Serial data rate 0.500 – FGTYMAX Gb/s RXSST Receiver spread-spectrum tracking1 Modulated at 33 kHz –5000 – 0 ppm RXRL Run length (CID) – – 256 UI RXPPMTOL Data/REFCLK PPM offset tolerance Bit rates ≤ 6.6 Gb/s –1250 – 1250 ppm Bit rates > 6.6 Gb/s and ≤ 8.0 Gb/s –700 – 700 ppm Bit rates > 8.0 Gb/s –200 – 200 ppm SJ Jitter Tolerance2 JT_SJ32.75 Sinusoidal jitter (QPLL)3 32.75 Gb/s 0.25 – – UI JT_SJ28.21 Sinusoidal jitter (QPLL)3 28.21 Gb/s 0.30 – – UI JT_SJ16.375 Sinusoidal jitter (QPLL)3 16.375 Gb/s 0.30 – – UI JT_SJ15.0 Sinusoidal jitter (QPLL)3 15.0 Gb/s 0.30 – – UI JT_SJ14.1 Sinusoidal jitter (QPLL)3 14.1 Gb/s 0.30 – – UI JT_SJ13.1 Sinusoidal jitter (QPLL)3 13.1 Gb/s 0.30 – – UI JT_SJ12.5 Sinusoidal jitter (QPLL)3 12.5 Gb/s 0.30 – – UI JT_SJ11.3 Sinusoidal jitter (QPLL)3 11.3 Gb/s 0.30 – – UI JT_SJ10.32_QPLL Sinusoidal jitter (QPLL)3 10.32 Gb/s 0.30 – – UI JT_SJ10.32_CPLL Sinusoidal jitter (CPLL)3 10.32 Gb/s 0.30 – – UI JT_SJ9.953_QPLL Sinusoidal jitter (QPLL)3 9.953 Gb/s 0.30 – – UI JT_SJ9.953_CPLL Sinusoidal jitter (CPLL)3 9.953 Gb/s 0.30 – – UI JT_SJ8.0 Sinusoidal jitter (CPLL)3 8.0 Gb/s 0.42 – – UI JT_SJ6.6 Sinusoidal jitter (CPLL)3 6.6 Gb/s 0.44 – – UI JT_SJ5.0 Sinusoidal jitter (CPLL)3 5.0 Gb/s 0.44 – – UI JT_SJ4.25 Sinusoidal jitter (CPLL)3 4.25 Gb/s 0.44 – – UI JT_SJ3.2 Sinusoidal jitter (CPLL)3 3.2 Gb/s4 0.45 – – UI JT_SJ2.5 Sinusoidal jitter (CPLL)3 2.5 Gb/s5 0.30 – – UI JT_SJ1.25 Sinusoidal jitter (CPLL)3 1.25 Gb/s6 0.30 – – UI JT_SJ500 Sinusoidal jitter (CPLL)3 500 Mb/s7 0.30 – – UI Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 47 Send Feedback

Table 53: GTY Transceiver Receiver Switching Characteristics (cont'd) Symbol Description Condition Min Typ Max Units SJ Jitter Tolerance with Stressed Eye2 JT_TJSE3.2 Total jitter with stressed eye8 3.2 Gb/s 0.70 – – UI JT_TJSE6.6 6.6 Gb/s 0.70 – – UI JT_SJSE3.2 Sinusoidal jitter with stressed eye8 3.2 Gb/s 0.10 – – UI JT_SJSE6.6 6.6 Gb/s 0.10 – – UI Notes: 1. Using RXOUT_DIV = 1, 2, and 4. 2. All jitter values are based on a bit error ratio of 10 –12. 3. The frequency of the injected sinusoidal jitter is 80 MHz. 4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. 5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. 6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. 7. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8. 8. Composite jitter with RX equalizer enabled. DFE disabled. GTY Transceiver Electrical Compliance The UltraScale Architecture GTY Transceivers User Guide (UG578) contains recommended use modes that ensure compliance for the protocols listed in the following table. The transceiver wizard provides the recommended se ttings for those use cases and for protocol specific char act eristics. Table 54: GTY Transceiver Protocol List Protocol Specification Serial Rate (Gb/s) Electrical Compliance CAUI-4 IEEE 802.3-2012 25.78125 Compliant 28 Gb/s backplane CEI-25G-LR 25–28.05 Compliant Interlaken OIF-CEI-6G, OIF-CEI-11GSR, OIF-CEI-28G-MR 4.25–25.78125 Compliant 100GBASE-KR4 IEEE 802.3bj-2014, CEI-25G-LR 25.78125 Compliant1 100GBASE-CR4 IEEE 802.3bj-2014, CEI-25G-LR 25.78125 Compliant1 50GBASE-KR4 IEEE 802.3by-2014, CEI-25G-LR 25.78125 Compliant1 50GBASE-CR4 IEEE 802.3by-2014, CEI-25G-LR 25.78125 Compliant1 25GBASE-KR4 IEEE 802.3by-2014, CEI-25G-LR 25.78125 Compliant1 25GBASE-CR4 IEEE 802.3by-2014, CEI-25G-LR 25.78125 Compliant1 OTU4 (OTL4.4) CFP2 OIF-CEI-28G-VSR 27.952493–32.75 Compliant OTU4 (OTL4.4) CFP OIF-CEI-11G-MR 11.18–13.1 Compliant CAUI-10 IEEE 802.3-2012 10.3125 Compliant nPPI IEEE 802.3-2012 10.3125 Compliant 10GBASE-KR2 IEEE 802.3-2012 10.3125 Compliant SFP+ SFF-8431 (SR and LR) 9.95328–11.10 Compliant XFP INF-8077i, revision 4.5 10.3125 Compliant RXAUI CEI-6G-SR 6.25 Compliant XAUI IEEE 802.3-2012 3.125 Compliant 1000BASE-X IEEE 802.3-2012 1.25 Compliant Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 48 Send Feedback

Table 54: GTY Transceiver Protocol List (cont'd) Protocol Specification Serial Rate (Gb/s) Electrical Compliance 5.0G Ethernet IEEE 802.3bx (PAR) 5 Compliant 2.5G Ethernet IEEE 802.3bx (PAR) 2.5 Compliant HiGig, HiGig+, HiGig2 IEEE 802.3-2012 3.74, 6.6 Compliant QSGMII QSGMII v1.2 (Cisco System, ENG-46158) 5 Compliant OTU2 ITU G.8251 10.709225 Compliant OTU4 (OTL4.10) OIF-CEI-11G-SR 11.180997 Compliant OC-3/12/48/192 GR-253-CORE 0.1555–9.956 Compliant PCIe Gen1, 2, 3 PCI Express base 3.0 2.5, 5.0, and 8.0 Compliant SDI3 SMPTE 424M-2006 0.27–2.97 Compliant UHD-SDI3 SMPTE ST-2081 6G, SMPTE ST-2082 12G 6 and 12 Compliant Hybrid memory cube (HMC) HMC-15G-SR 10, 12.5, and 15.0 Compliant MoSys bandwidth engine CEI-11-SR and CEI-11-SR (overclocked) 10.3125, 15.5 Compliant CPRI CPRI_v_6_1_2014-07-01 0.6144–12.165 Compliant Passive optical network (PON) 10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G-PON 0.155–10.3125 Compliant JESD204a/b OIF-CEI-6G, OIF-CEI-11G 3.125–12.5 Compliant Serial RapidIO RapidIO specification 3.1 1.25–10.3125 Compliant DisplayPort DP 1.2B CTS 1.62–5.4 Compliant3 Fibre channel FC-PI-4 1.0625–14.025 Compliant SATA Gen1, 2, 3 Serial ATA revision 3.0 specification 1.5, 3.0, and 6.0 Compliant SAS Gen1, 2, 3 T10/BSR INCITS 519 3.0, 6.0, and 12.0 Compliant SFI-5 OIF-SFI5-01.0 0.625 - 12.5 Compliant Aurora CEI-6G, CEI-11G-LR All rates Compliant Notes: 1. 25 dB loss at Nyquist without FEC. 2. The transition time of the transmitter is faster than the IEEE Std 802.3-2012 specification. 3. This protocol requires external circuitry to achieve compliance. GTM Transceiver Specifications The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Virtex UltraScale+ FPGAs that include the GTM transceivers. GTM Transceiver DC Input and Output Levels Table 55 summarizes the DC specifications of the GTM transceivers in Virtex UltraScale+ FPGAs. Consult the Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581) for further details. Table 55: GTM Transceiver DC Specifications Symbol DC Parameter Conditions Min Typ Max Units DVPPIN Differential peak-to-peak input voltage (external AC coupled) 150 – 1250 mV Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 49 Send Feedback

Table 56: GTM Transceiver Clock DC Input Level Specification Symbol DC Parameter Min Typ Max Units VIDIFF Differential peak-to-peak input voltage 250 – 2000 mV RIN Differential input resistance – 100 – Ω CEXT Required external AC coupling capacitor – 10 – nF Table 57: GTM Transceiver Clock Output Level Specification Symbol Description Conditions Min Typ Max Units VOL Output Low voltage for P and N RT = 100Ω across P and N signals 100 – 330 mV VOH Output High voltage for P and N RT = 100Ω across P and N signals 500 – 700 mV VDDOUT Differential output voltage (P–N), P = High (N–P), N = High RT = 100Ω across P and N signals 300 – 430 mV VCMOUT Common mode voltage RT = 100Ω across P and N signals 300 – 500 mV GTM Transceiver Switching Characteristics Consult the Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581) for further in f ormation. Table 58: GTM Transceiver Performance Symbol Description Modulation Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FGTMMAX GTM maximum line rate PAM41 58.00 56.42 53.20 56.42 Gb/s NRZ2 29.00 28.21 26.60 28.21 Gb/s FGTMMIN GTM minimum line rate PAM41 19.6 19.6 19.6 19.6 Gb/s NRZ2 9.8 9.8 9.8 9.8 Gb/s Notes: 1. For PAM4, data rates from 29 Gb/s to 39.2 Gb/s are not available. 2. For NRZ, data rates from 14.5 Gb/s to 19.6 Gb/s are not available. Table 59: GTM Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Symbol Description All Speed Grades Units FGTMDRPCLK GTMDRPCLK maximum frequency 250 MHz Table 60: GTM Transceiver Reference Clock Switching Characteristics Symbol Description Conditions All Speed Grades Units Min Typ Max FGCLK Reference clock frequency range 60 – 820 MHz TRCLK Reference clock rise time 20% – 80% – 200 – ps TFCLK Reference clock fall time 80% – 20% – 200 – ps TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 % Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 51 Send Feedback

Table 61: GTM Transceiver Reference Clock Oscillator Selection Phase Noise Mask Symbol Description1, 2 Offset Frequency Min Typ Max Units LCPLLREFCLKMASK LCPLL reference clock select phase noise mask at REFCLK frequency = 156.25 MHz 10 kHz – – –112 dBc/Hz 100 kHz – – –128 LCPLL0 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz 10 kHz – – –103 dBc/Hz 100 kHz – – –123 LCPLL0 reference clock select phase noise mask at REFCLK frequency = 625 MHz 10 kHz – – –98 dBc/Hz 100 kHz – – –117 Notes: 1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency. 2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol. Table 62: GTM Transceiver PLL/Lock Time Adaptation Symbol Description Conditions All Speed Grades Units Min Typ Max TLOCK Initial PLL lock. – – 1 ms TDLOCK Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE) After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. – UI Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled – UI Table 63: GTM Transceiver User Clock Switching Characteristics Symbol Description1 Data Width Conditions (Bit) Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V Internal Logic Interconnect Logic -3 -2 -1 -2 FTXOUTPMA TXOUTCLK maximum frequency sourced from OUTCLKPMA 453.13 440.78 415.63 440.78 MHz FRXOUTPMA RXOUTCLK maximum frequency sourced from OUTCLKPMA 453.13 440.78 415.63 440.78 MHz FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from TXPROGDIVCLK 725.00 705.25 665.00 705.25 MHz FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from RXPROGDIVCLK 725.00 705.25 665.00 705.25 MHz FTXIN TXUSRCLK maximum frequency PAM4 80 80 725.00 705.25 665.00 705.25 MHz 128 128 453.13 440.78 415.63 440.78 MHz 80 160 725.00 705.25 665.00 705.25 MHz 128 256 453.13 440.78 415.63 440.78 MHz NRZ 64 64 453.13 440.78 415.63 440.78 MHz 64 128 453.13 440.78 415.63 440.78 MHz Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 52 Send Feedback

Table 63: GTM Transceiver User Clock Switching Characteristics (cont'd) Symbol Description1 Data Width Conditions (Bit) Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V Internal Logic Interconnect Logic -3 -2 -1 -2 FRXIN RXUSRCLK maximum frequency PAM4 80 80 725.00 705.25 665.00 705.25 MHz 128 128 453.13 440.78 415.63 440.78 MHz 80 160 725.00 705.25 665.00 705.25 MHz 128 256 453.13 440.78 415.63 440.78 MHz NRZ 64 64 453.13 440.78 415.63 440.78 MHz 64 128 453.13 440.78 415.63 440.78 MHz FTXIN2 TXUSRCLK2 maximum frequency PAM4 80 80 725.00 705.25 665.00 705.25 MHz 128 128 453.13 440.78 415.63 440.78 MHz 80 160 362.50 352.63 332.50 352.63 MHz 128 256 226.56 220.39 207.81 220.39 MHz NRZ 64 64 453.13 440.78 415.63 440.78 MHz 64 128 226.56 220.39 207.81 220.39 MHz FRXIN2 RXUSRCLK2 maximum frequency PAM4 80 80 725.00 705.25 665.00 705.25 MHz 128 128 453.13 440.78 415.63 440.78 MHz 80 160 362.50 352.63 332.50 352.63 MHz 128 256 226.56 220.39 207.81 220.39 MHz NRZ 64 64 453.13 440.78 415.63 440.78 MHz 64 128 226.56 220.39 207.81 220.39 MHz Notes: 1. Clocking must be implemented as described in the Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581). Table 64: GTM Transceiver Transmitter Switching Characteristics Symbol Description Condition Min Typ Max Units FGTMTX Serial data rate range FGTMMIN – FGTMMAX Gb/s TRTX TX rise time 20%–80% – – ps TFTX TX fall time 80%–20% – – ps TLLSKEW TX lane-to-lane skew1 – – ps TJ58_PAM4 Total jitter2, 3 PAM4 58 Gb/s – – UI DJ58_PAM4 Deterministic jitter2, – – UI TJ56.42_PAM4 Total jitter2, PAM4 56.42 Gb/s – – UI DJ56.42_PAM4 Deterministic jitter2, – – UI TJ53.125_PAM4 Total jitter2, PAM4 53.125 Gb/s – – UI DJ53.125_PAM4 Deterministic jitter2, – – UI TJ52.125_PAM4 Total jitter2, PAM4 52.125 Gb/s – – UI DJ52.125_PAM4 Deterministic jitter2, – – UI TJ48_PAM4 Total jitter2, PAM4 48 Gb/s – – UI DJ48_PAM4 Deterministic jitter2, – – UI TJ28.21_PAM4 Total jitter2, PAM4 28.21 Gb/s – – UI DJ28.21_PAM4 Deterministic jitter2, – – UI Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 53 Send Feedback

Table 64: GTM Transceiver Transmitter Switching Characteristics (cont'd) Symbol Description Condition Min Typ Max Units TJ19.6_PAM4 Total jitter2, PAM4 19.6 Gb/s – – UI DJ19.6_PAM4 Deterministic jitter2, – – UI TJ29_NRZ Total jitter2, 3 NRZ 29 Gb/s – – UI DJ29_NRZ Deterministic jitter2, 3 – – UI TJ28.21_NRZ Total jitter2, 3 NRZ 28.21 Gb/s – – UI DJ28.21_NRZ Deterministic jitter2, 3 – – UI TJ26.5625_NRZ Total jitter2, 3 NRZ 26.5625 Gb/s – – UI DJ26.5625_NRZ Deterministic jitter2, 3 – – UI TJ25.78125_NRZ Total jitter23 NRZ 25.78125 Gb/ s – – UI DJ25.78125_NRZ Deterministic jitter23 – – UI TJ24_NRZ Total jitter23 NRZ 24 Gb/s – – UI DJ24_NRZ Deterministic jitter23 – – UI TJ15_NRZ Total jitter23 NRZ 15 Gb/s – – UI DJ15_NRZ Deterministic jitter23 – – UI TJ12_NRZ Total jitter23 NRZ 12 Gb/s – – UI DJ12_NRZ Deterministic jitter23 – – UI TJ10.1_NRZ Total jitter23 NRZ 10.1 Gb/s – – UI DJ10.1_NRZ Deterministic jitter23 – – UI TJ9.8_NRZ Total jitter23 NRZ 9.8 Gb/s – – UI DJ9.8_NRZ Deterministic jitter23 – – UI Notes: 1. Using same REFCLK input with TX phase alignment enabled for up to two consecutive transmitters (one fully populated GTM dual) at maximum line rate. 2. Using LCPLL_FBDIV = 40, 80-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 3. All jitter values are based on a bit-error ratio of 10 –12. Table 65: GTM Transceiver Receiver Switching Characteristics Symbol Description Condition Min Typ Max Units FGTMRX Serial data rate 0.500 – FGTMMAX Gb/s RXRL Run length (CID) – – 256 UI RXPPMTOL Data/REFCLK PPM offset tolerance –200 – 200 ppm SJ Jitter Tolerance2 JT_SJ58_PAM4 Sinusoidal jitter PAM4 58 Gb/s – – UI JT_SJ56.42_PAM4 Sinusoidal jitter PAM4 56.42 Gb/s – – UI JT_SJ53.125_PAM4 Sinusoidal jitter PAM4 53.125 Gb/s – – UI JT_SJ52.125_PAM4 Sinusoidal jitter PAM4 52.125 Gb/s – – UI JT_SJ48_PAM4 Sinusoidal jitter PAM4 48 Gb/s – – UI JT_SJ28.21_PAM4 Sinusoidal jitter PAM4 28.21 Gb/s – – UI JT_SJ19.6_PAM4 Sinusoidal jitter PAM4 19.6 Gb/s – – UI JT_SJ29_NRZ Sinusoidal jitter 3 NRZ 29 Gb/s – – UI JT_SJ28.21_NRZ Sinusoidal jitter 3 NRZ 28.21 Gb/s – – UI JT_SJ26.5625_NRZ Sinusoidal jitter 3 NRZ 26.5625 Gb/s – – UI Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 54 Send Feedback

Table 65: GTM Transceiver Receiver Switching Characteristics (cont'd) Symbol Description Condition Min Typ Max Units JT_SJ25.78125_NRZ Sinusoidal jitter 3 NRZ 25.78125 Gb/s – – UI JT_SJ24_NRZ Sinusoidal jitter3 NRZ 24.0 Gb/s – – UI JT_SJ15_NRZ Sinusoidal jitter3 NRZ 15.0 Gb/s – – UI JT_SJ12_NRZ Sinusoidal jitter3 NRZ 12.0 Gb/s – – UI JT_SJ10.1_NRZ Sinusoidal jitter3 NRZ 10.1 Gb/s – – UI JT_SJ9.8_NRZ Sinusoidal jitter3 NRZ 9.8 Gb/s – – UI Notes: 1. Using RXOUT_DIV = 1, 2, and 4. 2. All jitter values are based on a bit error ratio of 10 –12. 3. The frequency of the injected sinusoidal jitter is 80 MHz. GTM Transceiver Electrical Compliance The Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581) contains recommended use modes that ensure compliance for the protocols listed in the following table. The transceiver wizard provides the recommended se ttings for those use cases and for protocol specific char act eristics. Table 66: GTM Transceiver Protocol List Protocol Specification Modulation Serial Rate (Gb/s) Electrical Compliance 400GE (CDAUI8) IEEE 802.3bs (400GE), OIF-CEI-56G-VSR PAM4 53.125 Compliant 200GE (CCAUI4) QSFP561 PAM4 53.125 Compliant 100GE (CAUI2) chip-to-optics IEEE802.3ba (100GE), OIF-CEI-56G-VSR PAM4 53.125 Compliant 100GE (CAUI4) chip-to-chip OIF-CEI-56G-MR PAM4 53.125 Compliant 100GE (CAUI4) IEEE 802.3bm2 NRZ 25.78125 Compliant 50G LAUI IEEE (50GE) LAUI, OIF-CEI-VSR PAM4 52.125 Compliant 50GE LAUI2 (2 x 25G) chip-to-optics OIF-CEI-28G-VSR NRZ 26.5625 Compliant 10G-15G backplane capability 10G NRZ interfaces over customer backplane including high-confident region NRZ 15 Compliant Ethernet AN/LT (autonegotiation/ link training) IEEE802.3an3 NRZ Compliant 28.21G PAM4 backplanes Insertion loss @ Nyquist (7.05 GHz) at BER < 10e-17 with FEC PAM4 28.21 Compliant 58G PAM4 backplanes GTM supports 802.3bj style backplanes at 58 Gb/s (35 dB with RS (544, 514) FEC) PAM4 58 Compliant OTU4 optical modules NRZ optical 7% FEC 100G OTU4 and OTUCn requirements to CFP2, CFP4, and QSFP28 optics, OIF-CEI28-VSR NRZ 28.21 Compliant OTU4 optical module PAM4 optical 7% FEC 100G QSFP56, OIF-CEI56-VSR PAM4 56.4 Compliant Interlaken 25.78125G OIF-CEI-25G-MR @ 20 dB loss NRZ 25.78125 Compliant Interlaken 12.5G OIF-CEI-11G-SR (extended) NRZ 12.5 Compliant CPRI 48G PAM4 Fibre channel datapath and 1-lane FEC mode with customer alignment with 64/66 encoding PAM4 48 Compliant Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 55 Send Feedback

Table 66: GTM Transceiver Protocol List (cont'd) Protocol Specification Modulation Serial Rate (Gb/s) Electrical Compliance CPRI 24G, 12G, and 10.1G NRZ CPRI_v_6_1_2014-07-01 NRZ 24, 12, 10.1 Compliant Notes: 1. FEC, PCS, and MAC are soft. 2. Specified with loss target of 15 dB @ Nyquist. 3. Requires lock to reference on aper-lane basis and oversampling logic in the device logic to capture the slower autonegotiation. Integrated Interface Block for Interlaken More in f ormation and documen tation on solutions using the integrated interface block for Interlaken can be found at UltraScale+ Interlaken. The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each Virtex UltraScale+ FPGA. This section describes the following Interlaken c on figur ations.

• 12 x 12.5 Gb/s protocol and lane logic mode (Table 67).
• 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s protocol and lane logic mode (Table 68).
• 12 x 25.78125 Gb/s lane logic only mode (Table 69). Virtex UltraScale+ FPGAs in the FLVF1924 package are only supported using the 12 x 12.5 Gb/s Interlaken c on figur ation. See the FGTYMAX maximum line rates. Table 67: Maximum Performance for Interlaken 12 x 12.5 Gb/s Protocol and Lane Logic Mode Designs Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FRX_SERDES_CLK Receive serializer/ deserializer clock 195.32 195.32 195.32 195.32 MHz FTX_SERDES_CLK Transmit serializer/ deserializer clock 195.32 195.32 195.32 195.32 MHz FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 250.00 250.00 MHz Min1 Max Min1 Max Min1 Max Min1 Max Notes: 1. These are the minimum clock frequencies at the maximum lane performance. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 56 Send Feedback

Table 68: Maximum Performance for Interlaken 6 x 25.78125 Gb/s and 6 x 28.21 Gb/s Protocol and Lane Logic Mode Designs Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -31 -21 -1 -2 FRX_SERDES_CLK Receive serializer/ deserializer clock 440.79 440.79 N/A 402.84 MHz FTX_SERDES_CLK Transmit serializer/ deserializer clock 440.79 440.79 N/A 402.84 MHz FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 N/A 250.00 MHz Min2 Max Min2 Max Min Max Min2 Max Notes: 2. These are the minimum clock frequencies at the maximum lane performance. 3. The minimum value for CORE_CLK is 451.36 MHz for the 6 x 28.21 Gb/s protocol. 4. The minimum value for LBUS_CLK is 330.00 MHz for the 6 x 28.21 Gb/s protocol. Table 69: Maximum Performance for Interlaken 12 x 25.78125 Gb/s Lane Logic Only Mode Designs Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FRX_SERDES_CLK Receive serializer/ deserializer clock 402.84 402.84 N/A N/A MHz FTX_SERDES_CLK Transmit serializer/ deserializer clock 402.84 402.84 N/A N/A MHz FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 N/A N/A MHz FCORE_CLK Interlaken core clock 412.50 412.50 N/A N/A MHz FLBUS_CLK Interlaken local bus clock 349.52 349.52 N/A N/A MHz Integrated Interface Block for 100G Ethernet MAC and PCS More in f ormation and documen tation on solutions using the integrated 100 Gb/s Ethernet block can be found at UltraScale+ Integrated 100G Ethernet MAC/PCS. The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each Virtex UltraScale+ FPGA. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 57 Send Feedback

Table 70: Maximum Performance for 100G Ethernet Designs Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 CAUI-10 Mode FTX_CLK Transmit clock 390.625 390.625 322.266 322.266 MHz FRX_CLK Receive clock 390.625 390.625 322.266 322.266 MHz FRX_SERDES_CLK Receive serializer/deserializer clock 390.625 390.625 322.266 322.266 MHz FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 250.00 250.00 MHz CAUI-4, CAUI-4 + RS-FEC, and RS-FEC Transcode Bypass Modes FTX_CLK Transmit clock 390.625 322.266 322.266 322.266 MHz FRX_CLK Receive clock 390.625 322.266 322.266 322.266 MHz FRX_SERDES_CLK Receive serializer/deserializer clock 390.625 322.266 322.266 322.266 MHz FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 250.00 250.00 MHz Integrated Interface Block for PCI Express Designs More in f ormation and documen tation on solutions for PCI Express® designs can be found at PCI Express. The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many blocks are in each Virtex UltraScale+ FPGA. Devices with HBM contain a mixture of PCIE4 and PCIE4C blocks. The PCIE4C blocks are augmented with support for the CCIX protocol and additional timing enhancements allowing the PCIE4C blocks to run Gen3 x16 when VCCINT = 0.72V. Table 71: Maximum Performance for PCIE4-based PCI Express Designs Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 250.00 MHz FCORECLK Core clock maximum frequency 500.00 500.00 500.00 250.00 MHz FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 250.00 MHz FMCAPCLK MCAP clock maximum frequency 125.00 125.00 125.00 125.00 MHz Table 72: Maximum Performance for PCIE4C-based PCI Express and CCIX Designs Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 250.00 MHz FCORECLK Core clock maximum frequency 500.00 500.00 500.00 500.00 MHz FCORECLKCCIX CCIX TL interface clock maximum frequency 500.00 500.00 500.00 N/A MHz FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 250.00 MHz FMCAPCLK MCAP clock maximum frequency 125.00 125.00 125.00 125.00 MHz Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 58 Send Feedback

High Bandwidth Memory Controller The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Virtex UltraScale+ FPGAs with integrated high-bandwidth memory (HBM). Table 73: Maximum Performance for High Bandwidth Memory Controller Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FHBM_REF_CLK HBM controller reference clock maximum frequency 450.00 450.00 450.00 450.00 MHz FACLK AXI interface clock maximum frequency 450.00 450.00 400.00 400.00 MHz FAPB Advance peripheral bus (APB) clock maximum frequency 100.00 100.00 100.00 100.00 MHz FHBM HBM maximum line rate interface to DRAM 1800 1800 1600 1800 Mb/s System Monitor Specifications Table 74: System Monitor Specifications Parameter Symbol Comments/Conditions Min Typ Max Units VCCADC = 1.8V ±3%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = –40°C to 100°C, typical values at Tj = 40°C ADC Accuracy1 Resolution 10 – – Bits Integral nonlinearity2 INL – – ±1.5 LSBs Differential nonlinearity DNL No missing codes, guaranteed monotonic – – ±1 LSBs Offset error Offset calibration enabled – – ±2 LSBs Gain error – – ±0.4 % Sample rate – – 0.2 MS/s RMS code noise External 1.25V reference – – 1 LSBs On-chip reference – 1 – LSBs ADC Accuracy at Extended Temperatures Resolution Tj = –55°C to 125°C 10 – – Bits Integral nonlinearity2 INL Tj = –55°C to 125°C – – ±1.5 LSBs Differential nonlinearity DNL No missing codes, guaranteed monotonic Tj = –55°C to 125°C – – ±1 Analog Inputs2 ADC input ranges Unipolar operation 0 – 1 V Bipolar operation –0.5 – +0.5 V Unipolar common mode range (FS input) 0 – +0.5 V Bipolar common mode range (FS input) +0.5 – +0.6 V Maximum external channel input ranges Adjacent channels set within these ranges should not corrupt measurements on adjacent channels –0.1 – VCCADC V Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 59 Send Feedback

Table 74: System Monitor Specifications (cont'd) Parameter Symbol Comments/Conditions Min Typ Max Units On-Chip Sensor Accuracy Temperature sensor error1, 3 Tj = –55°C to 125°C (with external REF) – – ±3 °C Tj = –55°C to 110°C (with internal REF) – – ±3.5 °C Tj = 110°C to 125°C (with internal REF) – – ±5 °C Supply sensor error4 Supply voltages 0.72V to 1.2V, Tj = –40°C to 100°C (with external REF) – – ±0.5 % Supply voltages 0.72V to 1.2V, Tj = –55°C to 125°C (with external REF) – – ±1.0 % All other supply voltages, Tj = –40°C to 100°C (with external REF) – – ±1.0 % All other supply voltages, Tj = –55°C to 125°C (with external REF) – – ±2.0 % Supply voltages 0.72V to 1.2V, Tj = –40°C to 100°C (with internal REF) – – ±1.0 % Supply voltages 0.72V to 1.2V, Tj = –55°C to 125°C (with internal REF) – – ±2.0 % All other supply voltages, Tj = –40°C to 100°C (with internal REF) – – ±1.5 % All other supply voltages, Tj = –55°C to 125°C (with internal REF) – – ±2.5 % Conversion Rate5 Conversion time—continuous tCONV Number of ADCCLK cycles 26 – 32 Cycles Conversion time—event tCONV Number of ADCCLK cycles – – 21 Cycles DRP clock frequency DCLK DRP clock frequency 8 – 250 MHz ADC clock frequency ADCCLK Derived from DCLK 1 – 5.2 MHz DCLK duty cycle 40 – 60 % SYSMON Reference6 External reference VREFP Externally supplied reference voltage 1.20 1.25 1.30 V On-chip reference Ground VREFP pin to AGND, Tj = –40°C to 100°C 1.2375 1.25 1.2625 V Ground VREFP pin to AGND, Tj = –55°C to 125°C 1.225 1.25 1.275 V Notes: 1. ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is enabled. 2. See the Analog Input section in the UltraScale Architecture System Monitor User Guide (UG580). 3. When reading temperature values directly from the PMBus interface, the SYSMON has a +4°C offset due to the transfer function used by the PMBus application. For example, the external REF temperature sensor error’s range of ±3°C becomes +1°C to +7°C when the temperature is read through the PMBus interface. 4. Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified for when this feature is enabled. 5. See the Adjusting the Acquisition Settling Time section in the UltraScale Architecture System Monitor User Guide (UG580). 6. Any variation in the reference voltage from the nominal V REFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 60 Send Feedback

SYSMON I2C/PMBus Interfaces Table 75: SYSMON I2C Fast Mode Interface Switching Characteristics Symbol Description1 Min Max Units TSMFCKL SCL Low time 1.3 – µs TSMFCKH SCL High time 0.6 – µs TSMFCKO SDAO clock-to-out delay – 900 ns TSMFDCK SDAI setup time 100 – ns FSMFCLK SCL clock frequency – 400 kHz Notes: 1. The test conditions are configured to the LVCMOS 1.8V I/O standard. Table 76: SYSMON I2C Standard Mode Interface Switching Characteristics Symbol Description1 Min Max Units TSMSCKL SCL Low time 4.7 – µs TSMSCKH SCL High time 4.0 – µs TSMSCKO SDAO clock-to-out delay – 3450 ns TSMSDCK SDAI setup time 250 – ns FSMSCLK SCL clock frequency – 100 kHz Notes: 1. The test conditions are configured to the LVCMOS 1.8V I/O standard. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 61 Send Feedback

Configuration Switching Characteristics Table 77: Configuration Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 Power-up Timing Characteristics TPL Program latency 8.5 8.5 8.5 8.5 ms, Max TPOR Power-on reset (40 ms maximum ramp rate) 65 65 65 65 ms, Max 0 0 0 0 ms, Min Power-on reset with POR override (2 ms maximum ramp rate) 15 15 15 15 ms, Max 5 5 5 5 ms, Min TPROGRAM Program pulse width 250 250 250 250 ns, Min CCLK Output (Master Mode) TICCK Master CCLK output delay from INIT_B 150 150 150 150 ns, Min TMCCKL1 Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 %, Min/Max TMCCKH Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/60 %, Min/Max FMCCK Master BPI (x8/x16) SPI (x1/x2/x4) CCLK frequency XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P 125 125 125 100 MHz, Max Master SPI (x1/x2/x4) CCLK frequency XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 125 125 125 100 MHz, Max Master BPI (x8/x16) SPI (x8) CCLK frequency XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 125 125 125 60 MHz, Max FMCCK_START Master CCLK frequency at start of configuration 2.7 2.7 2.7 2.7 MHz, Typ FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK CCLK Input (Slave Mode) TSCCKL Slave CCLK clock minimum Low time 2.5 2.5 2.5 2.5 ns, Min TSCCKH Slave CCLK clock minimum High time 2.5 2.5 2.5 2.5 ns, Min Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 62 Send Feedback

Table 77: Configuration Switching Characteristics (cont'd) Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FSCCK Slave Serial/ Slave SelectMAP CCLK frequency XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P 125 125 125 100 MHz, Max Slave Serial CCLK frequency XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 125 125 125 100 MHz, Max Slave SelectMAP CCLK frequency XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 125 125 125 60 MHz, Max EMCCLK Input (Master Mode) TEMCCKL External master CCLK Low time 2.5 2.5 2.5 2.5 ns, Min TEMCCKH External master CCLK High time 2.5 2.5 2.5 2.5 ns, Min FEMCCK External master CCLK frequency XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P 125 125 125 100 MHz, Max XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 125 125 125 60 MHz, Max Internal Configuration Access Port FICAPCK Internal configuration access port (ICAPE3) XCVU3P, XQVU3P 200 200 200 150 MHz, Max Master SLR ICAPE3 accessing entire device XCVU5P, XCVU7P, XQVU7P, XCVU9P, XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 125 125 125 125 MHz, Max SLR ICAPE3 accessing local SLR XCVU5P, XCVU7P, XQVU7P, XCVU9P, XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 200 200 200 150 MHz, Max Slave Serial Mode Programming Switching TDCCK/TCCKD DIN setup/hold 3.0/0 3.0/0 3.0/0 4.0/0 ns, Min TCCO DOUT clock to out 8.0 8.0 8.0 9.0 ns, Max SelectMAP Mode Programming Switching TSMDCCK/TSMCCKD D[31:00] setup/hold XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 63 Send Feedback

Table 77: Configuration Switching Characteristics (cont'd) Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 TSMCSCCK/TSMCCKCS CSI_B setup/hold XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P TSMWCCK/TSMCCKW RDWR_B setup/hold XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P TSMCKCSO CSO_B clock to out (330Ω pull-up resistor required) XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P 7.0 7.0 7.0 7.0 ns, Max XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 7.0 7.0 7.0 10.0 ns, Max TSMCO D[31:00] clock to out in readback XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P 8.0 8.0 8.0 8.0 ns, Max XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 8.0 8.0 8.0 10.0 ns, Max FRBCCK Readback frequency XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P 125 125 125 100 MHz, Max XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 125 125 125 60 MHz, Max Boundary-Scan Port Timing Specifications TTAPTCK/TTCKTAP TMS and TDI setup/ hold XCVU5P, XCVU7P, XQVU7P, XCVU9P, XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 64 Send Feedback

Table 77: Configuration Switching Characteristics (cont'd) Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 TTCKTDO TCK falling edge to TDO output XCVU3P, XQVU3P 7.0 7.0 7.0 7.0 ns, Max XCVU5P, XCVU7P, XQVU7P, XCVU9P, XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 15.0 15.0 15.0 15.0 ns, Max FTCK TCK frequency XCVU3P, XQVU3P 66 66 66 66 MHz, Max XCVU5P, XCVU7P, XQVU7P, XCVU9P, XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P 20 20 20 20 MHz, Max BPI Master Flash Mode Programming Switching TBPICCO A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B clock to out 10 10 10 10 ns, Max TBPIDCC/TBPICCD D[15:00] setup/hold XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P SPI Master Flash Mode Programming Switching TSPIDCC/TSPICCD D[03:00] setup/hold 3.0/0 3.0/0 3.0/0 4.0/0 ns, Min TSPIDCC/TSPICCD D[07:04] setup/hold XCVU3P, XQVU3P, XCVU5P, XCVU7P, XQVU7P, XCVU9P XCVU11P, XQVU11P, XCVU13P, XCVU27P, XCVU29P, XCVU31P, XCVU33P, XCVU35P, XCVU37P TSPICCM MOSI clock to out 8.0 8.0 8.0 8.0 ns, Max TSPICCM2 D[04] clock to out 10.0 10.0 10.0 10.0 ns, Max TSPICCFC FCS_B clock to out 8.0 8.0 8.0 8.0 ns, Max TSPICCFC2 FCS2_B clock to out 10.0 10.0 10.0 10.0 ns, Max DNA Port Switching FDNACK DNA port frequency 200 200 200 175 MHz, Max STARTUPE3 Ports TUSRCCLKO STARTUPE3 USRCCLKO input port to CCLK pin output delay Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 65 Send Feedback

Table 77: Configuration Switching Characteristics (cont'd) Symbol Description Speed Grade and VCCINT Operating Voltages Units0.90V 0.85V 0.72V -3 -2 -1 -2 FCFGMCLK STARTUPE3 CFGMCLK output frequency 50 50 50 50 MHz, Typ FCFGMCLKTOL STARTUPE3 CFGMCLK output frequency tolerance TDCI_MATCH Specifies a stall in the startup cycle until the digitally controlled impedance (DCI) match signals are asserted 4 4 4 4 ms, Max Notes: 1. When the CCLK is sourced from the EMCCLK pin with a divide-by-one setting, the external EMCCLK must meet this duty-cycle requirement.

Revision History

Date Version Description of Revisions 04/26/2019 1.10 Updated Table 16, Table 17, and Table 18 to production release the following devices in the Vivado Design Suite. XQVU3P: 2018.3 v1.23 XQVU7P: 2018.3.1 v1.23 XQVU11P: 2018.3.1 v1.23 In Table 1, revised the TSTG. Added Note 14 in Table 2. Updated the VU3xP values in Table 6. Added LVDS component mode notes to FPGA Logic Performance Characteristics. 01/04/2019 1.9 Added the XCVU27P and XCVU29P devices. Also added the GTM Transceiver Specifications. Updated the calculations in Table 6: Power-on Current by Device Updated the speed specification version by device for Table 16 to Vivado Design Suite 2018.3. Updated the VIDIFF description in Table 15. In Table 51, updated Note 2. Removed PCI Express Gen4 support in Table 71: Maximum Performance for PCIE4-based PCI Express Designs and Notes 1, Note 2, and Note 3. In Table 72: Maximum Performance for PCIE4C-based PCI Express and CCIX Designs, removed Notes 1, 2, 3, 4, and 5. 08/01/2018 1.8 Added XCVU3xP data to Table 5. Updated the speed specification version by device for Table 16 to Vivado Design Suite 2018.2.1. In Table 20, added Note 4 to the LVDS RX DDR maximum data. In Table 70, revised the calculated values from 322.223 to 322.266. 06/18/2018 1.7 Revised the speed grade -1 (VCCINT = 0.85) FGTYMAX in Table 46, which also revised values in Table 51 and added Note 2. Revised FACLK and added FHBM to Table 73. Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics DS923 (v1.10) April 26, 2019 www.xilinx.com Product Specification 66 Send Feedback

Sequencing section, Table 6, Table 7, and Table 73. specifications and remove Note 1. Added Table 72. Revised some of the -3E (VCCINT = 0.90V) speed files in Table 35, Table 36, Table 37, and Table 39. Revised the DVPPOUT control signal in Table 43. 11/28/2017 1.4 In Table 1, corrected the minimum voltage for the System Monitor section. (VCCINT = 0.72V) devices/speed/temperature grades in Vivado Design Suite 2017.3.1. Revised the FREFCLK descriptions in Table 30. added package values to Table 42. Revised the FGTYQRANGE2 -1 speed grade minimum in Table 46. Added TSPICCM2 and TSPICCFC2 to Table 77. following devices/speed/temperature grades in Vivado Design Suite 2017.2.1. DIFF_SSTL15_DCI_S, DIFF_SSTL15_S, DIFF_SSTL18_I_DCI_S, and DIFF_SSTL18_I_S. Revised some of the -3E and -2LE (VCCINT = 0.72V) speed files in Table 24, Table 35, Table 36, and Table 37. grades in Vivado Design Suite 2017.2.

1. Added Note 1 to Table 31. Added Note 3 to Table 71. In Table 77, updated the -2LE (VCCINT = 0.72V)

and Note 9. Updated and added data to Table 2 through Table 6. Removed the -1LI speed grade. Table 39. Added data to Table 40 and Table 42. Updated the GTY Transceiver Specifications section. section adding notes to the tables. Updated the Configuration Switching Characteristics section. Removed the eFUSE Programming Conditions table and added the specifications to Table 2 and Table 3. Updated the Automotive Applications Disclaimer. 04/20/2016 1.0 Initial Xilinx release.

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