A160CB10VF

AM29SL160C_07 AMD | Alldatasheet

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Publication Number 21635 Revision C Amendment 5 Issue Date January 23, 2007 The following document contains information on Spansion memory products. Although the document is marked with the name of the company that orig inally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29SL160C Data Sheet

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This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21635 Rev: C Amendment/5 Issue Date: January 23, 2007 Am29SL160C

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 1.8 Volt-only Super Low Voltage Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Secured Silicon (SecSi) Sector: 256-byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Customer may program own custom data. Once locked, data cannot be changed ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero ■ Package options — 48-ball FBGA — 48-pin TSOP ■ Top or bottom boot block ■ Manufactured on 0.32 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power- supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast 100 ns — Program time: 8 µs/word typical using Accelerate ■ Ultra low power consumption (typical values) — 1 mA active read current at 1 MHz — 5 mA active read current at 5 MHz — 1 µA in standby or automatic sleep mode ■ Minimum 1 million erase cycles guaranteed per sector ■ 20 Year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Supports Common Flash Memory Interface (CFI) ■ Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to reading array data ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ Sector protection — Hardware method of locking a sector, either in- system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system

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The Am29SL160C is a 16 Mbit, 1.8 V volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The data appears on DQ0–DQ15. The device is offered in 48-pin TSOP and 48-ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed and erased in-system with a single 1.8 volt V CC supply. No VPP is required for program or erase operations. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 90, 100, 120, or 150 ns, allowing microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 1.8 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Com- mands are written to the command register using standard microprocessor write timings. Register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automati- cally preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits . After a program or erase cycle completes, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector pro- tection feature disables both program and erase operations in any combination of the sectors of memory. This is achieved in-system or via program- ming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly reduced in both modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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Note:See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29SL160C Speed Options -100 -120 -150 Max access time, ns (tACC) 100 120 150 Max CE# access time, ns (tCE) 100 120 150 Max OE# access time, ns (tOE)3 5 5 0 6 5 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# WP#/ACC CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A19

January 23, 2007 21635C5 Am29SL160C 5 DATA SHEET CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A19 NC WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 Standard TSOP

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CONNECTION DIAGRAMS (Continued) Special Handling Instructions for FBGA Packages Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2NCA18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 48-Ball FBGA (Top View, Balls Facing Down)

January 23, 2007 21635C5 Am29SL160C 7 DATA SHEET PIN CONFIGURATION A0–A19 = 20 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) CE# = Chip enable OE# = Output enable WE# = Write enable WP#/ACC = Hardware write protect/acceleration pin RESET# = Hardware reset pin, active low BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy# output V CC = 1.8–2.2 V single power supply VSS = Device ground NC = Pin not connected internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A19 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29SL160C T -100 E C N STANDARD PROCESSING N = SecSi Sector factory-locked with random ESN (Contact an AMD representative for more information) TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40 °C to +85°C) D = Commercial (0oC to +70oC) with Pb-free Package F = Industrial (-40 oC to +85oC) with Pb-free Package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) WC = 48-ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8 x 9 mm package (FBC048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29SL160C

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages AM29SL160CT -100, AM29SL160CB-100 EC, EI ED, EF AM29SL160CT -120, AM29SL160CB-120 AM29SL160CT -150, AM29SL160CB-150 Valid Combinations for FBGA Packages Order Number Package Marking AM29SL160CT -100, AM29SL160CB-100 WCC, WCI, WCD, WCF A160CT10V, A160CB10V C, I, D, F AM29SL160CT -120, AM29SL160CB-120 A160CT12V, A160CB12V AM29SL160CT -150, AM29SL160CB-150 A160CT15V, A160CB15V

describe each of these operations in further detail. Table 1. Am29SL160C Device Bus Operations

1. Addresses are A19:A0 in word mode (BYTE# = V IH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector

Block Protection and Unprotection” on page 15.

1. If WP#/ACC = V IL, the two outermost boot sectors are protected. If WP#/ACC = VIH, the two outermost boot sectors are

used as an input for the LSB (A-1) address function.

0.2 V XX VCC ±

0.2 V X X High-Z High-Z High-Z

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data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” on page 21 for more infor- mation. Refer to the AC table for timing specifications and to Figure 13, on page 35 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” on page 9 for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” on page 22 contains details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2, on page 12 and Table 3, on page 13 indicate the address space that each sector occupies. A “s ector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” on page 21 contains details on erasing a sector or the entire chip, or sus- pending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to “Autoselect Mode” on page 14 and “Autoselect Command Sequence” on page 22 for more information. I CC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” on page 35 contains timing specifica- tion tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operation through the ACC function, which is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster in-system programming of the device during the system production process. If the system asserts V HH on the pin, the device auto- matically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the pin to reduce the time required for pr ogram operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to normal operation. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” on page 27 for more information, and to “AC Characteristics” on page 35 for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.2 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.2 V, the device is in the standby mode, but the standby current is greater. The device requires stan- dard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to “RESET#: Hard- ware Reset Pin” on page 10. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 50 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the

January 23, 2007 21635C5 Am29SL160C 11 DATA SHEET RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ± 0.2 V, the standby current is greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase oper- ation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RESET# pin returns to VIH. Refer to “AC Characteristics” on page 35 for RESET# parameters and to “RESET# Timings” on page 36 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high imped- ance state.

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Table 2. Am29SL160CT Top Boot Sector Architecture

Table 3. Am29SL160CB Bottom Boot Sector Architecture Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section for more information.

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through the command register. command register, as shown in Table 12, on page 26. Table 4. Am29SL160C Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: Outputs for data bits DQ8–DQ15 are for BYTE#=VIH. DQ8–DQ15 are don’t care when BYTE#=VIL.

Table 5. Top Boot Sector/Sector Block Addresses Table 6. Bottom Boot Sector/Sector Block

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The primary method requires V ID on the RESET# pin only, and is implemented either in-system or via pro- gramming equipment. Figure 1, on page 17 shows the algorithms and Figure 24, on page 43 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires V ID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Pub- lication number 21622 contains further details. Contact an AMD representative to request the document con- taining further details. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” on page 14 for details. Write Protect (WP#) The write protect function provides a hardware method of protecting certain boot sectors without using V ID. This function is one of two provided by the WP#/ACC pin. If the system asserts V IL on the WP#/ACC pin, the device disables program and erase functions in the two “outermost” 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection” on page 15. The two out- ermost 8 Kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-con- figured device, or the two sectors containing the highest addresses in a top-boot-configured device. If the system asserts V IH on the WP#/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot sectors were last set to be protected or unpro- tected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection” on page 15. Note that if the system asserts V HH on the WP#/ACC pin, all sectors, including the two outermost sectors, are unprotected. V HH is intended fo r accelerated in- system programming of the device during system pro- duction. It is advisable, therefore, not to assert V HH on this pin after the system has been placed in the field for use. If faster programming is desired, the system may use the unlock bypass program command sequence. Temporary Sector Unprotect This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V ID. During this mode, formerly pro- tected sectors can be programmed or erased by selecting the sector addresses. Once V ID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2, on page 18 shows the algorithm, and Figure 22, on page 42 shows the timing diagrams, for this feature.

Figure 1. In-System Sector Protect/Unprotect Algorithms

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Figure 2. Temporary Sector Unprotect Operation a factory-locked part from being cloned. Table 7. SecSi Sector Addresses sequence, or until power is removed from the device. reverts to sending commands to the boot sectors. WE# do not initiate a write cycle. reset to reading array data on power-up.

1. All protected sectors unprotected. (If WP#/ACC = V IL,
2. All previously protected sectors are protected once

Description

Word Mode (x16) Byte Mode (x8) 16-byte random ESN 00–07h 000–00Fh User-defined code or factory erased (all 1s) 08–7Fh 010–0FFh

interfaces for long-term compatibility. mode), any time the device is ready to read array data. given in Table 8, on page 19 to Table 11, on page 21. representative for copies of these documents. Table 8. CFI Query Identification String

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Table 9. System Interface String Table 10. Device Geometry Definition

Table 11. Primary Vendor-Specific Extended Query sequence resets the device to reading array data. Characteristics” on page 35. more information on this mode.

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before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to read ing array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset comman d returns the device to reading array data (also applies during Erase Suspend). See “AC Characteristics” on page 35 for parameters, and to Figure 14, on page 36 for the timing diagram. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12, on page 26 shows the address and data requirements. This method is an alternative to that shown in Table 4, on page 14 , which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address 01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2, on page 12 and Table 3, on page 13 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Enter SecSi Sector/Exit SecSi Sector Com- mand Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi command sequence. The Exit SecSi command sequence returns the device to normal operation. Table 12, on page 26 shows the address and data requirements for both command sequences. See also “Secured Silicon (SecSi) Sector Flash Memory Region” on page 18 for further information. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or tim- ings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 12, on page 26 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” on page 27 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program- ming operation. The Byte Program command sequence should be reinitiated once the device resets to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc- cessful. However, a succeeding read shows that the data is still “0”. Only erase operations can convert a “0” to a “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is in itiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two- cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 12, on page 26 shows the requirements for the command sequence.

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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any con- trols or timings during these operations. Table 12, on page 26 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation imme- diately terminates the operation. The Chip Erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. The system can determine the status of the erase oper- ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” on page 27 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4, on page 25 illustrates the algorithm for the erase operation. See “Erase/Program Operations” on page 38 for parameters, and Figure 18, on page 40 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 12, on page 26 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts are re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See “DQ3: Sector Erase Timer” on page 29.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be rein- itiated once the device returns to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to “Write Operation Status” on page 27 for information on these status bits.) Figure 4, on page 25 illustrates the algorithm for the erase operation. Refer to the “Erase/Program Opera- tions” on page 38 for parameters, and to Figure 18, on page 40 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend comma nd allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo- rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately ter- minates the time-out period and suspends the erase operation.

on page 22 for more information.

1. See Table 12, on page 26 for erase command sequence.
2. See “DQ3: Sector Erase Timer” on page 29 for more in-

Figure 4. Erase Operation

26 Am29SL160C 21635C5 January 23, 2007

Table 12. Am29SL160C Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A19–A12 uniquely select any sector.

1. See Table 1, on page 9 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t cares in byte mode.
2. Unless otherwise noted, address bits A19–A11 are don’t cares.
3. No unlock or command cycles required when in read mode.
4. The Reset command is required to return to the read mode (or to
5. The fourth cycle of the autoselect command sequence is a read
6. The data is 00h for an unprotected sector and 01h for a protected

Command Sequence section for more information.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or

when device is in autoselect mode.

Suspend mode, Data# Polling produces a “1” on DQ7. the selected sectors that are protected.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm

28 Am29SL160C 21635C5 January 23, 2007

RY/BY#: Ready/Busy# RY/BY# is a dedicated, open-drain output pin that indi- cates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 13, on page 30 shows the outputs for RY/BY#. Figure 14, on page 36 , Figure 17, on page 39 and Figure 18, on page 40 shows RY/BY# for reset, pro- gram, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle (The system may use either OE# or CE# to control the read cycles). When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is acti vely erasing or is erase- suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling” on page 27). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 13, on page 30 shows the outputs for Toggle Bit I on DQ6. Figure 6, on page 29 shows the toggle bit algorithm. Figure 20, on page 41 shows the toggle bit timing diagrams. Figure 21, on page 42 shows the dif- ferences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. The device toggles DQ2 with each OE# or CE# read cycle. DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 13, on page 30 to compare outputs for DQ2 and DQ6. Figure 6, on page 29 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Figure 20, on page 41 shows the toggle bit timing diagram. Figure 21, on page 42 shows the differ- ences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6, on page 29 for the following discus- sion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as DQ5 went high. If the toggle bit is no longer toggling, the device successfully completed the program or erase operation. If it is still toggling, the

the status as described in the previous paragraph. status of the operation (top of Figure 6). accepted the command sequence, and then read DQ3. pend) are ignored until the erase operation is complete. on page 30 shows the outputs for DQ3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5

Figure 6. Toggle Bit Algorithm

30 Am29SL160C 21635C5 January 23, 2007

Table 13. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See

“DQ5: Exceeded Timing Limits” on page 29 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

32 Am29SL160C 21635C5 January 23, 2007

Notes: 1. The I CC current listed is typically less than 1 mA/MHz, with OE# at VIL. Typical VCC is 2.0 V. 2. The maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 50 ns. 5. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 11.0 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 5 10

1 MHz 1 3

CE# = VIL, OE# = VIH, Word Mode (Notes 2, 3, 5) CE# = VIL, OE# = VIH 20 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = V CC±0.2 V 1 5 µA ICC4 VCC Reset Current (Note 2) RESET# = V SS ± 0.2 V 1 5 µA ICC5 Automatic Sleep Mode (Notes 2, 3) VIH = VCC ± 0.2 V; VIL = VSS ± 0.2 V 15 µ A VIL Input Low Voltage –0.5 0.2 x V CC V VIH Input High Voltage 0.8 x V CC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.0 V 9.0 11.0 V VOL Output Low Voltage I OL = 100 μA, VCC = VCC min 0.1 VOH Output High Voltage I OH = –100 μA, VCC = VCC min V CC–0.1 VLKO Low VCC Lock-Out Voltage (Note 4) 1.2 1.5 V

34 Am29SL160C 21635C5 January 23, 2007

Table 14. Test Specifications Figure 11. Test Setup Figure 12. Input Waveforms and Measurement Levels

January 23, 2007 21635C5 Am29SL160C 35 DATA SHEET AC CHARACTERISTICS Read Operations Notes: 1. Not 100% tested. 2. See Figure 11, on page 34 and Table 14, on page 34 for test specifications. Parameter JEDEC Std Test Setup -100 -120 -150 Unit tAVAV tRC Read Cycle Time (Note 1) Min 100 120 150 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 100 120 150 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 100 120 150 ns tGLQV tOE Output Enable to Output Delay Max 35 50 65 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 30 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tDF tOH Figure 13. Read Operations Timings

36 Am29SL160C 21635C5 January 23, 2007

Figure 14. RESET# Timings

38 Am29SL160C 21635C5 January 23, 2007

Notes: 1. Not 100% tested. 2. See “Erase And Programming Performance” on page 46 for more information. Parameter Speed Options JEDEC Std. Description -100 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 120 150 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 50 60 70 ns tDVWH tDS Data Setup Time Min 50 60 70 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 50 60 70 ns tWHWL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 10 µs Word Typ 12 Accelerated Program Operation, Byte or Word (Note 2) Typ 8 µs tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec tVCS VCC Setup Time Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 200 ns

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

40 Am29SL160C 21635C5 January 23, 2007

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

42 Am29SL160C 21635C5 January 23, 2007

Figure 21. DQ2 vs. DQ6 Figure 22. Temporary Sector Unprotect Timing Diagram

44 Am29SL160C 21635C5 January 23, 2007

Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See “Erase And Programming Performance” on page 46 for more information. Parameter Speed Options JEDEC Std. Description -100 -120 -150 Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 120 150 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 50 60 70 ns tDVEH tDS Data Setup Time Min 50 60 70 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 50 60 70 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Notes 1, 2) Byte Typ 10 µs Word Typ 12 Accelerated Program Operation, Byte or Word (Note 2) Typ 8 µs tWHWH2 tWHWH2 Sector Erase Operation (Notes 1, 2) Typ 2 sec

1. PA = program address, PD = program data , DQ7# = complement of the data written, DOUT = data written
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.

Figure 25. Alternate CE# Contro lled Write Operation Timings

46 Am29SL160C 21635C5 January 23, 2007

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 2.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 12, on page 26 for further information on command definitions. 6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time. TSOP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 2 15 s Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 70 s Byte Programming Time 10 300 µs Excludes system level overhead (Note 5) Word Programming Time 12 360 µs Accelerated Program Time, Word/Byte 8 240 µs Chip Programming Time (Note 3) Byte Mode 20 160 s Word Mode 14 120 s Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 11.0 V Input voltage with respect to VSS on all I/O pins –0.5 V V CC + 0.5 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 6 7.5 pF COUT Output Capacitance V OUT = 0 8.5 12 pF CIN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

January 23, 2007 21635C5 Am29SL160C 47 DATA SHEET PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

48 Am29SL160C 21635C5 January 23, 2007

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm package Dwg rev AF; 10/99

January 23, 2007 21635C5 Am29SL160C 49 DATA SHEET REVISION SUMMARY Revision A (December 1998) Initial release. Revision A+1 (January 1999) Distinctive Characteristics WP#/ACC pin: In the third subbullet, deleted reference to increased erase performance. Device Bus Operations Accelerated Program and Erase Operations: Deleted all references to accelerated erase. Sector/Sector Block Protection and Unprotection: Changed section name and text to include tables and references to sector block protection and unprotection. AC Characteristics Accelerated Program Timing Diagram: Deleted refer- ence in title to accelerated erase. Revision A+2 (March 23, 1999) Connection Diagrams Corrected the TSOP pinout on pins 13 and 14. Revision A+3 (April 12, 1999) Global Modified the description of accelerated programming to emphasize that it is intend ed only to speed in-system programming of the device during the system produc- tion process. Distinctive Characteristics Secured Silicon (SecSi) Sector bullet: Added the 8-byte unique serial number to description. Device Bus Operations table Modified Note 3 to indicate sector protection behavior when V IH is asserted on WP#/ACC. Applied Note 3 to the WP#/ACC column for write operations. Added the “N” designator to the optional processing section. Secured Silicon (SecSi) Sector Flash Memory Region Modified explanatory text to indicate that devices now have an 8-byte unique ESN in addition to the 16-byte random ESN. Added table for address range clarification. Revision A+4 (May 14, 1999) Global Deleted all references to the unique ESN. Revision A+5 (July 23, 1999) Global Added 90 ns speed option. Revision A+6 (September 1, 1999) AC Characteristics Hardware Reset (RESET#) table: Deleted t RPD specifi- cation. Erase/Program Operations table: Deleted t OES specification. Revision A+7 (September 7, 1999) Distinctive Characteristics Ultra low power consumption bullet: Corrected values to match those in the DC Characteristics table. AC Characteristics Alternate CE# Controlled Erase/Program Operations: Deleted tOES specification. Revision B (December 14, 1999) AC Characteristics—Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations Deleted t GHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. Revision C (February 21, 2000) Removed “Advance Information” designation from data sheet. Data sheet parameters are now stable; only speed, package, and temperature range combinations are expected to change in future revisions. Device Bus Operations table Changed standby voltage specification to V CC ± 0.2 V. Standby Mode Changed standby voltage specification to VCC ± 0.2 V. DC Characteristics table Changed test conditions for ICC3, ICC4, ICC5 to VCC ± 0.2 Revision C+1 (November 14, 2000) Global Added dash to speed options and OPNs. Added table of contents. AC Characteristics—Read Operations Changed tDF to 16 ns for all speeds.

50 Am29SL160C 21635C5 January 23, 2007

Revision C+2 (June 11, 2002) Secured Silicon (SecSi) Sector Flash Memory Region Deleted reference to A-1 not being used in addressing, and to address bits that are don’t cares. In Table 7, changed lower address bit for user-defined code to 08h (word mode) and 010h (byte mode). Revision C+3 (November 1, 2004) Global Added colophon and reference links. Added temperature ranges for Pb-free Package Valid Combinations for TSOP Packages Added ED, and EF combinations. Valid Combinations for FBGA Packages Added WCD, and WCF to Order Number column, and added D, and F to Package Marking column. Revision C4 (July 13, 2005) Global Deleted 90 ns speed option. Deleted options for extended temperature range in Pb- free packages. Revision C5 (January 23, 2007) Erase and Program Operations table Changed tBUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright ©1998–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.