80188-10B

80188 AMD | Alldatasheet

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High Integration 8-Bit Microprocessor iAPX86 Family EI DISTINCTIVE CHARACTERISTICS 3 © Integrated feature set © High-performance processor _ Enhanced 10 MHz 8088-1 CPU Two times the performance of the standard 8088 Glock generator 2.25 Mbyte/sec bus bandwidth interface Two independent, high-speed OMA channels © Direct addressing capability to 1 Mbyte of memory Programmable interrupt controller © Completely object code compatible with all existing Three programmable 16-bit timors iAPX 86, 88 software Programmable memory and peripheral chip-select Ten new instruction types logic Compatible with 29843/45, 29833/63, 8284, and Programmable wait state generator 8288 bu s support components Local bus controller ‘© Optional numeric processor extension ‘© Eight-bit data bus interface, 16-bit internal architecture © Available in 68-pin Plastic Leaded Chip Carrier (PLCC), © Available in 10 MHz (80188-10), 8 MHz (80188) Ceramic Leadless Chip Carrior (LCC), and Pin Grid Array > (PGA) packages. GENERAL DESCRIPTION Q “The 80188 is a highly-integrated microprocessor with an the standard 5 MHz 8088. The 80188 is upward compatible 2 8-bit data bus interface and a 16-bit internal architecture for with 8086 and 8088 software and adds 10 new instruction | high performance. It effectively combines 15-20 of the most _ types to the existing set. a common iAPX 86 system components onto one. The ; The 80188 comes in a 68-pin package and requires a single

8 MHz 80188 provides two times greater throughput thane Ya ner guna, ny

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Leadiess Chip Carrier (LCC*) Top Bottom en an sgumbesest | TeBEEE 3 2 JL SL IL JL SL SL JU JL UL SL ak SLL St st sb ES Ze ie = =arens 2s LNW ABEL EL EEETETTEEEPSL *LOC package placed in socket top down. “ Pin Grid Array (PGA) Pins Facing Up Pins Facing Down Ll | NOL OLOLOROLCLOROOLC) @OO0©OOHHOOO exo) O® ©O ®® exo ® exo) O® ®® Xo) ©o O® OO Xo) ©© ato) NOLOROROLCLOLOLOLONS) ®OOCOGOQOO® ®©OOOOOOO OLOLOLOLOXGLOLONO) \\ ono um”

CONNECTION DIAGRAMS (Cont'd.) Plastic Leaded Chip Carrier (PLCC) Top Bottom Papa FAP pared papel PaPAP ear aFa © faninintrinintninininninicintncen By be) Go op) by sho ops: - Gal fi} “Geo ops ec a vfbe obo a] fi) zo ofc Eq po) Oc op)? ) {3} seo oe fa] fa se opie ce 7B op}s ce 15] och oF} [a fe so of} Ea [3] «po ops ce 2) 2Beo =) | 2} 2To o-p)s0 en ng ibe SB. » BSBEBEBEEEEEEE NA Voth Tow Te es 60010530 PLCC package placed in socket top up. (PLCC pin-out same as LCC.) LOGIC SYMBOL Arg! SB-Ayy/ SE * —) pe Aehss, Jouxour —) TMA 1 ADyAD, rar out + fra no —) TMA out 0 ne saoy a AROY a rest . rat er RTA os INT 2/IRTAD DER] ins oun wo co Fes reset — TS LDA) How ne orc Tes nay] (reso POSB/AY FESB/a2 Ls001970

ORDERING INFORMATION

‘Commodity Products ‘AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type ©. Device Number d. Speed Option e. Optional Processing

1 AR 80188 -_

L_ . OPTIONAL PROCESSING B= Burnin d. SPEED OPTION Blank = 8 MHz -10 = 10 MHz ©, DEVICE NUMBER/DESCRIPTION 80188 High Integration 8-Bit Microprocessor b. PACKAGE TYPE R = 68-Pin Ceramic Leadiess Chip Carrier (CA2068) N = 68-Pin Plastic Leaded Chip Carrier (PL 068) A= 68-Pin Grid Array (CGX068) a. TEMPERATURE RANGE* Blank = Commercial (0 to + 70°C) |= Industrial (-40 to +85°C) Valid Combinations Valid combinations list configurations planned to be [Valid Combinations _| ‘supported in volume for this device. Consult the local Valid Combinations AMD sales office to confirm availabilty of specific valid ARN combinations, to check on newly released valid : combinations, and to obtain additional data on AMD's standard military grade products. *This device is also available in Military temperature range. See MOS Micro-processors and Peripherals Handbook (Order #09275A/0) for electrical performance characteristics.

[Active state] Name | vo Description [ [Wor voo_[ 1 Syitom Power 78 vo power oo es a Reset Output indicates that the 80188 CPU is being reset; and can be used as a system reset. It is. £55 RARE ats th Be pes Soda ane nj’ nanar Sos Pos corresponding to the length of the signal. Crystal inputs, X1 and X2, provide an external connection for a fundamental mode parailel resonant ~ Re oe eae re ee nae eS sya ee Se a maceensy & tay ced ante gone eoek sal ROUT) CLKOUT Clock Output provides the system with a 50% duty cycle wavetorm. All device pin timings are specified Seek Od ren Frans mite MOM Sle capuoncn tt ercnte ieeeoer waa waive To Sytem, Reset cots the OGT68 to immed tarrnae rosso, close ara oge Ses ee cae ee Lame saree tee tae Got Tha Sous bodes fetching instructions approximately 7 clock cycles after FES is returned HIGH. RES is required to be epee rd ee err nae ect aed ic mt ac HIGH transition of RES must occur no sooner than 50 microseconds after power up. This input is provided with a Schmitt-tngger to facilitate power-on RES generation via an RC network. When RES Se a ee ran aes Sere ae Stas ee Active LOW TEST is examined by the WAIT instruction. If the TEST input is HiGH when "WAIT" execution begins, instruction execution will suspend. TEST will be resampled until it goes LOW, at which time execution: will resume. If interrupts are enabled while the 80188 is waiting for TEST, interrupts will be serviced. Se rat! Tie Tine eps awd ler ano oonbo age, dpedng jon Te pagrraned ine ae TH ina earn orien atone ap TOUT Tr Sopa a sed ie rode Wie be or roo eavcaen geveraion deparing wean Be a our? pepe DRQO DMA Request is driven HIGH by an external device when it desires that a DMA channel (Channel 0 or 1) oRQ1 perform a transfer. These signals are active HIGH, level-triggered, and internally synchronized. Rordisslail taxrpts oeiqeiggredipt wi comes # pe Zhlaript Nile rot resale Ree re ee ee ee ee ite cea recess peor Min Peter en pond ome peice patie er see fae TR TT Nestbietarapt Roque can bo toqmned by araing on of osepa When conigued es _ or INT2/INTAG 170. _ | inputs, these pins are active HIGH. Interrupt Requests are synchronized intemally. INT2 and INT3 may Low | INTS/INTAT 70 | be configured via software to provide active-LOW interrupt-acknowledge output signals. All interrupt Fe ee a ae a ceed tee recnr te al Pc etetetebelpintt re eae oobi erie ascent pepe beper oper rect ey ete abn fae GR | Maree | tabbaes Bs Gps 81) and on Oye Ste Ga) oot eT moat mate aos ie niaves Ro ee a a ae means eekie ese olsen menns cae ae i a A TT ‘$3, S4, and S5 are defined as LOW during To-Ta. TOFADS 70 | attens(Oam Goa f7) sanae Sontnas Ba Gea asad Ty UD aoe Thy on ae (Ta, Ts. Tw. and T4) bus. Rave HIGH [ AISA’ | 0 | Aderess-oniy Bus (6-15), containing valid address from Ty Ta [rwenor [sr 8 This signal is always HIGH to indicate that the 80188 has an 8-bit data bus and is tri-state OFF during war ALE/QSO ‘Address Latch Enable/Queue Status 0 is provided by the 80188 to latch the address into the 8282/ Care ee ere ee ee ee ects Montz See Se ee ea eet te anocumd ne cycle, effectively one-half clock cycle earlier than in the standard 8088. The trailing edge is generated Sree are one So ee eae an a ee cee

PIN DESCRIPTION (Cont.) [Active state| Name | VO | Description’ = Fotve Low | WA/OSt Wrte Svobe/Quoue Status | indicates that the data on the bus is to be written into a memory or an 1/0 See ee a an ee eee Tree aemes act be pro tO nt Mera cebred ar terete Mier eter WR/QS1 pins provide information about processor/instruction queue interaction. (ost [050 | ueve Operation a a (Try te eee ‘Active LOW RO/OSMD Read Strobe indicates that the 80188 is performing a memory or I/O read cycle. AID is active LOW for Ferty aa rays op es nanand ata (Ban ea she hao dns floated. RD is active LOW, and floats during "HOLD." is driven HIGH for one clock during Reset, and then the output driver is floated. A weak internal pull-up mechanism on the AD line holds HIGH re tent tt oe A ee ee CU aC Ore we Gotan ad provide ALE, WR, and RD, or if the Queue-Status should be provided. FID should be connected to GND to provide Queve-Status data. any operas Hendy hig ts OOTES Tal ho aonsed manny space o 70 doves wl comple EE eS ET ae oe re woceia Goes eee nn ee a ne MabY oun te pt Kecodepir log rpg pobioe ot iets gdp boca acted pint denen her ae Mame paper reread See oe ee Dae font cee te peppers meet Cee a ara sare Sk Tae WG | SRY Syoctrenous Reaoy most be Synctronaed ofraly we Ww BOW, Tho vse of SADY proves a Sr eee ee ee al neared ecing fa cnealt ee a ee rat cea onen whe se MIT ee ope arh erp re eatrig em pogiient yrettden ind ee ee reacatun cei ianrae tinea, Cao eee en ee ee ee rene mst A nS Saal peak ‘Active LOW TOCK ‘TORK output indicates that other system bus masters are not to gain control of the system bus while TOCK is active LOW. The COCK signal is requested by the LOCK prefix instruction and is activated at Coe a ee nt ee en Oe mete eres a a ee eS vs a oes we LOCK is asserted. When executing more than one LOCK instruction, there must be six bytes of code between the end of the first LOCK instruction and the start of the second LOCK instruction. LOCK is ae Ee ee a eet a es toma 30, 51, 52 Bus cycle status 50-52 are encoded to provide bus-transaction information: Sois6 ber Gyaas Sahar tooo psi J Bus Cycle initiated a a A [oo wrt v0 a [ao Fea ata or nr [eo rata mony as a SE ‘The status pins float dunng “HOLD." _ 52 may be used as a logical M/IO indicator, and ST as a DT/R indicator. eee ere a une St nd a tun cyle bon HOLD (input) "HOLD indicates that another bus master is requesting the local bus, The HOLD input is active HIGH, HILDA (output) HOLD may be asynchronous with respect to the 80188 clock. The 80188 will issue a HLDA in response See ee ee cnet EDA the 60108 a toe Ha ea ee x nt a eine te etab ower HEDX What Pee eleanor oo ner fate Ungar Monon, Chip Sle! sh ache LOW cuss stoner = assay rotece a mede Wo he defined upper portion (1K-=256K block) of memory. This line is not floated during bus HOLD. The ‘address range activating UCS is software programmabie. ae oT vow Mornay Gp Sac ese LOW whanero a meray Trae & nade 0 he dood ower fee fae tno sn shied soy tn HOLD Th sous an Pe, hear sree ‘Active LOW WCSO-3 ‘Mid-Range Memory Chip Select signals are active LOW when a memory reference is made to the detined mid-range portion of memory (8K-512K). These lines are not floated during bus HOLD. The Se en Oem ogame ‘Active LOW PCSO Peripheral Chip Select signals 0-4 are active LOW when a reference is made to the defined peripheral Fe Fee oh Sea thaeitewenatastng uae He asses ane eke Wr sokwats bragraneabe

Previously latched valve of At during a bus HOLD. Previously latched value of A2 during a bus HOLD. ing 8086, int specific registers for operand and address calculations. 8-bit registers. in Table 2. Figure 1. 80188 General Purpose Register Set

Figure 2. Status Word Format Table 2. Status Word Bit Function Instruction Set control transfer, high-level instructions, and processor control. Lo le| Carry Flag — Set on high-order bit carry ‘These categories are summarized in Figure 3. CF | or borrow; cleared otherwise. Slenred otherwise, modes are discussed later in this data sheet. causes auto increment. external data areas.

Figure 3. 80188 Instruction Set All mnemonics copyright Intel Corp.

Addressing Modes . Bo. A te (unpacked) representation of the decimal s 0-8. The 80188 provides eight catogoies of adsressing modes fo | F's a0. & eres packed) representation of two dect specify operands. Two addressing modes are provided for 1 BCD: . instructions that operate on register or immediate operands: mal ae (0-9). One digit is stored in each nibble (4-bits) of © Register Operand Mode: The operand is located in one of ° - or 1 | registers. © Floating Point: A signed 32-, 64-, or 80-bit real number the 8- or 16-bit general registers representation. (Floating point operands are supported ‘© Immediate Operand Mode: The operand is included in the using a numeric data processor configuration.) instruction. In general, individual data elements must fit within defined Six modes are provided to specify the location of an operand segment limits. Figure 6 graphically represents the data types _— in a memory segment. A memory operand address consists of ‘supported by the 80188. two 16-bit components: a segment base and an offset. The segment base is supplied by a 16-bit segment register either , ° implicity chosen by the addressing mode or explicitly chosen soueo (rr by a segment override prefix. The offset, also called the u effective address, is calculated by summing any combination SON aeTOOE of the following three address elements: , : © the displacement (an 8- or 16-bit immediate value con- ween [TT] tained in the instruction); = © the base (contents of either the BX or BP base registers): nr and west ay 0 ‘© the index (contents of either the SI or DI index registers) cd a oy Any carry out from the 16-bit addition is ignored. Eight-bit pomiiaes displacements are sign extended to 16-bit values, sicneo »_*? <2 a ot ot Combinations of these three address elements define the six = Coreen memory addressing modes, described below. ere ———— ® Direct Mode: The operand's offset is contained in the soneo "7 “Sya® “tye? Pa! ® instruction as an 8- or 16-bit displacement element | ‘© Register indirect Mode:The operand’ oftset is in one of the SON 8 ae ———— —_ registers Si, Di, BX, or BP. on e wt : © Based Mode: The operands offset is the sum of an 8- or vow [TTT 16-bit displacement and the contents of a base register (BX use or BP) —Swowre ‘© Indexed Mode: The operand's offset is the sum of an 8- or emany 77h 8 pane 16-bit displacement and the contents of an index register coven [TTT] ee FTP] (St or DD. (800) gear w oat) oo © ‘© Based Indexed Mode: The operand's offset is the sum of 7 tM 6 yt) o7 0 6 the contents of a base register and an index register. asea [TTT] oe. TTT] © Based Indexed Mode with Displacement: The operand's enpacTORe unten, Banucten, offset is the sum of a base register’s contents, an index 7 tN og 7 tt 97 O ® oe ‘ ace register's contents, and an 8- or 16-bit displacement. ‘BCD CT wee Cert) Data Types wor tast Sthanicawt ovr SOMPICANT OT The 80188 directly supports the following data types: . 1 ° rH rat! gre 0 © Integer: A signed binary numeric value contained in an 8-bit sme [TTT] PPTET OTT byte or a 16-bit word. All operations assume a two's ‘complement representation. Signed 32 and 64 bit integers evrewonon Remora yrewonoo are supported using a numeric data processor. rt “r 4 roses PTT) © Ordinal: An unsigned binary numeric value contained in an _ B-bit byte or a 16-bit word. \\—sacton —— arr nee tbo? s6 48 ca 43 42 41 OG © Pointer: A 16- or 32-bit quantity, composed of a 16-bit offset FLOATING CLILIITIIriCitl) component or a 16-bit segment base component in addition eel, to a 16-bit offset component. a _ © String: A contiguous sequence of bytes or words. A string F002040 may contain from 1K to 64K bytes. NOTE: "SUPPORTED BY 60188 WITH A NUMERIC DATA @ ASCII: A byte representation of alphanumeric and control PROCESSOR characters using the ASCII standard of character represen- tation. Figure 6. 80188 Supported Data Types

1/0 Space Table 4. 80188 Interrupt Vectors The 1/0 space consists of 64K 8-bit or 32K 16-bit ports. | nterupt name | ata] Baia 1 Related ‘Separate instructions address the 1/O space with either an 8- Type instructions bit port address, specified in the instruction, or a 16-bit port Divide Error oO ial DIV, IDIV address in the DX register, B-bit port addresses are zero Exception extended such that Ay5-Ag are LOW. I/O port addresses —_| Single Step 1 | 122 | al 00F8(H) through OOFF(H) are reserved. Interrupt NMI 2 1 All Breakpoint 3 1 INT Interrupts eet

7 INTO Detected 4 a INTO

An interrupt transfers execution to a new program location. Overflow The old program address (CS:P) and machine state (Status Exception Word) are saved on the stack to allow resumption of the Array Bounds 5 4 BOUND interrupted program. Interrupts fall into three classes: hard- Exception ware initiated, INT instructions, and instruction exceptions. Unused-Opcode 6 4 Undefined Hardware initiated interrupts occur in response to an external Exception Opcodes input and are classified as non-maskable or maskable. ESC Opcode 7 | tt | ESC Opcodes Exception Programs may cause an interrupt with an INT instruction. Timer © Interrupt 8 atte Instruction exceptions occur when an unusual condition, which | Timer 1. Interrupt 18 | apr Prevents further instruction processing, is detected while Timer 2 Interrupt 19 2cerr* attempting to execute an instruction. If the exception was Reserved 9 3 caused by executing an ESC instruction with the ESC trap bit DMA 0 Interrupt 10 4 set in the relocation register, the return instruction will point to DMA 1 Interrupt "4 5 the ESC instruction, or to the segment override prefix immedi- INTO Interrupt 12 6 ately preceding the ESC instruction if the prefix was present. INTI Interrupt 13 7 In ail other cases, the return address from an exception will INT2 Interrupt 14 8 point at the instruction immediately following the instruction INT3 Interrupt 15 9 causing the exception. A table containing up to 256 pointers defines the proper Notes, interrupt service routine for each interrupt. Interrupts 0-31, aa A some of which are used for instruction exceptions, are 7. These are generated as the result of an instruction reserved. Table 4 shows the 80188 predefined types and os default priority levels. For each interrupt, an B-bit vector must... Fn eee ee eee ee ance of request to be supplied to the 80188 which identifies the appropriate table . ‘the interrupt controller. The Timer interrupts all have entry. Exceptions supply the interrupt vector intemally. In the same detault priority level wth re toa omer addition, internal peripherals and noncascaded external inter- inte sources. fever, they have a defined rupts will generate their own vectors through the internal ‘errupt to interrupt controller. INT instructions contain or imply the vector Hard cee aoe) nah tier internany hes s and allow access to all 256 interrupts. Maskable hardware eerste voctor ‘ype number initiated interrupts supply the 8-bit vector to the CPU during an 4 Detauit tories ter the interrupt sources are used interrupt acknowledge bus sequence. Non-maskable hard- - P only if the user does not program each source into a ware interrupts use a predefined intemally supplied vector. unique priority level ***5. An escape opcode will cause a trap only if the proper Interrupt Sources bit is set in the peripheral contro! block relocation register. The 80188 can service interrupts generated by software or hardware. The software interrupts are generated by specific instructions (INT, ESC, unused OP, etc.) or the results of conditions specified by instructions (array bounds check, INTO, DIV, IDIV, etc.) All interrupt sources are serviced by an SINGLE-STEP INTERRUPT (TYPE 1) indirect call through an element of a vector table. This vector - - table is indexed by using the interrupt vector type (Table 4), Generated after most instructions if the TF flag is set. multiplied by four. All hardware-generated interrupts are sam- _ Interrupts will not be generated after prefix instructions (e.9., pled at the end of each instruction. Thus, the software REP), instructions which modify segment registers (e.9., POP interrupts will begin service first. Once the service routine is OS), or the WAIT instruction. entered and interupts are enabled, any hardware source of sufficient priority can interrupt the service routine in progress. NON-MASKABLE INTERRUPT-NMI (TYPE 2) The software generated 80188 interrupts are described below. An external interrupt source which cannot be masked. DIVIDE ERROR EXCEPTION (TYPE 0) BREAKPOINT INTERRUPT (TYPE 3) A oni version of the INT instruction. It uses 12 as an expressed in the number of bits in the destination. ype 8 interiax).

INTO DETECTED OVERFLOW EXCEPTION inactive and an internal processing interval elapses, the 80168, (TYPE 4) begins execution with the instruction at physical location FFFFO(H). RES al Hi Generated during an INTO instruction if the OF bit is set as Fo. intabes. ts some registers to predefined values ARRAY BOUNDS EXCEPTION (TYPE 5) Generated during a BOUND instruction if the array index is Table 5, 80188 Initial Register State after RESE outside the array bounds. The array bounds are located in (“Status Word SS~*«d Foo2H) memory at a location indicated by one of the instruction ‘operands. The other operand indicates the value of the index (0000(H) 1 bo checked FFF — UNUSED OPCODE EXCEPTION (TYPE 6) Data Segment (0000(H) Generated if execution is attempted on undefined opcodes. 000(H) ESCAPE OPCODE EXCEPTION (TYPE 7) 000%) Generated if execution is attempted of ESC opcodes (D8H- Relocation Register 20FF(H) DFH). This exception will only be generated if a bit in the ‘UMCS FFFB(H) relocation register is set. The return address of this exception will point to the ESC instruction causing the exception. If a segment override prefix preceded the ESC instruction, the THE 80188 COMPARED TO THE 80186 return address will point to the segment override prefix. The 80188 CPU is an &-bit processor designed around the Hardware-generated interrupts are divided into two groups: 80786 internal structure. Most internal functions of the 80188 maskable interupts and nor-maskable interrupts. The 80188 -_@€ identical to the equivalent 80186 functions. The 80166 provides maskable hardware interrupt request pins INTO- _handles the external bus the same way the 80186 does with INT3. in addition, maskable interrupts may be generates by ‘the distinction of handling only 8 bits at a time. Sixteen bit the 80188 integrated DMA controller and the integrated timer OPerands are fetched or writen in two consecutive bus cycles. unit. The vector types for these interrupts is shown in Table 4. Both processors will appear identical to the software engineer, Software enables these inputs by setting the interrupt flag bit With the exception of execution time. The intemal register (IF) in the Status Word. The interrupt controller is discussed in _stfucture ts identical and all instructions have the same end the peripheral section of this data sheet result. The differences between the 80188 and 80186 are outlined below. internally, there are three differences between Further maskable interrupts are disabled while servicing an the 60188 and the 80186. All changes are related to the 8-bit interrupt because the IF bit is reset as part of the response to bus interface. fa an interrupt or exception. The saved Status Word will reflect _ the enable status of the processor prior to the interrupt. The © The queue length is 4 bytes in the 80188, whereas the interrupt flag will remain zero unless specifically set. The 80186 queue contains 6 bytes, or three words. The queue interrupt return instruction restores the Status Word, thereby was shortened to prevent overuse of the bus by the BIU restoring the original status of IF bit. If the interrupt return re- when prefetching instructions. This was required because enables interrupts, and another interrupt is pending, the 80188 of the additional time necessary to fetch instructions 8 bits will immediately service the highest-priority interrupt pending, at a time. i.e., no instructions of the main line program will be executed. To further optimize the queue, the prefetching algorithm was changed. The 80188 BIU will fetch a new instruction to Non-Maskable Interrupt Request (NMI) load into the queue each time there is a 1-byte hole (space Anon-maskable interrupt (NMI) is also provided, This interrupt available) in the queue. The 80186 waits until a 2-byte is serviced regardless of the state of the IF bit. A typical use of space is available. NMI would be to activate a power failure routine. The a activation of this input causes an interrupt with an internally © he vernal sxscution lime of he struction is affected Py supplied vector value of 2. No external interrupt acknowledge take on ade to ercnes sales The CPU may sequence is performed. The IF bit is cleared at the beginning Se ee re ad ot etachon tetenes when of an NMI interrupt to prevent maskable interrupts from being also be limited by the speed of instruction fetches when a serviced. series of simple operations occurs. When the more sophis- ticated instructions of the 80188 are being used, the queue Single-Step Interrupt has time to fill and the execution proceeds as fast as the execution unit will allow. The 80188 has an internal interrupt that allows programs to execute one instruction at a time. It is called the single-step The 80188 and 60186 are completely software compatible by interrupt and is controlled by the single-step flag bit (TF) in the virtue of their identical execution units. Software that is system Status Word. Once this bit is set, an internal single-step _dPendent may not be completely transferable, but software ~~ interrupt will occur after the next instruction has been execut- that is not system dependent will operate equally well on an ed. The interrupt clears the TF bit and uses an internally 80188 or an 80186 supplied vector of 1. The IRET instruction is used to set the TF The hardware interface of the 80188 contains the major bit and transfer controf to the next instruction to be single- differences between the two CPUs. The pin assignments are stepped. nearly identical, however, with the following functional changes. Initialization and Processor Reset © A8-A15—These pins are only address outputs on the Processor initialization or startup is accomplished by driving en val taste 9 nes oe ee the RES input pin LOW. RES forces the 80188 to terminate all the BOCS upper eddross lines. ‘execution and local bus activity. No instruction or bus activity will occur as long as RES is active. After RES becomes © HE has no meaning on the 80188 and has been eliminated.

80188 CLOCK GENERATOR In addition, the 80188, as part of the integrated chip-select

internal and external clock generation. The clock generator Ready Logic description. oscialltoris used, it can be connected directly to input pin X1 in delayed Up to two and one-half clocks behind FES. ae Ins setup time before the falling edge of the 80188 clock input. Ari Ie 8 Mn lores) buffers and to direct the flow of data on and off the local bus. Figure 7. Recommended 80188 Crystal Memory/Peripheral Control 9 ‘The 80188 provides ALE, RD, and WR bus control signals. CLKOUT pin provides the processor clock signal for use OF use only the integrated chip-select circuitry. Tg and again in the middle of each Tw until ARDY is sampled tion of these signals is shown in Table 6. proper operation of the circuit, Sor during a operator.

Local Bus Arbitration ’be read or written by the 80186 CPU at any time. The location of any register contained within the 256-byte control block is The 80188 uses a HOLD/HLDA system of local bus ex- —_getermined by thi of th 1 change. This provides an asynchronous bus exchange mecha- ined by the current base address of the control Block ism. This means multiple masters utilizing the same bus can _The control block base address is programmed via a 16-bit operate at separate clock frequencies. The 80188 provides a___relocation register contained within the control block at offset single HOLD/HLDA pari through which all other bus masters EH from the base address of the control block (see Figure 8) may gain cotnrol of the local bus. This requires external It provides the upper 12 bits of the base address of the control circuitry to arbitrate whcih external device will gain control of block. Note that mapping the control register block into an the bus from the 60188 when there is more than one alternate address range corresponding to a chip-select range is not local bus master. When the 80188 relinquishes control of the recommended (the chip select circuitry is discussed later in local bus, it floats DEN, AD, WR, S0-S2, LOCK, ADO-AD7, A8- _this date sheet). In addition, bit 12 of this register determines —_ A19, 57 and DT/R to allow another master to drive these lines whether the control block will be mapped into 1/0 or memory directiy space. If this bit is 1, the contro! block will be located in , whereas if , the | block will be The 80188 HOLD latency time, ie., the time between HOLD Iocated in 70. eee ne oe cgeice block Stopes Hessel ‘noo acknowledge, Is 3 en ey the activity into VO space, the upper 4 bits of the base address must be focesso q med ince 1/0 addr ly 16 bit Geived. A HOLD request isthe highost priority activity request oBrammed as 0 (since O addresses are only 16 bits wide) which the processor may receive: higher than instruction _In addition to providing relocation information for the control fetching or internal DMA cycles. However, if a DMA cycle is in block, the relocation register contains bits which place the progress, the 80188 will complete the transfer before relin- _interrupt controller into AMX mode, and cause the CPU to quishing the bus. This implies that if a HOLD request is interrupt upon encountering ESC instructions. At RESET, the received just as a DMA transfer begins, the HOLD latency time. relocation register is set to 20FFH. This causes the control can be as great as 4 bus cycles. This will occur if a DMA word block to start at FFOOH in I/O space. An offset map of the 256- ‘transfer operation is taking place from an odd address to an byte control register block is shown in Figure 9. ‘odd address. This is a total of 16 clocks or more, if WAIT The int ‘i lograted 80188 peripherals operate semiautonomously baesnesaeiie ioe anuineaaaiat rina transfers are pet from the CPU. Access to them for the most partis via software mee } he HOLD latency me will be increased by the length read/write of the control and data locations in the control ‘of the locked transfer. block. Most of these registers can be both read and written. A tL few dedicated lines, such as interrupts and DMA request al Bus Controller and Reset provide real-time communication between the CPU and pe- Upon receipt of a RESET pulse from the RES input, the local ripherals as in a more conventional system utilizing discrete bus controller will perform the following actions: peripheral blocks. The overall interaction and function of the © Drive DEN, RID, and WR HIGH for one clock cycle, then Peripheral blocks has not substantially changed. — float. CHIP-SELECT/READY GENERATION LOGIC NOTE: RE is also provided with an intemal pull-up de- vice to prevent the processor from inadvertently enter- The 80188 contains logic which provides programmable chip- ing Queue Status mode during reset select generation for both memories and peripherals. In . addition, it can be programmed to provide READY (or WAIT © Drive SO-S2 to the passive state (all HIGH) and then float. state) generation. It can also provide latched address bits At © Drive LOCK HIGH and then float and A2. The chip-select lines are active for all memory and I/O - cycles in their programmed areas, whether they be generated @ Tristate ADO-AD7, A8-A19, 57, DT/R by the CPU or by the integrated DMA unit © Drive ALE LOW (ALE is never floated) Me: Chip Sele ‘© Drive HLDA LOW. mory Chip cts The 80188 provides 6 memory chip select outputs for 3 INTERNAL PERIPHERAL INTERFACE address areas: upper memory, lower memory, and midrange memory. One each is provided for upper memory and lower All the 80188 integrated peripherals are controlled via 16-bit registers contained within an internal 256-byte control block. TO". while four are provided for midrange memory This control block may be mapped into either memory or /O The range for each chip select is user-programmable and can space. Internal logic will recognize the address and respond to —_be set to 2K, 4K, BK, 16K, 32K, 64K, 128K (plus 1K and 256K the bus cycle. During bus cycles to internal registers, the bus _for upper and lower chip selects). In addition, the beginning or controller will signal the operation externally (.e., the RD, WR, base address of the midrange memory chip select may also be status, address, data, etc., lines will be driven as in a normal _selected. Only one chip select may be programmed to be bus cycle), but 'D7.9, SROY, and ARDY will be ignored. The —_active for any memory location at a time. All chip select sizes base address of the control block must be on an even 256- _are in bytes, whereas 80188 memory is arranged in words. _ byte boundary (i., the lower 8 bits of the base address are all__ ‘This means that if, for example, 16 64K x 1 memories are zeros). Ail of the defined registers within this control blockmay _used, the memory block size will be 128K, not 64K. 1140 13 2 0s BO UK UH orrser: FeH[ ET [RMX] _[M/I0] Relocation Address Bits R19-R8 ET =ESC Trap/No ESC Trap (1/0) M/lO = Register block located in Memory / 1/0 Space (1/0) RMX = Normal Interrupt Controller mode / IRMX compatible Interrupt Controller mode (0/1)

Figure 8. Relocation Register The 80188 provides a chip select for low memory called LCS. CAH starting at location 00000H. defined. Table 7 shows the relationship between the base become active until the LMCS register is accessed. Table 7. UMCS Programming Values TCS to be active. LMCS register bits R2-RO are used to 8 | memory | UMCS Value this chip-select register. FC000 16K FC3sH address and size of this memory block are programmable. Table 7. Any combination of bits 6-13 not shown in Table 7 will the fist range and MCS3 being active for the last range. larger upper memory area is desired. described in a later section.

‘weated as 16-bit registers located on even boundaries in 1/0 ble Base Address (PBA) of the peripheral chip-select block. Figure 14. PACS Register specify READY mode for PCSO-PCS3. bits is shown in Table 12. Table 10. PCS Address Ranges Table 12. READY Bits Programming PCso PBA = —PBA+ 127 0 | 0] 0 | 0 wait states, external RDY also used. 1| 0} 0 | 0 wait states, external RDY ignored. by the MPCS register (which is also used to set the size of the ignored. register is located at offset A8H in the internal control block. nored. 6 is used to select whether the peripheral chip selects are nored. the MPCS and the PACS registers are undefined, however READY, not in series if the external READY is used (R2 = 0). Table 11. MS, EX Programming Values wait states, not six. This is because the two wait states 0= Peripherals mapped into I/O space. cycles accessing internal peripherals. MPGS bits 0-2 are used to specify READY mode for PCS4- of MPCS set the PCS4-6 READY mode. states to be inserted for each peripheral or memory is * ‘AN Chip-select outputs will be driven HIGH. READY with the integrated ready generator. Ready consideration (i.e. UMCS resets to FFFBH).

Figure 17. DMA Control Register gardless of the state of the bit. @ the mode of synchronization; 01 Source synchronization. @ whether bytes or words will be transferred; 10 Destination synchronization. ‘© whether interrupts will be generated after the last transfer; 11 Unused. © whether the source pointer addresses memory or I/O transfer. ‘© whether the destination pointer will be incremented, dec- 2 (B/W) after each transfer. © whether the destination pointer will address memory or I/O (170). DMA Control Word Bit Descriptions 0 low priority. CHG/NOCHG: — Ghange/Do not change (1/0) ST/ 2. ‘STGP bit. if this bit is set when writing 1: Enable DMA requests from timer 2. when writing the control word, the pointer will remain constant after each cycle.

dresses, since this will allow data to be accessed ina single when destination synchronization is performed, however. Data memory access. will not be fetched from the source address until the destina- tion device signatis that it is ready to receive it. When DMA Transfer Count Register destination synchronized transfers are requested, the OMA ; controller will relinquish control of the bus after every transfer. rc ova babe ie maintains 3 Ten ae OMA aie, If no other bus activity is initiated, another DMA cycle will ee eee eee ees itn the OMe Colac; Bedi after two processor clocks. This is done to allow the non est be Toba the DMA contol words oot destination device time to remove its request it another Bea heal ontrol word rowever, transfor is not desired. Since the DMA controller wil relinquish SotMiy will terminate when the transfer count regis the bus, the CPU can initiate a bus cycle. As a result, a reaches zero. complete bus cycle will often be inserted between destination — synchronized transfers. These lead to the maximum DMA DMA Requests transfer rates shown in Table 14, Data transfers may be either source or destination synchro- nized, that is either the source of the data or the destination ot Table 14. Maximum DMA Transfer Rates the data may request the data transfer. In addition, DMA with 8 MHz 80188 transfers may be unsynchronized; that is, the transfer will take Type of place continually until the correct number of transfers has synchronization occurred. When source or unsynchronized transfers are per- Selected formed, the DMA channel may begin another transfer immedi- ately after the end of a previous DMA transfer. This allows Yeamnohroniged 1 Memosrees || Mpres/sec complete transfer to take place every 2 bus cycles or eight Detoaticn Synch | 0 tovmeainec | 17 Movicsiaec clock cycles (assuming no wait states). No prefetching occurs bytes: 75 Mbytes/ HIGHER REGISTER | XXX Xxx XXX A19-A16 ADDRESS LOWER REGISTER | A15-A12 | A11-AB | A7-A4 A3-A0 ‘ADDRESS 15 0 XXX = DON'T CARE ~ Figure 18. DMA Memory Pointer Register Format DMA Acknowledge DRO. ust also have been generated, Therefore, the source ination transfer pointers, and the transfer count register No explicit DMA acknowledge pulse is provided. Since both Gf isec) must be programmed before ths bit is set. source and destination pointers are maintained, a read from a requesting source, or a write to a requesting destination, Each DMA register may be modified while the channel is should be used as the DMA acknowledge signal. Since the operating. I the CHG/NOCHG bit is cleared when the control chip-select lines can be programmed to be active for a given _register is written, the ST/STOP bit of the control register will block of memory or 1/0 space, and the DMA pointers can be —_not be modified by the write. If multiple channel registers are programmed to point to the same given block, a chip-solect modified, itis recommended that a LOCKED string transfer be line could be used to indicate a OMA acknowledge. used to prevent a DMA transfer from occurring between SMA Priority updates to the channel registers. rior The DMA channels may be programmed such that one DMA Channels and Reset channelio aways ven Frome cycog or ne mee Upon RESET, the DMA channels will perform the following programmed such as to wl ‘ions: requests pending. DMA cycles always have priority over SO" internal CPU cycles except between locked memory accesses @ The Start/Stop bit for each channel will be rest to STOP. or word accesses the odd memory locations; however, an external bus hold takes priority over an internal DMA cycle. © Any transfer in progress is aborted. Because an interrupt request cannot suspend a DMA opera- _ tion and the CPU cannot access memory during a DMA cycle, TIMERS interrupt latency time will sutter during sequences of continu- ous DMA cycles. An NMI request, however, will cause all re, e188 Prowdes three internal 16-bit programmabio imers internal DMA activity to halt. This allows the CPU to quickly 88 Figure 18). Two of these are highly flexible and are qui connected to four external pins (2 per timer). They can be respond to the NM request. used to count external events, time external events, generate nonrepetitive waveforms, etc. The third timer is not connected DMA Programming to any external pins, and is usetut for real-time coding and time DMA cycles will occur whenever the ST/STOP bit of the Control. _delay applications. In addition, this third timer can be used as a Register is set, It synchronized transfers are programmed, a _prescaler to the other two, or as a DMA request source.

ALT: INH: ‘The ALT bit determines which of two MAX COUNT registers is The inhibit bit allows for selective updating of the enable (EN) used for count comparison. If ALT = 0, register A for that timer bit, If INH is a one during the write to the mode/control word, is always used, while if ALT = 1, the comparison will alternate _then the state of the EN bit will be modified by the write. If INH between register A and register B when each maximum count is a zero during the write, the EN bit will be unaffected by the is reached. This alternation allows the user to change one ‘operation. This bit is not stored; it will always be a 0 on a read. MAX COUNT register while the other is being used, and thus . provides a method of generating nonrepetitive waveforms. INT: Square waves and pulse outputs of any duty cycle are a When set, the INT bit enables interrupts from the timer, which ‘subset of available signals obtained by not changing the final will be generated on every terminal count. If the timer is count registers. The ALT bit also determines the function of configured in dual MAX COUNT register mode, an interrupt will _ the timer output pin. If ALT is zero, the output pin will go LOW —_be generated each time the value in MAX COUNT register A is for one clock, the clock after the maximum count is reached, If reached, and each time the value in MAX COUNT register B is ALT is one, the output pin will reflect the current MAX COUNT —_ reached. If this enable bit is cleared after the interrupt request register being used (0/1 for B/A). has been generated, but before a pending interrupt is ser- CONT: viced, the interrupt request will sil be in force. (The request is latched in the Interrupt Controller.) Setting the CONT bit causes the associated timer to run continuously, while resetting it causes the timer to halt upon MC: maximum count. If CONT = 0 and ALT = 1, the timer will count The Maximum Count bit is set whenever the timer reaches its to the MAX COUNT register A value, reset, count to the final maximum count value. If the timer is configured in dual register B value, reset, and halt. MAX COUNT register mode, this bit will be set each time the EXT: value in MAX COUNT register A is reached, and each time the value in MAX COUNT register B is reached. This bit is set The external bit selects between internat and external clocking regardless of the timers interrupt-enable bit. The MC bit gives for the timer. The external signal may be asynchronous with the user the ability to monitor timer status through software respect to the 80188 clock. If this bit is set, the timer will count instead of through interrupts. LOW-to-HIGH transitions on the input pin. If cleared, it will count an internal clock while using the input pin for control. in RIU: this mode, the function of the external pin is defined by the The Register In Use bit indicates which MAX COUNT register ATG bit. The maximum input to output transition latency time ig currently being used for comparison to the timer count may be as much as 6 clocks. However, clock inputs may be value, A zero value indicates register A. The RIU bit cannot be pipelined as closely together as every four clocks without written, ie., its value is not affected when the control register _ losing clock pulses. is written. It is always cleared when the ALT bit is zero. P: Not all mode bits are provided for timer 2. Certain bits The prescaler bit is ignored unless internal clocking has been are hardwired as indicated below: selected (EXT = 0). If the P bit is a zero, the timer will count at one-fourth the internal CPU clock rate. If the P bit is a one, the ALT =0, EXT =0, P=0, RTG=0, RIU=O output of timer 2 will be used as a clock for the timer. Note that the user must initialize and start imer 2 to obtain the prescaled Count Registers clock Each of the three timers has a 16-bit count register. The RTG: current contents of this register may be read or written by the processor at any time. if the register is written into while the Retrigger bit is only active for internal clocking (EXT = 0). In timer is counting, the new vaiue will take effect in the current this case it determines the control function provided by the count cycle. input pin. It ATG = 0, the input level gates the internal clock on and of Max Count Registers if the input pin is HIGH, the timer will count; if the input pin is Timers 0 and 1 have two MAX COUNT registers, whille timer 2 LOW, the timer will hold its value. As indicated previously, the has a single MAX COUNT register. These contain the number input signal may be asynchronous with respect to the 80188 of ‘events the timer will count. In timers 0 and 1, the MAX clock. COUNT register used can alternate between the two max When RTG = 1, the input pin detects LOW-lo-HIGH transi count values whenever the current maximum count is tions. The first such transition starts the timer running, clearing feached. The condition which causes a timer to reset is the timer value to zero on the first clock, and then increment- equivalent between the current count value and the max count ing thereafter. Further transitions on the input pin will again being used. This means that if the count is changed to be _ reset the timer to zero, from which it will start counting up above the max count value, or if the max count value is ‘again. It CONT = 0, when the timer has reached maximum changed to be below the current value, the timer will not reset count, the EN bit will be cleared, inhibiting further timer activity. to zero, but rather will count to its maximum value, "wrap EN: around” to zero, then count until the max count is reached. The enable bit provides programmer control over the timers Timers and Reset RUN/HALT status. When set, the timer is enabled to incre- Upon RESET, the Timers will perform the following actions: ‘ment subject to the input pin constraints in the internal clock mode (disc previously). When cleared, the timer will bo @ All EN (Enable) bits are reset preventing timer counting. inhibited from counting. All input pin transitions during the time © All SEL (Select) bits are reset to zero. This selects MAX EN is zero will be ignored. !f CONT is zero, the EN bit is COUNT register A, resulting in the Timer Out pins going automatically cleared upon maximum count. HIGH upon RESET.

INTERRUPT CONTROLLER four external interrupt pins. The interrupt controller is set into one of these three modes by programming the correct bits in The 80186 can receive interrupts from a number of Sources, the INTO and INT1 control registers. The modes of interrupt both internal and external, The internal interrupt controller controller operation are as follows: serves to merge these requests on a priority basis, for individual service by the CPU. Internal interrupt sources Fully Nested Mode (Timers and DMA channels) can be disabled by their own control registers or by mask bits within the interrupt controller. When in the fully nested mode four pins are used as direct The 80188 interupt controler has #s own contol registers nterut requests, The vectors for these four lnputs. are that set the mode of operation for the controler. interrupt source. If a lower-priority device requests an interrupt ‘The interrupt controller will resolve priority among requests while the in-service bit (IS) is set, no interrupt will be generated that are pending simultaneously. Nesting is provided so by the interrupt controller. In addition, if another interrupt interrupt service routines for lower prionty interrupts may request occurs from the same interrupt source while the themselves be interrupted by higher priority interrupts, A block inservice bit is set, no interrupt will be generated by the diagram of the interrupt controller is shown in Figure 21 interrupt controller, This allows interrupt service routines to The interrupt controller has a special iRMX 86 compatibilt operate with intenupts enabled without being themselves ree eeetoae the ce ol the BOT8B within the TMX go _inlerrupted by lower-prioiy interrupts. Since interrupts are ‘operating system interrupt structure. The controller is set in ©nabled, higher-priority interrupts will be serviced. this mode by setting bit 14 in the peripheral control block = hen a service routine is completed, the proper IS bit must be relocation register (see iRMX 86 Compatibility Mode section). reset by writing the proper pattern to the EOI register. This is In this mode, the internal 80188 interrupt controller functions required to allow subsequent interrupts from this interrupt as a “slave” controller to an external "master" controller. source and to allow servicing of lower-priority interrupts. An Special initialization software must be included to property set —_ EO] command is issued at the end of the service routine just up the 80188 interrupt controller in RMX 86 mode. before the issuance of the return from interrupt instruction. If F the fully nested structure has been upheld, the next highest- MASTER (NON-iRMX) MODE OPERATION priority source with its IS bit set is then serviced. Interrupt Controller External Interface Cascade Mode For external interrupt sources, five dedicated pins are provid- The 80188 has four interrupt pins and two of them have dual ed. One of these pins is dedicated to NMI, non-maskable functions. In the fully nested mode the four pins are used as interrupt. This is typically used for power-fail interrupts, etc. _girect interrupt inputs and the corresponding vectors are The other four pins may function either as four interrupt input generated internally. In the cascade mode, the four pins are lines with internally generated interrupt vectors, as an interrupt. Configured into interrupt input-dedicated acknowledge signal line and an interrupt acknowledge line (called the “cascade ——_ pairs. The interconnection is shown in Figure 22. INTO is an mode") along with two other input lines with internally generat- interrupt input interfaced to an 8259A, while INT2/INTAO ed interrupt vectors, or as two interrupt input lines and two serves as the dedicated interrupt acknowledge signal to that dedicated interrupt acknowledge ouput lines. When the inter- peripheral. The same is true for INT1 and INT3/INTAT. Each rupt lines are configured in cascade mode, the 80188 interrupt pair can selectively be placed in the cascade or non-cascade controller will not generate internal interrupt vectors. mode by programming the proper value into INTO and INT1 External sources in the cascade mode use externally generat- control registers. The use of the dedicated acknowledge ed interrupt vectors. When an interrupt is acknowledged, two. signals eliminates the need for the use of external logic to INTA cycles are initiated and the vector is read into the 80188 generate INTA and device select signals. ‘on the second cycle. The capability to interface to external lity to serve up t 8259A programmable interupt controllers is thus provided yng Wnmrar arate ongeueimiayon te toe af external when the inputs are configured in cascade mode. master and slave 8259As. Three levels of priority are created, requiring priority resolution in the 80188 interrupt controller, interrupt Controller Modes of Operation the master 8259As, and the slave 6259As. If an external The basic modes of operation of the interrupt controller inion-_interrupt is serviced, one IS bit is set at each of these levels. iRMX mode are similar to the 8259A. The interrupt controller When the interrupt service routine is completed, up to three responds identically to internal interrupts in all three modes: _end-of-interrupt commands must be issued by the program- the difference is only in the interpretation of function of the mer.

Figure 21. Interrupt Controller Block Diagram will continue to be set, however, to inhibit interrupts from other __"&V8 Preprogrammed default priority levels (see Table 4). active and the next interrupt service routine is entered. set the indicated in-service bit. The 80188 provides a Poll progress.

Until the interrupt request is acknowledged by the 80188 CPU. of.interrupt command issued by the CPU. The 80188 Interrupt Controller will generate interrupt vectors channels. for the integrated DMA channels and the integrated Timers. In The state of the external interrupt input pins is also indicated. Interrupt Controller Registers register will be HIGH only after an inactive-to-active transition. contains 15 registers. All registers can both be read or written edges the requests. CPU when it receives interrupt requests from devices with a registers, and vice versa. Figure 22. Cascade Mode Interrupt Connection

Correct master-slave interface requires decoding of the slave Figure 35. The interrupt request bits are set when a request addresses (CASO-2). Slave 8259As do this internally. Be- arrives from an internal source, and are rest when the cause of pin limitations, the 80188 salve address will have to. processor acknowledges the request. be decoded externally. INTT is used as a slave-select input. Note that the slave vector address is transferred internally, but Mask Register the READY input must be supplied externally. This register contains a mask bit for each interrupt source. The INT2 is used as an acknowledge output, suitable to drive the format for this register is shown in Figure 35. If the bit in this INTA input of an 8259A. register corresponding to a particular interrupt source is set, any interrupts from that source will be masked. These mask Interrupt Nesting bits are exactly the same bits which are used in the individual iAMX 86 mode operation allows nesting of interrupt requests. control registers, i.e, changing the state of a mask bit in this When an interrupt is acknowledged, the priority logic masks off _-"@dister will also change the state of the mask bit in tho all priority levels except those with equal or higher priority, individual interrupt control register corresponding to the bit. Vector Generation in the RMX 86 MODE Control Registers Vector generation in iRMX mode is exactly like that of an These registers are the control words for all the internal 8259A slave. The interrupt controller generates an 8-bit vector _interrupt sources. The format of these registers is shown in which the CPU multiplies by four and uses as an address into a Figure 36. Each of the timers and both of the DMA channels vector table. The significant five bits of the vector are user- have their own Control Register. programmable while the lower three bits are generated by the . Priory logic. These bits represent the encoding of th prorty The bits of the Control Registers are encoded as follows: level requesting service. The significant five bits of the vector pr, 3.bit encoded field indicating a priority level for the are programmed by writing to the Interrupt Vector register at source; note that each source must be programmed offset 20H. at specified levels. Specific End-of-Interrupt msk: mask bit for the priority level indicated by pry bits. In RMX mode the specific EO! command operates to reset an in-service bit of a specific priority. The user supplies a 3-bit priority-level value that points to an in-service bit to be reset. The command is executed by writing the correct value in the OFFSET Specific EOI register at offset 22H. LEVEL 5 CONTROL REGISTER (TIMER 2) SAH Interrupt Controller Registers in the iRMX

86 Mode LEVEL 4 CONTROL REGISTER | 45),

(TIMER 1) All control and command registers are located inside the TROL REGIST internal peripheral control block. Figure 33 shows the offsets LEVEL 8 oma ty EGISTER 36H of these registers. LEVEL 2 CONTROL REGISTER | 44, End-of-Interrupt Register {OMA 0) ‘The end-of-interrupt register is a command register which can LEVEL 0 CONTROL REGISTER | 4.) ‘only be written. The format of this register is shown in Figure (TIMER 0) 34. It initiates an EO! command when written by the 80188 cpu INTERRUPT-REQUEST REGISTER | 25H The bits in the EOI register are encoded as follows: INSERVICE REGISTER 2CH Le Encoded value indicating the priority of the IS bit to be reset. PRIORITY-LEVEL MASK REGISTER | 24H In-Service Register This register can be read from or written into. It contains the in- MASK REGISTER 28H service bit for each of the internal sources. The format for this register is shown in Figure 35. Bit positions 2 and 3 corre- SPECIFIC EOI Ri 4 spond to the DMA channels; positions 0, 4, and 5 correspond ‘01 REGISTER 22) to the integral timers. The source's IS bit is set when the processor acknowledges its interrupt request. INTERRUPT VECTOR REGISTER | 20H Interrupt Request Register This register indicates which internal peripherals have interrupt Figure 33. Interrupt Controller Registers requests pending. The format of this register is shown in (iRMX 86 Mode)

Figure 39. Typical 80188 Computer

Figure 40. Typical 80188 Multi-Master Bus Interface

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature cevessesssnens “65°C 10 +150°C Commercial (C) Devices Industrial (I) Devices Stresses above those listed under ABSOLUTE MAXIMUM = OVEN) Devices RATINGS may cause permanent device failure. Functionality Supply Voltage (VOC) ooeessveseseernerrneeesS V 5% at or above these limits is not implied. Exposure to absolute . maximum ratings for extended periods may affect device Operating ranges define those limits between which the reliability. functionality of the device is guaranteed. DC CHARACTERISTICS (over operating range unless otherwise specified) [Parameters | Dessrpnon [Yost Ganatons [wns — wan [ons] [vu Finer Low Vonage 0s 08 von) Input HIGH Voltage . 7 [wi tnout WiGH Vonage (RES) PT Voc #05] vots TA= 28 mA for SO-8E | va [ewerowvonee TRIES ARE Share wee || one | ae | | Vos [Output HIGH Votage [ton ==400 pa vats [tanner ooo ‘ec Powor Supply Current [tanore 00m [tasroro [ius rput Leakage Curent Yo VV veg sto | ho [Output Leakage Curent [045 VeVour<Voo Tete | vaio Geek Output tow TT igeao mao vos |__vowo | Giock Output HGH ions =200 wk go vots Clock input LOW Voitage po os os vos) [Vou | Gock tnput HIGH Voltage [8 vec 10] vos | [Cw trput Capacitance [Go| 0 Capactanes no ar SWITCHING CHARACTERISTICS PIN TIMING 80188 Timing Requirements All Timings Measured At 1.5 Volts Unless Otherwise Noted so18e-10 (10 mia)] 90188 (8 MHz) | [_ Parameters | Description Test Conditions | win. | Max._| min. | max. units | Data in Setup (A/D) [Ts ) | Touox | Data in Hole (AO) to es Peo lieereee es [st Pt te (AREADY) actwe setup time [ Tarwuc __['AREADY inactive setup time [ass [Tonarvx [AREADY heed te [as a [ones Pare erm [a time a (GREADY) transiton setup time [Tosay | SREADY wansiton oid tne Ys se | tavor [HOLD Setup” eos | Tinwow [NTR NM, TEST, TMERIN, Setup” [a as as [Tnwven —[0RO0, ORGE Soup” os fs] “Te guarantee recognition al next clock, For Industral Grade Parts only

SWITCHING CHARACTERISTICS (Cont'd.)

80188 Master Interface Timing Responses

Test Conations | win. [wax | in| max | [Tov [Adsress Vaid Ooay «f= 20-200 atowputs [5 [a fs [ss [ns | [roux [Adesso | Tt Ts —~— Froxz_[Aderess oat Delay [Ct use| [Toncz {Command Lines Float Dewy [| | Tas os ca ak (after float) [Tome ALE wan reucnso Pf reuctas [as | [Town [ALE Acwebeay PC Ps Ts [Tout [ALE inactive Dewy] TT ns [Tux [Address Hold to ALE nace [Teo || once || ns [Toy [Oata vad dey | tw aes [Tapox _[Oaavodtime | tts [Twnox _[OataWodaterwa | Treg | cuca [| os [Tovery [Conk Actwo Delays | | a Ts os [Toner _[Gonwor Active Owe [Tt we Ts ns [Toverx _[onvot wactve Delay TT we ss | ac er (Non.Wrte Cycle) [Tam [Address Float to AD Acwe [TT ns [Tom [AD Active Owey | tT (Tou [AO inactive Dolay [| tT ve Pts os [Tanav |B inactive to adiross Acie | Teuctao [| ruc [| ns | [Toumav [MLDAVata Dewy | wo sf os ruse [RO wien arenas [Parcicuso fT os | [Tmwe [wRwam OTC areca [Parco {| os [Tava _[Addioss vaio wo alecow | Puce [| cucnas | |r| [Tousy _[Staws Actve Dowy | Os Tt ss | [Tosh [Status Inactve Dewy | Tc Ts fs [Tour [Timer Output Oey | Ope mee Tae Po | [Tono [Reset Duy | we we [Tonosy [Qveuo Stas Ooay | Cd a Ts | [Touox |StausHodtme | ts [Tavon [Address vaid to Goo GH [Pt fs [Teuxy [LOCK Validvinvaid Delay | CT Tw Ts ne

80188 Chip-Select Timing Responses

fermeeceaee [meee | | Teat conaitions | win. wax. | in| wax. | _ [Recsy _[GripSetect Active Dewy PCC CdS so es Chip-Select Hold from [reese lemme Tw TT Td [Toucsx _[ohipSeloct mactwe Delay TT Te Ps ns

SWITCHING CHARACTERISTICS (Cont'd.)

80188 CLKIN Requirements

80188-10(10 MHz) 80188 (8 MHz) Test Conditions | Min. | max. | win. | Max. | a A cm [tonue [KW Ase Tine te as vets [Wrote OK LOW Trp isa [ Tonck | CUKIN HIGH Time [aS vorts Tees Ts

80188 CLKOUT Timing (200 pF load)

[Parameters| Description |__Test Conditions| Min._ | Max. | Min. | Max. | Units | a A ek [Ttexcx——[axour tow Time we [tenor | -GlxoUT nigh Tine [15 wis rex | | tuts | |e | [Tonncse | GKOUT Ase Tme | tow sswis YP | [rexzcry —[eaxour Fate 950 1 vans |) pi SWITCHING TEST INPUT/OUTPUT WAVEFORM ts err AC testing inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic ''0."" The clock is driven at

Vou th te wh Ww ‘7 a reas / oxour Y y oe 3,88. P| | r — rel dat | = fries a a ic ea = — roams TX Tee eave { wa LY 1 AeA > nar VE => Toucry ToHCTY = f Ss 9.578. ~ Vow | | oe ¢ oe k K7 | Soran, Bees > a ie ay rar o

SWITCHING WAVEFORMS (Cont'd.) MAJOR CYCLE TIMING (Cont'd.) a t bt k ve rd} os romicne cxour Fam __ a Cet One oases Gen ~FPSe TCHLH TAVAL, a ron) pecat tT youn rove. —a Ta, tem TOT KT eT . eR yt JHtcHerv _ ova ATT = von m= roves aS ts, —re1ev | exes f= Ss wrooezes Notes: 1. Following a Write cycle, the Local Bus is floated by the 80188 only when the 80188 enters a ‘Hold Acknowledge"’ state. 2. INTA occurs one clock later in RMX-mode. 3. Status inactive just prior to Ts.

SWITCHING WAVEFORMS (Cont'd.) ne cuxouT —+| rev —+| rou OR WF006232 ‘cuxouT ~ oRa0, orar Twaven — Te. Mt, Test INTO-3 TIMERIN WFO06240 cuxout Tenasv 980, a81 WF006250

SWITCHING WAVEFORMS (Cont'd.) foo foe | foe | “en S\\N f | anvnen | roman | | ‘AROY } | amen sannie.—s| noe weoszte cxxout “| TCLSRY sror vwroosero HOLD-HLDA TIMING Te n euxout we, ve. vow | seus rou ‘HLDA - — | ‘TCLAY sorsase +. u _ cen 018s --- ZF 90188 a =F oA, i vm “e roosts

SWITCHING WAVEFORMS (Cont'd.) eKIN TeLeK. cu ~ OKA. rex onc rowscn — yeuzcis cuxout Teico. re.cn. rowel. * wro06233 TIMER ON 80188 men | Ten i | | Tourmy |= _ sna | wFo06200 80188 INSTRUCTION TIMINGS © All word-data is located on even-address boundaries. The following instruction timings represent the minimum All jumps and calls include the time required to fetch the execution time in clock cycles for each instruction. The timings opcode of the next instruction at the destination address. given are based on the following assumptions: All instructions which involve memory reference can require The opcode, along with any data or displacement required Gre (ang in some cases, two) additional clocks above the for execution of a particular instruction, has boon pre- Ve, (ene in meme, DE TN) eat tne. asynchronous fetched and resides in the queue at the time it is needed. nate of the handshake between the BIU and the Execution ‘© No wait states or bus HOLDS occur. unit a

Moray 6 aes ° fesse ener ‘ neve mer 1 sare pte 2 Sean wt tena am ust = Pues Mer " aeoer Seamer ase ° POP = Pop Memory ” Fogster * segment ogi veseon | ° Fegan wih rote “7 Rag wit cums a N= pat rome: Fa pot 0 vara pot ‘ OUT = Output to: Fred pot : Vaso pot , MLAT= Translate yo t AL " LEA Lond EA 1 ot ° 18 = Loud ponte to 05 wots | ” LES ~ Load pontr 1 ES meas» | ” Lave on A fags 2 SAF = Sto AH i tos a PUSH = Push flags ° pore =P tas ‘ Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors.

INSTRUCTION SET SUMMARY (Cont'd.) [amcnon FORMAT | Se [comme | TNE aoe feptoenay oth egtarw tea ono Immediate to regeter/miroy «ss (OOTOew| mevvoorm | aa [auiewso] | «ns ~ | ave aed wt carr fea!mencr psi oer one I tcremon nets ney ous $00 = tabeact Feymenoty and ester 1 ete ano inmate tom ogeix/menoy «(OOO DOew| mevtotmm | aw [wmnewnor] | «vo Inne tam exude an] arene am baboat th borow feglnaney and eg ster ano immediate tom ognv/mmoy «(ODO OOsw[ mevetivm | aa [davewsm] | «ve nc beeromont ~ | reo 2 Pepamener wes ono nade win gste/nonoy «LODO DOee]| merit | aa | watewno] | oo Imes wh acct on | arene wea = carn sen : AAA ASCH est fora 8 AA Decimal ads or add ‘ AAS = ASCi adust for subact 7 DAS = Decal ast for subtract ‘ Aegean 25-20 Memory-Byte 92-34 UL = eae may (set feoseese 2-28 acta Ron bay wey ye Be were B28 rea DIV = Divide (unsigned: Fuge ye » Retort 8 ie FA nes 2 ‘Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. All mnemonics copyright of Intel Corp, 1982

INSTRUCTION SET SUMMARY (Cont'd.) Clock FORMAT Cycles ARITHMETIC (Continued): Regaine Regeterors so-01 fomonyyie 52% AAAML= ASC ast fr ruil 8 80 = Convene 6 wor 2 WD = Convert word to dovbie wore 4 Loaic Shit/Rotate Instructions: RegsteMenor y \\pbcstiachiniiie shane 25 oS ea TE eR TOD See eee Oe dies ge eee ae 7 rawasten bes oR ote Bey ios ous An» ane: Immediate 10 reistr/memery (recooow] moatoovm [de [ awiw-t ] | ane Immediate to acount [covoorow] aa | diatw=t ae | sree TEST= And function to flags, o result: Regater/ memory and epitr avo Immediate date and regstovmonoy [TF T101tw] miooovm | aa [ watw=t] | «0 Immediate date and accumulator = [FOF OT00w] ata | deetwet | ae | ertee on =0r Regimen ad et ter ono Immediate to cei nemory [roccooow] mosooivm [dae | diatw=1] | aie XOR = Excunve or STRING MANIPULATION MOVS = Move byto/word aren (CMPS = Compare byt0/word 5 +200 SCAS = Scan byte/wors 5415 {LODS ~ Load byte/wd to AL/AX ee ttn STOS = Sior byto/wd from AL/A +n ‘Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. AW memories copyright of Intel Corp. 1982

INSTRUCTION SET SUMMARY (Cont'd.) ] Clock FUNCTION FORMAT Cycles ‘STRING MANIPULATION (Corin Fepeates by count in CX OWS = Mowe stone “ (CHP — Compare sng 2 SEAS = Sean srg s L008 = toas stn e Stos Store sung id | not Pepa CONTROL TRANSFER CALL = cat Dract win segment “ Regater meron rene noc wan Wont rac etersgment = [sear stor) Indes itaragmt twearin | * INP = Unconditional um. Srerviong ° Registr’memory mdnect witvn segment war ect rage » Inset itrsegrent iweein | = | | ner =setum from CALL: wie segment Troooer rf win 209 ada ied 10 SP * Irsegment 2 Intersegment acking inmeciate to SP aaiatigh 2% ‘Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. | At mnemonics copyright of Intl Cor. 1982

‘CONTROL TRANSFER (Continued): IELS2 = Jump on equal z0r0 ane | sone JLIINGE = ump on ess ot eater oF ea. ans | Se EINE =e os et get wa fee SBIMIE =r co ie ava JBEJJNA = hump on below or equal not above ans PPE = n pay pry er wa 8 me on sn wa .INE/INZ = Jump on not equal not 200 ans JNL/IGE = Jump on rot less rater or eaual ans JNLE/IG =e on 01 es ex! gator ana LINBIJAE = Jump on nol below above oF equa ans INBE/IA Jump on nt below or equal above ans LINP/JPO = Jump on net par! par odd ans JNO = Jump 00 not ovetiow ans {= np on nt sn wa 00° Lop 6x ees ons LOOPZ/LOOPE = Loop while 200 equa one LOOPNZ/LOOPNE = Loop whe not 20 eqUa! ene JOXZ = Jump 09 CX 2000 16 | JMP takers S| eats "ip specie a INTO Interust on overtiow a IRET = Irtervpt rower Ey ‘Shaded areas indicate new 80188 instructions not available in 8086 or 8088 microprocessors. ‘At mnemonics copyight of Intl Cop. 1082

INSTRUCTION SET SUMMARY (Cont'd.) Clock Cycles PROCESSOR CONTROL CLE = Ger cary (GMC = Compierent cary STC = Set cary — | ct clear aracton STO Set drocton Lr = Gioar itorupt S71 Sat iterugn HLT = Hatt WAIT ~ Won LOCK = Bus lock pret ESC ~ Processor Extension Escape (FFT LLL are opcode to processor extension) FOOTNOTES REG is assigned according to the following table: ‘The effective Address (EA) of the momory operand is 16-Bit (w= 1) 8-BIt (w= 0) computed according to the mod and ¢/m fields: (000 Ax (000 AL it mod = 11 then r/m is trgated as a REG field 001 GX 001 CL it mod = 00 then DISP = 0", disp-low and disp-high are 010 DX 010 DL absent O11 BX 011 BL if mod = 01 then DISP = disp-low signextended to 16-bits, 400 SP 100 AH disp-high is absent 401 BP 401 cH it mod-= 10 then DISP = disp-high: disp-low 110 St 110 OH —~__ | if r/m= 000 then EA = (BX) + (SI) + DISP 114 Ot 111 BH if r/m=001 then EA = (BX) + (D)) + DISP if r/m= 010 then EA = (BP) + (SI) + DISP if r/m= 011 then EA = (@P) + (0!) + DISP if r/m= 100 then EA = (SI) + DISP The physical addresses of all operands addressed by the BP if eém=101 then EA~(D)) + DISP | register are computed using the SS segment register. The if r/m= 110 then EA = (BP) + DISP physical addresses of the destination operands of the string if r/m= 111 then EA = (BX) + DISP primitive operations (those addressed bythe DI register) are DISP follows 2nd byte of instruction (before data if required) Gomputed using the ES segment, which may not be overrid- “excopt if mod = 00 and r/m= 110 then EA-= disp-high: disp-ow. SEGMENT OVERRIDE PREFIX r0g is assigned according to the following Segment reg Register oo ES o © cs 10 | SS 11 DS

—— 2 Ce +63 EST e¢ rom GE a

PHYSICAL DIMENSIONS (Cont'd.) cGxX068 BOTTOM VIEW (Pins facing up) ase Pane Hig seat Pane ors as ner i Rateconcn Cana fe" 9% ese os ABCOEFGHS KL 4 ed iftecoebsoooe 2] ©C© 000600000 Fe 3] @@ oe ee 2 ‘1°00 WY us ‘|e2 ZZ ee oat ‘ . 3 2] Ceoocegeooeg et 78 0900S css ||. me a if roswnce ~ =~ 29 *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering

PHYSICAL DIMENSIONS (Cont'd,) PL 068 dk ar ow qd bt =| Se q bh = d 5 Ltr ge q 3 #) ET s 4 ; Hh q p = q p = 4 =e *For reference only. All dimensions are measured in inches. BSC is an ANSI standard for Basic Space Centering.

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