AM27C4096 AMD | Alldatasheet
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Publication# 11408 Rev: F Amendment/ 0 Issue Date: May 1998 Am27C4096
4 Megabit (256 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS ■ Fast access time — Speed options as fast as 90 ns ■ Low power consumption — 100 µA maximum CMOS standby current ■ JEDEC-approved pinout — Plug-in upgrade of 1 Mbit and 2 Mbit EPROMs — 40-pin DIP/PDIP — 44-pin PLCC ■ Single +5 V power supply ■ ±10% power supply tolerance standard ■ 100% Flashrite programming — Typical programming time of 32 seconds ■ Latch-up protected to 100 mA from –1 V to V CC + 1 V ■ High noise immunity GENERAL DESCRIPTION The Am27C4096 is a 4 Mbit, ultraviolet erasable pro- grammable read-only memory. It is organized as 256 Kwords, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The Am27C4096 is ideal for use in 16-bit microprocessor systems. The device is avail- able in windowed ceramic DIP packages, and plastic one time programmable (OTP) PDIP and PLCC pack- ages. Data can be typically accessed in less than 90 ns, al- lowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus micro- processor system. AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 125 mW in active mode, and 125 µW in standby mode. All signals are TTL levels, including programming sig- nals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 µs pulses), re- sulting in a typical programming time of 32 seconds. BLOCK DIAGRAM 11408F-1 A0–A17 Address Inputs CE#/PGM# OE# VCC VSS VPP Data Outputs DQ0–DQ15 Output Buffers Y Gating 4,194,304 Bit Cell Matrix X Decoder Y Decoder Output Enable Chip Enable and Prog Logic
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Notes: 1. JEDEC nomenclature is in parenthesis. 2. Don’t use (DU) for PLCC. PIN DESIGNATIONS A0–A17 = Address Inputs CE# (E#)/ = Chip Enable Input/ PGM#/ (P#) Program Enable Input DQ0–DQ15 = Data Input/Outputs OE# (G#) = Output Enable Input VCC =V CC Supply Voltage VPP = Program Voltage Input VSS = Ground LOGIC SYMBOL Family Part Number Am27C4096 Speed Options VCC = 5.0 V ± 5% -95 -105 -255 VCC = 5.0 V ± 10% -100 -120 -150 -200 Max Access Time (ns) 90 100 120 150 200 250 CE# (E#) Access (ns) 90 100 120 150 200 250 OE# (G#) Access (ns) 50 50 50 65 75 75 V CC A17 A16 A15 A14 A13 A12 A11 A10 V SS V PP CE# (E#)/PGM# (P#) DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 V SS DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE# (G#) 11408F-2 1 4 44 34 2543264 1 4 0 A13 A12 A11 A10 V SS NC DQ13 DQ14 DQ15 CE# (E#)/PGM# (P#) V PP DU (Note 2) V CC A17 A16 A15 A14 DQ12 DQ11 DQ10 DQ9 DQ8 V SS NC DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 OE# (G#) DU (Note 2) 23 24 25 2619 20 21 2218 27 28 11408F-3 DQ0–DQ15 A0–A17 CE# (E#)/PGM# (P#) OE# (G#) 11408F-4
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM27C4096 -95 D C OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In TEMPERATURE RANGE C = Commercial (0°C to +70°C) I= Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE D = 40-Pin Ceramic DIP (CDV040) SPEED OPTION See Product Selector Guide and Valid Combinations B Valid Combinations AM27C4096-95 VCC = 5.0 V ± 5% DC, DCB AM27C4096-100 DC, DCB, DI, DIBAM27C4096-105 VCC = 5.0 V ± 5% AM27C4096-120 DC, DCB, DE, DEB, DI, DIBAM27C4096-150 AM27C4096-200 AM27C4096-255 VCC = 5.0 V ± 5% DC, DCB, DI, DIB DEVICE NUMBER/DESCRIPTION Am27C4096
4 Megabit (256 K x 16-Bit) CMOS UV EPROM
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AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DEVICE NUMBER/DESCRIPTION Am27C4096
4 Megabit (256 K x 16-Bit) CMOS OTP EPROM
Blank = Standard Processing TEMPERATURE RANGE C = Commercial (0°C to +70°C) I= Industrial (–40°C to +85°C) PACKAGE TYPE P = 40-Pin Plastic DIP (PD 040) J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED OPTION See Product Selector Guide and Valid Combinations Valid Combinations AM27C4096-105 VCC = 5.0 V ± 5% PC, JC AM27C4096-120 PC, PI, JC, JI AM27C4096-150 AM27C4096-200 AM27C4096-255 VCC = 5.0 V ± 5%
In order to clear all locations of their programmed con- tents, the device must be exposed to an ultraviolet light source. A dosage of 15 W seconds/cm 2 is required to completely erase the device. This dosage can be ob- tained by exposure to an ultraviolet lamp—wavelength of 2537 Å—with intensity of 12,000 µW/cm 2 for 15 to 20 minutes. The device should be directly under and about one inch from the source, and all filters should be re- moved from the UV light source prior to erasure. Note that all UV erasable devices will erase with light sources having wavelengths shorter than 4000 Å, such as fluorescent light and sunlight. Although the erasure process happens over a much longer time period, ex- posure to any light source should be prevented for maximum system reliability. Simply cover the package window with an opaque label or substance. Device Programming Upon delivery, or after each erasure, the device has all of its bits in the “ONE”, or HIGH state. “ZEROs” are loaded into the device through the programming pro- cedure. The device enters the programming mode when 12.75 V ± 0.25 V is applied to the V PP pin, and CE#/PGM# is at VIL and OE# is at VIH. For programming, the data to be programmed is ap- plied 16 bits in parallel to the data pins. The flowchart in the Programming section (Section 5, Figure 5-1) shows AMD’s Flashrite algorithm. The Flashrite algorithm reduces programming time by using a 100 µs programming pulse and by giving each address only as many pulses to reliably program the data. After each pulse is applied to a given address, the data in that address is verified. If the data does not verify, additional pulses are given until it verifies or the maximum pulses allowed is reached. This process is repeated while se- quencing through each address of the device. This part of the algorithm is done at V CC = 6.25 V to assure that each EPROM bit is programmed to a sufficiently high threshold voltage. After the final address is completed, the entire EPROM memory is verified at V CC = VPP = 5.25 V. Please refer to Section 5 for additional programming in- formation and specifications. Program Inhibit Programming different data to multiple devices in par- allel is easily accomplished. Except for CE#/PGM#, all like inputs of the devices may be common. A TTL low-level program pulse applied to one device’s CE#/ PGM# input with V PP = 12.75 V ± 0.25 V and OE# HIGH will program that particular device. A high-level CE#/PGM# input inhibits the other devices from being programmed. Program Verify A verification should be performed on the programmed bits to determine that they were correctly programmed. The verify should be performed with OE# at V IL, CE#/ PGM# at VIH, and VPP between 12.5 V and 13.0 V. Autoselect Mode The autoselect mode provides manufacturer and de- vice identification through identifier codes on DQ0– DQ7. This mode is primarily intended for programming equipment to automatically match a device to be pro- grammed with its corresponding programming algo- rithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when pro- gramming the device. To activate this mode, the programming equipment must force V H on address line A9. Two identifier bytes may then be sequenced from the device outputs by tog- gling address line A0 from V IL to VIH (that is, changing the address from 00h to 01h). All other address lines must be held at V IL during the autoselect mode. Byte 0 (A0 = VIL) represents the manufacturer code, and Byte 1 (A0 = VIH), the device identifier code. Both codes have odd parity, with DQ7 as the parity bit. Read Mode To obtain data at the device outputs, Chip Enable (CE#/ PGM#) and Output Enable (OE#) must be driven low. CE#/PGM# controls the power to the device and is typ- ically used to select the device. OE# enables the device to output data, independent of device selection. Ad- dresses must be stable for at least t ACC –tOE . Refer to the Switching Waveforms section for the timing dia- gram. Standby Mode The device enters the CMOS standby mode when CE#/PGM# is at V CC ± 0.3 V. Maximum VCC current is reduced to 100 µA. The device enters the TTL-standby mode when CE#/PGM# is at V IH. Maximum VCC cur- rent is reduced to 1.0 mA. When in either standby mode, the device places its outputs in a high-imped- ance state, independent of the OE# input. Output OR-Tieing To accommodate multiple memory connections, a two-line control function provides: ■ low memory power dissipation, and ■ assurance that output bus contention will not occur. CE#/PGM# should be decoded and used as the pri- mary device-selecting function, while OE# be made a
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common connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. System Applications During the switch between active and standby condi- tions, transient current peaks are produced on the ris- ing and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the out- put capacitance loading of the device. At a minimum, a 0.1 µF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between V CC and VSS to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM ar- rays, a 4.7 µF bulk electrolytic capacitor should be used between V CC and VSS for each eight devices. The loca- tion of the capacitor should be close to where the power supply is connected to the array. MODE SELECT TABLE Notes: 2. X = Either VIH or VIL. 3. A1–A8 and A10–17 = VIL. 4. See DC Programming Characteristics for VPP voltage during programming. Mode CE#/PGM# OE# A0 A9 V PP Outputs Read V IL VIL XX X D OUT Output Disable V IL VIH X X X High Z Standby (TTL) V IH X X X X High Z Standby (CMOS) V CC ± 0.3 V X X X X High Z Program V IL VIH XX V PP D IN Program Verify V IH VIL XX V PP D OUT Program Inhibit V IH XX XV PP High Z Autoselect (Note 3) Manufacturer Code V IL VIL VIL VH X 01h Device Code V IL VIL VIH VH X 19h
Voltage with Respect to VSS All pins except A9, VPP, VCC . . –0.6 V to VCC + 0.6 V Notes: 1. Minimum DC voltage on input or I/O pins –0.5 V. During voltage transitions, the input may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on A9 is –0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to –2.0 V for periods of up to 20 ns. A9 and VPP must not exceed+13.5 V at any time. Stresses above those listed under “Absolute Maximum Rat- ings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure of the device to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Industrial (I) Devices Extended (E) Devices Ambient Temperature (T Supply Read Voltages Operating ranges define those limits between which the func- tionality of the device is guaranteed.
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Caution: The device must not be removed from (or inserted into) a socket when VCC or VPP is applied.
- VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP..
- ICC1 is tested with OE# = VIH to simulate open outputs.
Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns. Figure 1. Typical Supply Current vs. Frequency Figure 2. Typical Supply Current vs. Temperature
Table 1. Test Specifications Figure 3. Test Setup Diodes are IN3064 or equivalents.
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Caution: Do not remove the device from (or insert it into) a socket or board that has VPP or VCC applied. Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. This parameter is sampled and not 100% tested. 3. Switching characteristics are over operating range, unless otherwise specified. 4. See Figure 3 and Table 1 for test specifications. SWITCHING WAVEFORMS Notes: 1. OE# may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC . 2. tDF is specified from OE# or CE#, whichever occurs first. PACKAGE CAPACITANCE Notes: 1. This parameter is only sampled and not 100% tested. 2. TA = +25°C, f = 1 MHz. Parameter Symbols Description Test Setup Am27C4096 UnitJEDEC Standard -95 -105 -120 -150 -200 -255 tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 90 100 120 150 200 250 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 90 100 120 150 200 250 ns tGLQV tOE Output Enable to Output Delay CE# = VIL M a x 5 05 05 06 57 57 5 n s tEHQZ tGHQZ tDF (Note 2) Chip Enable High or Output Enable High to Output High Z, Whichever Occurs First M a x 3 03 04 04 04 06 0 n s t AXQX tOH Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First M i n 000000 n s Addresses CE#/PGM# OE# Output 11408F-9 Addresses Valid High Z High Z tCE Valid Output 2.4 0.45 2.0 0.8 2.0 0.8 tACC (Note 1) tOE tDF (Note 2) tOH Parameter Symbol Parameter Description Test Conditions CDV040 PD 040 PL 044 UnitTyp Max Typ Max Typ Max C IN Input Capacitance V IN = 0 10 13 6 8 10 13 pF C OUT Output Capacitance VOUT = 0 10 13 8 10 12 14 pF
PHYSICAL DIMENSIONS* CDV040—40-Pin Ceramic Dual In-Line Package, UV Lens (measured in inches) * For reference only. BSC is an ANSI standard for Basic Space Centering. PD 040—40-Pin Plastic Dual In-Line Package (measured in inches) TOP VIEW SIDE VIEW END VIEW INDEX AND TERMINAL NO. 1 I.D. AREA .565 .605 2.035 2.080 .005 MIN .045 .065 .014 .026 .100 BSC .015 .060 .160 .220 .125 .200 BASE PLANE SEATING PLANE .300 BSC .600 BSC .008 .018 94° 105° .700 MAX 16-000038H-3 CDV040 DF11 3-30-95 ae DATUM D CENTER PLANE DATUM D CENTER PLANE UV Lens Pin 1 I.D. 2.040 2.080 .530 .580 .005 MIN .045 .065 .090 .110 .140 .225 .120 .160 .014 .022 SEATING PLANE .015 .060 16-038-SC_AF PD 040 DG76 2-28-95 ae 40 21 .630 .700 10° .600 .625 .008 .015
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PL 044—44-Pin Plastic Leaded Chip Carrier (measured in inches) REVISION SUMMARY FOR AM27C4096 Revision F Global Changed formatting to match current data sheets. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Flashrite is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. TOP VIEW SEATING PLANE .685 .695 .650 .656 Pin 1 I.D. .685 .695 .650 .656 .026 .032 .050 REF .042 .056 .062 .083 .013 .021 .590 .630 .500 REF .009 .015 .165 .180 .090 .120 16-038-SQ PL 044 EC80 11.3.97 lv SIDE VIEW