XCO572XL-10CS48I

XC9572XL-5VQ44C AMD | Alldatasheet

Document overview

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• PDF pages: 10

Technical content

Features

• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (38 user I/O pins) - 64-pin VQFP (52 user I/O pins) - 100-pin TQFP (72 user I/O pins) - Pb-free available for all packages
• Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS Fast FLASH™ technology
• Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECT™ II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9572 device in the 44-pin PLCC package and the 100-pin TQFP package WARNING: Programming temperature range of T A = 0° C to +70° C

Description

The XC9572XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems. It is comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. See Figure 2 for overview. Power Estimation Power dissipation in CPLDs can vary substantially depend- ing on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addi- tion, unused product-terms and macrocells are automati- cally deactivated by the software to further conserve power. For a general estimate of I CC, the following equation may be used: ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP + 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f where: MCHS = # macrocells in high-speed configuration PTHS = average number of high-speed product terms per macrocell MC LP = # macrocells in low power configuration PTLP = average number of low power product terms per macrocell f = maximum clock frequency MCTOG = average % of flip-flops toggling per clock (~12%) This calculation was derived from laboratory measurements of an XC9500XL part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual I CC value varies with the design application and should be veri- fied during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007 00 Product Specification R

XC9572XL High Performance CPLD 2 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification R application note XAPP114, “Understanding XC9500XL CPLD Power.” Figure 1: Typical ICC vs. Frequency for XC9572XL Clock Frequency (MHz) Typical ICC (mA) 100 200 DS057_01_010102 125 100 50 150

104 MHz

178 MHz

r Figure 2: XC9572XL Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. In-System Programming ControllerJTAG Controller I/O Blocks Function Block 1 Macrocells 1 to 18 Macrocells 1 to 18 JTAG Port I/O/GTS I/O/GSR I/O/GCK I/O I/O I/O I/O I/O I/O I/O I/O DS057_02_082800 Function Block 2 Function Block 3 Macrocells 1 to 18 Macrocells 1 to 18 Function Block 4 Fast CONNECT II Switch Matrix

XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007 www.xilinx.com 3 Product Specification R Absolute Maximum Ratings(2) Recommended Operation Conditions Quality and Reliability Characteristics DC Characteristic Over Recommended Operating Conditions Symbol Description Value Units VCC Supply voltage relative to GND –0.5 to 4.0 V VIN Input voltage relative to GND(1) –0.5 to 5.5 V VTS Voltage applied to 3-state output(1) –0.5 to 5.5 V TSTG Storage temperature (ambient)(3) –65 to +150 oC TJ Junction temperature +150 oC Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free packages, see XAPP427. Symbol Parameter Min Max Units VCCINT Supply voltage for internal logic and input buffers Commercial TA = 0oC to 70oC3 . 0 3 . 6 V Industrial TA = –40oC to +85oC3 . 0 3 . 6 V VCCIO Supply voltage for output drivers for 3.3V operation 3.0 3.6 V Supply voltage for output drivers for 2.5V operation 2.3 2.7 V V IL Low-level input voltage 0 0.80 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 V CCIO V Symbol Parameter Min Max Units TDR Data Retention 20 - Years NPE Program/Erase Cycles (Endurance) 10,000 - Cycles VESD Electrostatic Discharge (ESD) 2,000 - Volts Symbol Parameter Test Conditions Min Max Units VOH Output high voltage for 3.3V outputs I OH = –4.0 mA 2.4 - V Output high voltage for 2.5V outputs I OH = –500 μA9 0 % V CCIO -V VOL Output low voltage for 3.3V outputs I OL = 8.0 mA - 0.4 V Output low voltage for 2.5V outputs I OL = 500 μA- 0 . 4 V IIL Input leakage current V CC = Max; VIN = GND or VCC -± 1 0 μA IIH I/O high-Z leakage current V CC = Max; VIN = GND or VCC -± 1 0 μA IIH I/O high-Z leakage current V CC = Max; VCCIO = Max; VIN = GND or 3.6V -± 1 0 μA VCC Min < VIN < 5.5V - ±50 μA CIN I/O capacitance V IN = GND; f = 1.0 MHz - 10 pF ICC Operating supply current (low power mode, active) VIN = GND, No load; f = 1.0 MHz 20 (Typical) mA

XC9572XL High Performance CPLD 4 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification R AC Characteristics Symbol Parameter XC9572XL-5 XC9572XL-7 XC9572XL-10 UnitsMin Max Min Max Min Max TPD I/O to output valid - 5.0 - 7.5 - 10.0 ns TSU I/O setup time before GCK 3.7 - 4.8 - 6.5 - ns TH I/O hold time after GCK 0 - 0 - 0 - ns TCO GCK to output valid - 3.5 - 4.5 - 5.8 ns fSYSTEM Multiple FB internal operating frequency - 178.6 - 125.0 - 100.0 MHz TPSU I/O setup time before p-term clock input 1.7 - 1.6 - 2.1 - ns TPH I/O hold time after p-term clock input 2.0 - 3.2 - 4.4 - ns TPCO P-term clock output valid - 5.5 - 7.7 - 10.2 ns TOE GTS to output valid - 4.0 - 5.0 - 7.0 ns TOD GTS to output disable - 4.0 - 5.0 - 7.0 ns TPOE Product term OE to output enabled - 7.0 - 9.5 - 11.0 ns TPOD Product term OE to output disabled - 7.0 - 9.5 - 11.0 ns TAO GSR to output valid - 10.0 - 12.0 - 14.5 ns TPAO P-term S/R to output valid - 10.5 - 12.6 - 15.3 ns TWLH GCK pulse width (High or Low) 2.8 - 4.0 - 4.5 - ns TAPRPW Asynchronous preset/reset pulse width (High or Low) TPLH P-term clock pulse width (High or Low) 5.0 - 6.5 - 7.0 - ns Figure 3: AC Load Circuit Device Output Output Type V TEST 3.3V 2.5V VTEST 320 Ω 250 Ω R2 CL 360 Ω 660 Ω CL 35 pF 35 pF DS058_03_081500 VCCIO 3.3V 2.5V

XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007 www.xilinx.com 5 Product Specification R Internal Timing Parameters Symbol Parameter XC9572XL-5 XC9572XL-7 XC9572XL-10 UnitsMin Max Min Max Min Max Buffer Delays TIN Input buffer delay - 1.5 - 2.3 - 3.5 ns TGCK GCK buffer delay - 1.1 - 1.5 - 1.8 ns TGSR GSR buffer delay - 2.0 - 3.1 - 4.5 ns TGTS GTS buffer delay - 4.0 - 5.0 - 7.0 ns TOUT Output buffer delay - 2.0 - 2.5 - 3.0 ns TEN Output buffer enable/disable delay - 0 - 0 - 0 ns Product Term Control Delays TPTCK Product term clock delay - 1.6 - 2.4 - 2.7 ns TPTSR Product term set/reset delay - 1.0 - 1.4 - 1.8 ns TPTTS Product term 3-state delay - 5.5 - 7.2 - 7.5 ns Internal Register and Combinatorial Delays TPDI Combinatorial logic propagation delay - 0.5 - 1.3 - 1.7 ns TSUI Register setup time 2.3 - 2.6 - 3.0 - ns THI Register hold time 1.4 - 2.2 - 3.5 - ns TECSU Register clock enable setup time 2.4 - 2.6 - 3.0 - ns TECHO Register clock enable hold time 1.4 - 2.2 - 3.5 - ns TCOI Register clock to output valid time - 0.4 - 0.5 - 1.0 ns TAOI Register async. S/R to output delay - 6.0 - 6.4 - 7.0 ns TRAI Register async. S/R recover before clock 5.0 7.5 10.0 ns TLOGI Internal logic delay - 1.0 - 1.4 - 1.8 ns TLOGILP Internal low power logic delay - 5.0 - 6.4 - 7.3 ns Feedback Delays TF Fast CONNECT II feedback delay - 1.9 - 3.5 - 4.2 ns Time Adders TPTA Incremental product term allocator delay - 0.7 - 0.8 - 1.0 ns TSLEW Slew-rate limited delay - 3.0 - 4.0 - 4.5 ns

XC9572XL High Performance CPLD 6 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification R XC9572XL I/O Pins(4) Func- tion Block Macro- cell PC44 VQ44 CS48 VQ64 TQ100 BScan Order Func -tion Block Macro- c e l l P C 4 4V Q 4 4C S 4 8V Q 6 4 T Q 1 0 0 BScan Order 1 1 ---- 1 6 2 1 3 3 1 ---- 4 1 1 0 5 1 2 1 39 D7 8 13 210 3 2 11 5 B5 22 32 102 1 3 - - D4 12 18 207 3 3 - - C4 31 49 99 1 4 --- 1 3 2 0 2 0 4 3 4 --- 3 2 5 0 9 6 1 5 2 40 D6 9 14 201 3 5 12 6 A4 24 35 93 16 3 4 1 C 7 1 0 1 5 1 9 836 - - - 3 4 5 3 9 0 1 7 ---- 2 5 1 9 5 3 7 ---- 5 4 8 7 18 4 4 2 C 6 1 1 1 7 1 9 238 1 3 7 B 4 2 5 3 7 8 4 19 5 (1) 43(1) B7(1) 15(1) 22(1) 1 8 939 1 4 8 A 3 2 7 4 2 8 1 1 10 - - - 18 28 186 3 10 - - D3 39 60 78 11 1 6 (1) 44(1) B6(1) 16(1) 23(1) 183 3 11 18 12 B2 33 52 75 1 1 2--- 2 3 3 3 1 8 0 3 1 2--- 4 0 6 1 7 2 1 1 3---- 3 6 1 7 7 3 1 3---- 6 3 6 9 11 4 7 (1) 1(1) A7(1) 17(1) 27(1) 174 3 14 19 13 B1 35 55 66 11 5 8 2 A 6 1 9 2 9 1 7 1 31 5 2 0 1 4 C 2 3 6 5 6 6 3 1 1 6---- 3 9 1 6 8 3 1 6 2 4 1 8 D 2 4 2 6 4 6 0 11 7 9 3 C 5 2 0 3 0 1 6 5 31 7 2 2 1 6 C 3 3 8 5 8 5 7 1 1 8---- 4 0 1 6 2 3 1 8---- 5 9 5 4 2 1 ---- 8 7 1 5 9 4 1 ---- 6 5 5 1 2 2 35 29 F4 60 94 156 4 2 25 19 E1 43 67 48 2 3 --- 5 8 9 1 1 5 3 4 3 --- 4 6 7 1 4 5 2 4 --- 5 9 9 3 1 5 0 4 4 --- 4 7 7 2 4 2 2 5 36 30 G5 61 95 147 4 5 26 20 E2 44 68 39 2 6 37 31 F5 62 96 144 4 6 - - E4 49 76 36 2 7 ---- 3 (2) 1 4 1 4 7 ---- 7 7 3 3 2 8 38 32 G6 63 97 138 4 8 27 21 F1 45 70 30 29 3 9 2 1 0---1 1 1 3 2 4 1 0--- 5 1 8 1 2 4 21 1 4 0 (1) 34(1) F6(1) 2(1) 4(1) 129 4 11 28 22 G1 48 74 21 2 1 2---4 6 1 2 6 4 1 2--- 5 2 8 2 1 8 2 1 3----8 1 2 3 4 1 3---- 8 5 1 5 21 4 4 2 (3) 36(3) E6(3) 5(3) 9(3) 120 4 14 29 23 F2 50 78 12 2 15 43 37 E7 6 11 117 4 15 33 27 E3 56 89 9 2 1 6---- 1 0 1 1 4 4 1 6---- 8 6 6 21 7 4 4 3 8 E 5 7 1 2 1 1 1 41 7 3 4 2 8 G 4 5 7 9 0 3 2 1 8---- 9 2 1 0 8 4 1 8---- 7 9 0 Notes: 1. Global control pin. 2. GTS1 for TQ100. 3. GTS1 for PC44, VQ44, CS48, and VQ64. 4. The pin-outs are the same for Pb-free versions of packages.

XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007 www.xilinx.com 7 Product Specification R XC9572XL Global, JTAG and Power Pins(1) Pin Type PC44 VQ44 CS48 VQ64 TQ100 I/O/GCK1 5 43 B7 15 22 I/O/GCK2 6 44 B6 16 23 I/O/GCK3 7 1 A7 17 27 I/O/GTS1 42 36 E6 5 3 I/O/GTS2 40 34 F6 2 4 I/O/GSR 39 33 G7 64 99 TCK 17 11 A1 30 48 TDI 15 9 B3 28 45 TDO 30 24 G2 53 83 TMS 16 10 A2 29 47 V CCINT 3.3V 21, 41 15, 35 C1, F7 3, 37 5, 57, 98 VCCIO 2.5V/3.3V 32 26 G3 26, 55 26, 38, 51, 88 GND 10, 23, 31 4, 17, 25 A5, D1, F3 14, 21, 41, 54 21, 31, 44, 62, 69, 75, 84, 100 N o C o n n e c t s ---- 2 , 7 , 1 9 , 2 4 , 3 4 , 43, 46, 73, 80 Notes: 1. The pin-outs are the same for Pb-free versions of packages.

XC9572XL High Performance CPLD 8 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification R Device Part Marking and Ordering Combination Information Device Ordering and Part Marking Number Speed (pin-to-pin delay) Pkg. Symbol No. of Pins Package Type Operating Range(1) XC9572XL-5PC44C 5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C XC9572XL-5VQ44C 5 ns VQ44 44-pin Quad Flat Pack (VQFP) C XC9572XL-5CS48C 5 ns CS48 48-ball Chip Scale Package (CSP) C XC9572XL-5VQ64C 5 ns VQ64 64-pin Quad Flat Pack (VQFP) C XC9572XL-5TQ100C 5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C XC9572XL-7PC44C 7.5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C XC9572XL-7VQ44C 7.5 ns VQ44 44-pin Quad Flat Pack (VQFP) C XC9572XL-7CS48C 7.5 ns CS48 48-ball Chip Scale Package (CSP) C XC9572XL-7VQ64C 7.5 ns VQ64 64-pin Quad Flat Pack (VQFP) C XC9572XL-7TQ100C 7.5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C XC9572XL-7PC44I 7.5 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I XC9572XL-7VQ44I 7.5 ns VQ44 44-pin Quad Flat Pack (VQFP) I XC9572XL-7CS48I 7.5 ns CS48 48-ball Chip Scale Package (CSP) I XC9572XL-7VQ64I 7.5 ns VQ64 64-pin Quad Flat Pack (VQFP) I XC9572XL-7TQ100I 7.5 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I XC9572XL-10PC44C 10 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) C XC9572XL-10VQ44C 10 ns VQ44 44-pin Quad Flat Pack (VQFP) C XC9572XL-10CS48C 10 ns CS48 48-ball Chip Scale Package (CSP) C XC9572XL-10VQ64C 10 ns VQ64 64-pin Quad Flat Pack (VQFP) C XC9572XL-10TQ100C 10 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) C XC9572XL-10PC44I 10 ns PC44 44-pin Plastic Lead Chip Carrier (PLCC) I XC9572XL-10VQ44I 10 ns VQ44 44-pin Quad Flat Pack (VQFP) I XC9572XL-10CS48I 10 ns CS48 48-ball Chip Scale Package (CSP) I XC9572XL-10VQ64I 10 ns VQ64 64-pin Quad Flat Pack (VQFP) I XC9572XL-10TQ100I 10 ns TQ100 100-pin Thin Quad Flat Pack (TQFP) I Notes: C = Commercial: TA = 0° to +70°C; I = Industrial: TA = –40° to +85°C Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line:

• Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXL.
• Line 2 = Not related to device part number.
• Line 3 = Not related to device part number.
• Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C1 = CS48, C2 = CSG48. XC95xxxXL TQ144 Device Type Package Speed Operating Range This line not related to device part number Sample package with part marking. R

XC9572XL High Performance CPLD DS057 (v2.0) April 3, 2007 www.xilinx.com 9 Product Specification R XC9572XL-5PCG44C 5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free C XC9572XL-5VQG44C 5 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free C XC9572XL-5CSG48C 5 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free C XC9572XL-5VQG64C 5 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free C XC9572XL-5TQG100C 5 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-free C XC9572XL-7PCG44C 7.5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free C XC9572XL-7VQG44C 7.5 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free C XC9572XL-7CSG48C 7.5 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free C XC9572XL-7VQG64C 7.5 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free C XC9572XL-7TQG100C 7.5 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-free C XC9572XL-7PCG44I 7.5 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free I XC9572XL-7VQG44I 7.5 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free I XC9572XL-7CSG48I 7.5 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free I XC9572XL-7VQG64I 7.5 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free I XC9572XL-7TQG100I 7.5 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-free I XC9572XL-10PCG44C 10 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free C XC9572XL-10VQG44C 10 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free C XC9572XL-10CSG48C 10 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free C XC9572XL-10VQG64C 10 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free C XC9572XL-10TQG100C 10 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-free C XC9572XL-10PCG44I 10 ns PCG44 44-pin Plastic Lead Chip Carrier (PLCC); Pb-free I XC9572XL-10VQG44I 10 ns VQG44 44-pin Quad Flat Pack (VQFP); Pb-free I XC9572XL-10CSG48I 10 ns CSG48 48-ball Chip Scale Package (CSP); Pb-free I XC9572XL-10VQG64I 10 ns VQG64 64-pin Quad Flat Pack (VQFP); Pb-free I XC9572XL-10TQG100I 10 ns TQG100 100-pin Thin Quad Flat Pack (TQFP); Pb-free I Notes: 1. C = Commercial: T A = 0° to +70°C; I = Industrial: TA = –40° to +85°C Device Ordering and Part Marking Number Speed (pin-to-pin delay) Pkg. Symbol No. of Pins Package Type Operating Range(1) Standard Example: XC9572XL Device Speed Grade Package Type Number of Pins Temperature Range -4 TQ C 144 Pb-Free Example: XC9572XL TQ G 144 C Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range

XC9572XL High Performance CPLD 10 www.xilinx.com DS057 (v2.0) April 3, 2007 Product Specification R Warranty Disclaimer THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUC TS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS TH AT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Further Reading The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down. Data Sheets, Application Notes, and White Papers. Packaging

Revision History

The following table shows the revision history for this document. Date Version Revision 09/28/98 1.0 Initial Xilinx release. 08/28/01 1.1 Added VQ44 package. 06/20/02 1.2 Updated I CC equation, page 1. Updated Component Availability table. Added additional IIH test conditions and measurements to DC Characteristics table. 05/27/03 1.3 Updated T SOL from 260 to 220oC. Added Part Marking and updated Ordering Information. 08/21/03 1.4 Updated Package Device Marking Pin 1 orientation. 07/15/04 1.5 Added Pb-free documentation 09/15/04 1.6 Added T APRPW specification to AC Characteristics. 04/29/05 1.7 No change to documentation. 07/15/05 1.8 Move to Product Specification 03/22/06 1.9 Add Warranty Disclaimer. 04/03/07 2.0 Add programming temperature range warning on page 1.