XCKU025

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DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 1 © Copyright 2013–2017 Xilinx, Inc. Xi linx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other design ated brands included herein are trademarks of Xilinx in the United States and other countries. All othe r trademarks are the property of their respective owners. Summary The Xilinx® Kintex® UltraScale™ FPGAs are available in -3, -2, -1, and -1L speed grades, with -3 having the highest performance. The -1L devices can operate at either of two V CCINT voltages, 0.95V and 0.90V and are screened for lower maximum stat ic power. When operated at V CCINT = 0.95V, the speed specification of a -1L device is the same as the -1 speed grade. When operated at V CCINT = 0.90V, the -1L performance and static and dynamic power is reduced. DC and AC characteristics are specified in commerci al, extended, industrial, and military temperature ranges. Except the operating temperature range or unl ess otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 spee d grade commercial device). However, only selected speed grades and/or devices are av ailable in each temperature range. All supply voltage and junction temp erature specifications are representative of worst-case conditions. The parameters included are common to po pular designs and typical applications. This data sheet, part of an overall set of documentat ion on the UltraScale architecture-based devices, is available on the Xilinx website at www.xilinx.com/documentation . DC Characteristics Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 Product Specification Table 1: Absolute Maximum Ratings(1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage –0.500 1.100 V VCCINT_IO(2) Internal supply voltage for the I/O banks –0.500 1.100 V VCCAUX Auxiliary supply voltage –0.500 2.000 V VCCBRAM Supply voltage for the block RAM memories –0.500 1.100 V VCCO Output drivers supply voltage for HR I/O banks –0.500 3.400 V Output drivers supply voltage for HP I/O banks –0.500 2.000 V VCCAUX_IO(3) Auxiliary supply voltage for the I/O banks –0.500 2.000 V VREF Input reference voltage –0.500 2.000 V VIN(4)(6)(7) I/O input voltage for HR I/O banks(5) –0.400 V CCO + 0.550 V I/O input voltage for HP I/O banks –0.550 V CCO + 0.550 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(8) –0.400 2.625 V Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 2 VBATT Key memory battery backup supply –0.500 2.000 V IDC Available output current at the pad –20 20 mA IRMS Available RMS output current at the pad –20 20 mA GTH and GTY Transceivers VMGTAVCC Analog supply voltage for the GTH and GTY transmitter and receiver circuits –0.500 1.100 V VMGTAVTT Analog supply voltage for the GTH and GTY transmitter and receiver termination circuits –0.500 1.320 V VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTH and GTY transceivers –0.500 1.935 V VMGTREFCLK GTH and GTY transceiver reference clocks absolute input voltage –0.500 1.320 V VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTH and GTY transceiver columns –0.500 1.320 V VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.500 1.260 V IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating –0 (9) mA IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT –1 0 m A IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND –1 0 m A IDCIN-PROG DC input current for receiver input pins DC coupled RX termination = Programmable –N / A (9) mA IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating –0 (9) mA IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT –6 m A System Monitor VCCADC System Monitor supply relative to GNDADC –0.500 2.000 V VREFP System Monitor reference input relative to GNDADC –0.500 2.000 V Temperature TSTG Storage temperature (ambient) –65 150 °C TSOL Maximum soldering temperature for Pb-free component bodies(10) – 260 °C Maximum soldering temperature for Pb/Sn component bodies(10) – 220 °C Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 3 Tj Maximum junction temperature(10) – 125 °C Notes: 1. Stresses beyond those listed under Absolute Maximum Rati ngs might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. V CCINT_IO must be connected to VCCINT. 3. V CCAUX_IO must be connected to VCCAUX. 4. The lower absolute voltage specification always applies. 5. If V CCO is 3.3V, the maximum voltage is 3.4V. 6. For I/O operation, see the UltraScale Architecture SelectIO Resources User Guide (UG571). 7. The maximum limit applied to DC signals. For maxi mum undershoot and overshoot AC specifications, see Table 4 and Table 5. 8. See Table 12 for TMDS_33 specifications. 9. For more information on supported GTH or GTY transceiver terminations see the UltraScale Architecture GTH Transceiver User Guide (UG576) or the UltraScale Architecture GTY Transceiver User Guide (UG578). 10. For soldering guidelines and thermal considerations, see the UltraScale and UltraScale+ FPGAs Packaging and Pinout Specifications (UG575). Table 2: Recommended Operating Conditions(1)(2) Symbol Description Min Typ Max Units FPGA Logic VCCINT Internal supply voltage 0.922 0.950 0.979 V For -1L (0.90V) devices: internal supply voltage 0.880 0.900 0.920 V For -3 (1.0V only) devices: internal supply voltage 0.970 1.000 1.030 V V CCINT_IO(3) Internal supply voltage for the I/O banks 0.922 0.950 0.979 V For -1L (0.90V) devices: internal supply voltage for the I/O banks 0.880 0.900 0.920 V For -3 (1.0V only) devices: internal supply voltage for the I/O banks 0.970 1.000 1.030 V VCCBRAM Block RAM supply voltage 0.922 0.950 0.979 V For -3 (1.0V only) devices: block RAM supply voltage 0.970 1.000 1.030 V VCCAUX Auxiliary supply voltage 1.746 1.800 1.854 V VCCO(4)(5) Supply voltage for HR I/O banks 1.140 – 3.400 V Supply voltage for HP I/O banks 0.950 – 1.890 V VCCAUX_IO(6) Auxiliary I/O supply voltage 1.746 1.800 1.854 V VIN(7) I/O input voltage –0.200 – V CCO + 0.200 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(8). – 0.400 2.625 V IIN(9) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ––1 0 . 0 0 0 m A VBATT(10) Battery voltage 1.000 – 1.890 V GTH and GTY Transceivers VMGTAVCC(11) Analog supply voltage for the GTH and GTY transceivers(10) 0.970 1.000 1.030 V VMGTAVTT(11) Analog supply voltage for the GTH and GTY transmitter and receiver termination circuits 1.170 1.200 1.230 V VMGTVCCAUX(11) Auxiliary analog QPLL voltage supply for the transceivers 1.750 1.800 1.850 V Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 4 VMGTAVTTRCAL(11) Analog supply voltage for the resistor calibration circuit of the GTH and GTY transceiver columns 1.170 1.200 1.230 V SYSMON VCCADC SYSMON supply relative to GNDADC 1.746 1.800 1.854 V VREFP Externally supplied reference voltage 1.200 1.250 1.300 V Temperature Tj Junction temperature operating range for commercial (C) temperature devices 0– 8 5 ° C Junction temperature operating range for extended (E) temperature devices 0 – 100 °C Junction temperature operating range for industrial (I) temperature devices –40 – 100 °C Junction temperature operating range for military (M) temperature devices –55 – 125 °C Notes: 1. All voltages are relative to ground. 2. For the design of the power distribution system consult UltraScale Architecture PCB Design Guide (UG583). 3. V CCINT_IO must be connected to VCCINT. 4. For V CCO_0, the minimum recommended operating voltage for power on and during configuration is 1.425V. After configuration, data is retained even if VCCO drops to 0V. +3/–5%. 6. V CCAUX_IO must be connected to VCCAUX. 7. The lower absolute voltage specification always applies. 8. See Table 12 for TMDS_33 specifications. 9. A total of 200 mA per 52-pin bank should not be exceeded. 10. VBATT is required only when using bitstream encryption. If battery is not used, connect V BATT to either ground or VCCAUX. 11. Each voltage listed requires filtering as described in UltraScale Architecture GTH Transceiver User Guide (UG576). Table 2: Recommended Operating Conditions(1)(2) (Cont’d) Symbol Description Min Typ Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 5 Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ (1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.82 – – V VDRAUX Data retention VCCAUX voltage (below which configuration data might be lost) 1.50 – – V IREF VREF leakage current per pin – – 15 µA IL Input or output leakage current per pin (sample-tested) – – 15 (2) µA Input or output leakage current per pin for XQ devices (sample-tested) –– 2 0 (2) µA CIN(3) Die input capacitance at the pad (HP I/O) – – 3.75 pF Die input capacitance at the pad (HR I/O) – – 7.00 pF IRPU Pad pull-up (when selected) at VIN =0 V , VCCO =3 . 3 V 7 5 – 1 7 5 µ A Pad pull-up (when selected) at VIN =0 V , VCCO =2 . 5 V 5 0 – 1 6 9 µ A Pad pull-up (when selected) at VIN =0 V , VCCO =1 . 8 V 6 0 – 6 7 8 µ A Pad pull-up (when selected) at VIN =0 V , VCCO =1 . 5 V 3 0 – 4 5 0 µ A Pad pull-up (when selected) at VIN =0 V , VCCO =1 . 2 V 1 0 – 2 6 2 µ A IRPD Pad pull-down (when selected) at VIN =3 . 3 V 6 0 – 1 9 0 µ A Pad pull-down (when selected) at VIN =1 . 8 V 2 9 – 6 8 5 µ A ICCADC Analog supply current per SYSMON instance in powered up state. – – 19.2 mA IBATT(4) Battery supply current – – 150 nA Calibrated programmable on-die termination (DCI) in HP I/O banks(6) (measured per JEDEC specification) R(7) Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_40 –10%(5) 40 +10% (5) Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –10%(5) 48 +10% (5) Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_60 –10%(5) 60 +10% (5) Ω Programmable input termination to VCCO where Programmable input termination to VCCO where Programmable input termination to VCCO where Programmable input termination to VCCO where Programmable input termination to VCCO where Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 6 Uncalibrated programmable on-die termination in HP I/Os banks (measured per JEDEC specification) R(7) Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_40 –50% 40 +50% Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –50% 48 +50% Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_60 –50% 60 +50% Ω Programmable input termination to VCCO where ODT = RTT_40 –50% 40 +50% Ω Programmable input termination to VCCO where ODT = RTT_48 –50% 48 +50% Ω Programmable input termination to VCCO where ODT = RTT_60 –50% 60 +50% Ω Programmable input termination to VCCO where ODT = RTT_120 –50% 120 +50% Ω Programmable input termination to VCCO where ODT = RTT_240 –50% 240 +50% Ω Uncalibrated programmable on-die termination in HR I/O banks (measured per JEDEC specification) R(7) Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_40 –50% 40 +50% Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –50% 48 +50% Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_60 –50% 60 +50% Ω Internal VREF 50% VCCO VCCO x 0.49 VCCO x 0.50 VCCO x 0.51 V 70% VCCO VCCO x 0.69 VCCO x 0.70 VCCO x 0.71 V Differential termination Programmable differential termination (TERM_100) – 100 – Ω n Temperature diode ideality factor – 1.002 – – r Temperature diode series resistance – 2 – Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. For HP I/O banks with a V CCO of 1.8V and separated VCCO and VCCAUX_IO power supplies, the IL maximum current is 70 µA. 3. This measurement represents the die capacitance at the pad, not including the package. 4. Maximum value specified for worst case process at 25°C. 5. If VRP resides at a different bank (DCI cascade), the range increases to ±15%. 6. VRP resistor tolerance is (240 Ω ±1%) 7. On-die input termination resistance, for more information see the UltraScale Architecture SelectIO Resources User Guide (UG571 Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d) Symbol Description Min Typ (1) Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 7 Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1) AC Voltage Overshoot % of UI at –40°C to 100°C AC Voltage Undershoot % of UI at –40°C to 100°C VCCO + 0.30 100% –0.30 100% VCCO + 0.35 100% –0.35 70.00% VCCO + 0.40 100% –0.40 27.00% VCCO + 0.45 100% –0.45 10.00% Notes: 1. A total of 200 mA per bank should not be exceeded. Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks(1)(2) AC Voltage Overshoot % of UI at –40°C to 100°C A C Voltage Undershoot % of UI at –40°C to 100°C VCCO + 0.05 100% –0.05 100% VCCO + 0.10 100% –0.10 100% VCCO + 0.15 100% –0.15 100% VCCO + 0.20 100% –0.20 100% VCCO + 0.25 100% –0.25 100% VCCO + 0.30 100% –0.30 100% Notes: 1. A total of 200 mA per bank should not be exceeded. 2. For UI smaller than 20 µs. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 8 Table 6: Typical Quiescent Supply Current Symbol Description Device Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L ICCINTQ Quiescent VCCINT supply current XCKU025 N/A 998 998 N/A N/A mA XCKU035 1097 998 998 998 907 mA XCKU040 1097 998 998 998 907 mA XCKU060 1590 1446 1446 1446 1315 mA XCKU085 3181 2893 2893 2893 2631 mA XCKU095 N/A 2100 2100 N/A N/A mA XCKU115 3181 2893 2893 2893 2631 mA XQKU040 N/A 998 998 N/A N/A mA XQKU060 N/A 1446 1446 N/A N/A mA XQKU095 N/A 2100 2100 N/A N/A mA XQKU115 N/A 2893 2893 N/A N/A mA I CCINT_IOQ Quiescent current for VCCINT_IO supply XCKU025 N/A 87 87 N/A N/A mA X C K U 0 3 5 9 88 78 78 77 7 m A X C K U 0 4 0 9 88 78 78 77 7 m A XCKU060 118 105 105 105 93 mA XCKU085 236 210 210 210 187 mA XCKU095 N/A 143 143 N/A N/A mA XCKU115 236 210 210 210 187 mA XQKU040 N/A 87 87 N/A N/A mA XQKU060 N/A 105 105 N/A N/A mA XQKU095 N/A 143 143 N/A N/A mA XQKU115 N/A 210 210 N/A N/A mA I CCOQ Quiescent VCCO supply current XCKU025 N/A 1 1 N/A N/A mA X C K U 0 3 5 11111 m A X C K U 0 4 0 11111 m A X C K U 0 6 0 11111 m A X C K U 0 8 5 11111 m A XCKU095 N/A 1 1 N/A N/A mA X C K U 1 1 5 11111 m A XQKU040 N/A 1 1 N/A N/A mA XQKU060 N/A 1 1 N/A N/A mA XQKU095 N/A 1 1 N/A N/A mA XQKU115 N/A 1 1 N/A N/A mA Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 9 ICCAUXQ Quiescent VCCAUX supply current XCKU025 N/A 145 145 N/A N/A mA XCKU035 145 145 145 145 145 mA XCKU040 145 145 145 145 145 mA XCKU060 188 188 188 188 188 mA XCKU085 376 376 376 376 376 mA XCKU095 N/A 273 273 N/A N/A mA XCKU115 376 376 376 376 376 mA XQKU040 N/A 145 145 N/A N/A mA XQKU060 N/A 188 188 N/A N/A mA XQKU095 N/A 273 273 N/A N/A mA XQKU115 N/A 376 376 N/A N/A mA I CCAUX_IOQ Quiescent VCCAUX_IO supply current XCKU025 N/A 66 66 N/A N/A mA X C K U 0 3 5 6 66 66 66 66 6 m A X C K U 0 4 0 6 66 66 66 66 6 m A X C K U 0 6 0 8 38 38 38 38 3 m A XCKU085 165 165 165 165 165 mA XCKU095 N/A 124 124 N/A N/A mA XCKU115 165 165 165 165 165 mA XQKU040 N/A 66 66 N/A N/A mA XQKU060 N/A 83 83 N/A N/A mA XQKU095 N/A 124 124 N/A N/A mA XQKU115 N/A 165 165 N/A N/A mA I CCBRAMQ Quiescent VCCBRAM supply current XCKU025 N/A 39 39 N/A N/A mA X C K U 0 3 5 4 23 93 93 93 9 m A X C K U 0 4 0 4 23 93 93 93 9 m A X C K U 0 6 0 7 66 96 96 96 9 m A XCKU085 153 139 139 139 139 mA XCKU095 N/A 111 111 N/A N/A mA XCKU115 153 139 139 139 139 mA XQKU040 N/A 39 39 N/A N/A mA XQKU060 N/A 69 69 N/A N/A mA XQKU095 N/A 111 111 N/A N/A mA XQKU115 N/A 139 139 N/A N/A mA Notes: 1. Typical values are specified at nomina l voltage, 85°C junction temperatures (Tj) with single-ended SelectIO™ resources. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. Use the Xilinx Power Estimator (XPE ) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for conditions other than those specified. Table 6: Typical Quiescent Supply Current (Cont’d) Symbol Description Device Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 10 Power-On/Off Power Supply Sequencing The recommended power-on sequence is V CCINT /VCCINT_IO , VCCBRAM , VCCAUX /VCCAUX_IO , and V CCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If V CCINT /VCCINT_IO and V CCBRAM have the same recommended voltage levels, th ey can be powered by the same supply and ramped simultaneously. VCCINT_IO must be connected to V CCINT . If V CCAUX /VCCAUX_IO and V CCO have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. V CCAUX and VCCAUX_IO must be connected together. When the current minimums are met, the device powers on after the VCCINT /VCCINT_IO , VCCBRAM , VCCAUX /VCCAUX_IO , and V CCO supplies have all passed through their power-on reset threshold voltages. The device mu st not be configured until after V CCINT is applied. VCCADC and V REF can be powered at any time and have no power-up sequencing recommendations. The recommended power-on sequence to achieve mini mum current draw for the GTH or GTY transceivers is VCCINT , VMGTAVCC , VMGTAVTT OR VMGTAVCC , VCCINT , VMGTAVTT . There is no recommended sequencing for VMGTVCCAUX . Both V MGTAVCC and V CCINT can be ramped simultaneous ly. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from V MGTAVTT can be higher than specifications during power-up and power-down. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 11 Table 7 shows the minimum current, in addition to I CCQ, that are required by Kintex UltraScale FPGAs for proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The device must not be configured until after V CCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies. Table 8 shows the power supply ramp time. Table 7: Power-on Current by Device Device I CCINTMIN +I CCINT_IOMIN ICCO ICCAUXMIN +I CCAUX_IOMIN ICCBRAMMIN Units XCKU025 I CCINTQ +I CCINT_IOQ + 2400 I CCO_0Q + 100 I CCAUXQ +I CCAUX_IOQ +3 8 0 I CCBRAMQ +5 0 m A XCKU035 I CCINTQ +I CCINT_IOQ + 2400 I CCO_0Q + 100 I CCAUXQ +I CCAUX_IOQ +3 8 0 I CCBRAMQ +5 0 m A XCKU040 I CCINTQ +I CCINT_IOQ + 2400 I CCO_0Q + 100 I CCAUXQ +I CCAUX_IOQ +3 8 0 I CCBRAMQ +5 0 m A XCKU060 I CCINTQ +I CCINT_IOQ + 3284 I CCO_0Q + 137 I CCAUXQ +I CCAUX_IOQ +5 2 0 I CCBRAMQ + 100 mA XCKU085 I CCINTQ +I CCINT_IOQ + 6568 I CCO_0Q + 274 I CCAUXQ +I CCAUX_IOQ + 1040 I CCBRAMQ + 137 mA XCKU095 I CCINTQ +I CCINT_IOQ + 3300 I CCO_0Q +4 0 I CCAUXQ +I CCAUX_IOQ +4 0 0 I CCBRAMQ + 150 mA XCKU115 I CCINTQ +I CCINT_IOQ + 6568 I CCO_0Q + 274 I CCAUXQ +I CCAUX_IOQ + 1040 I CCBRAMQ + 137 mA XQKU040 I CCINTQ +I CCINT_IOQ + 2400 I CCO_0Q + 100 I CCAUXQ +I CCAUX_IOQ +3 8 0 I CCBRAMQ +5 0 m A XQKU060 I CCINTQ +I CCINT_IOQ + 3284 I CCO_0Q + 137 I CCAUXQ +I CCAUX_IOQ +5 2 0 I CCBRAMQ + 100 mA XQKU095 I CCINTQ +I CCINT_IOQ + 3300 I CCO_0Q +4 0 I CCAUXQ +I CCAUX_IOQ +4 0 0 I CCBRAMQ + 150 mA XQKU115 I CCINTQ +I CCINT_IOQ + 6568 I CCO_0Q + 274 I CCAUXQ +I CCAUX_IOQ + 1040 I CCBRAMQ + 137 mA Table 8: Power Supply Ramp Time Symbol Description Min Max Units TVCCINT Ramp time from GND to 95% of VCCINT 0.2 40 ms TVCCINT_IO Ramp time from GND to 95% of VCCINT_IO 0.2 40 ms TVCCO Ramp time from GND to 95% of VCCO 0.2 40 ms TVCCAUX Ramp time from GND to 95% of VCCAUX 0.2 40 ms TVCCBRAM Ramp time from GND to 95% of VCCBRAM 0.2 40 ms TMGTAVCC Ramp time from GND to 95% of VMGTAVCC 0.2 40 ms TMGTAVTT Ramp time from GND to 95% of VMGTAVTT 0.2 40 ms TMGTVCCAUX Ramp time from GND to 95% of VMGTVCCAUX 0.2 40 ms Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 12 DC Input and Output Levels Values for V IL and V IH are recommended input voltages. Values for I OL and I OH are guaranteed over the recommended operating conditions at the V OL and V OH test points. Only selected standards are tested. These are chosen to ensure that all standards meet th eir specifications. The selected standards are tested at a minimum V CCO with the respective V OL and V OH voltage levels shown. Other standards are sample tested. Table 9: SelectIO DC Input and Output Levels For HR I/O Banks(1)(2) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVCMOS12 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.400 V CCO – 0.400 Note 3 Note 3 LVCMOS15 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.450 V CCO – 0.450 Note 4 Note 4 LVCMOS18 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.450 V CCO – 0.450 Note 4 Note 4 Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O st andard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). 3. Supported drive stre ngths of 4, 8, or 12 mA in HR I/O banks. 4. Supported drive streng ths of 4, 8, 12, or 16 mA in HR I/O banks. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 13 Table 10: SelectIO DC Input and Output Levels for HP I/O Banks(1)(2)(3) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVCMOS12 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.400 V CCO – 0.400 Note 4 Note 4 LVCMOS15 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.450 V CCO – 0.450 Note 5 Note 5 LVCMOS18 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.450 V CCO – 0.450 Note 5 Note 5 Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O st andard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). 3. POD10 and POD12 DC input and output levels are shown in Table 11, Table 16, and Table 17. 4. Supported drive streng ths of 2, 4, 6, or 8 mA in HP I/O banks. 5. Supported drive strength s of 2, 4, 6, 8, or 12 mA in HP I/O banks. Table 11: DC Input Levels for Single-ended POD10 and POD12 I/O Standards(1)(2) I/O Standard VIL VIH V, Min V, Max V, Min V, Max POD10 –0.300 V REF – 0.068 V REF +0 . 0 6 8 V CCO + 0.300 POD12 –0.300 V REF – 0.068 V REF +0 . 0 6 8 V CCO + 0.300 Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O st andard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 14 Table 12: Differential SelectIO DC Input and Output Levels I/O Standard VICM (V)(1) VID(V)(2) VOCM(V)(3) VOD(V)(4) Min Typ Max Min Typ Max Min Typ Max Min Typ Max PPDS_25 0.200 0.900 V Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage (Q – Q). 3. V OCM is the output common mode voltage. 4. V OD is the output differential voltage (Q – Q). 5. V OD for BLVDS will vary significantly depending on topology and loading. 6. LVDS_25 is specified in Table 18. 7. LVDS is specified in Table 19. Table 13: Complementary Differential SelectIO DC Input and Output Levels for HR I/O Banks I/O Standard VICM (V)(1) VID (V)(2) VOL (V)(3) VOH (V)(4) IOL IOH Min Typ Max Min Max Max Min mA mA Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage. 3. V OL is the single-ended low-output voltage. 4. V OH is the single-ended high-output voltage. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 15 Table 14: Complementary Differential SelectIO DC Input and Output Levels for HP I/O Banks(1) I/O Standard VICM (V)(2) VID (V)(3) VOL (V)(4) VOH (V)(5) IOL IOH Min Typ Max Min Max Max Min mA mA Notes: 1. DIFF_POD10 and DIFF_POD12 HP I/O ba nk specifications are shown in Table 15, Table 16, and Table 17. 2. V ICM is the input common mode voltage. 3. V ID is the input differential voltage. 4. V OL is the single-ended low-output voltage. 5. V OH is the single-ended high-output voltage. Table 15: DC Input Levels for Differential POD10 and POD12 I/O Standards(1)(2) I/O Standard VICM (V) V ID (V) Min Typ Max Min Max DIFF_POD10 0.63 0.70 0.77 0.14 – DIFF_POD12 0.76 0.84 0.92 0.16 – Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O st andard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). Table 16: DC Output Levels for Single-ended and Differential POD10 and POD12 Standards(1)(2) Symbol Description V OUT Min Typ Max Units ROL Pull-down resistance V OM_DC (as described in Table 17) 3 64 04 4 Ω ROH Pull-up resistance V OM_DC (as described in Table 17) 3 64 04 4 Ω Notes: 1. Tested according to relevant specifications. 2. Standards specified using the default I/O st andard configuration. For details, see the UltraScale Architecture SelectIO Resources User Guide (UG571). Table 17: Table 16 Definitions for DC Output Levels for POD Standards Symbol Description All Devices Units VOM_DC DC output Mid measurement level (for IV curve linearity) 0.8 x V CCO V Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 16 LVDS DC Specifications (LVDS_25) The LVDS_25 standard is available in the HR I/O banks. See the UltraScale Architectu re SelectIO Resources User Guide (UG571 ) for more information. LVDS DC Specifications (LVDS) The LVDS standard is available in the HP I/O banks. See the UltraScale Architecture SelectIO Resources User Guide (UG571 ) for more information. Table 18: LVDS_25 DC Specifications Symbol DC Parameter Conditions Min Typ Max Units VCCO Supply voltage 2.375 2.500 2.625 V VODIFF(1) Differential Output Voltage: (Q – Q), Q = High (Q –Q ) , Q=H i g h RT =1 0 0Ω across Q and Q signals 247 350 600 mV VOCM(1) Output Common-Mode Voltage R T =1 0 0 Ω across Q and Q signals 1.000 1.250 1.485 V VIDIFF Differential Input Voltage: (Q – Q), Q = High (Q –Q ) , Q=H i g h 100 350 600 (2) mV VICM_DC(3) Input Common-Mode Voltage (DC Coupling) 0.300 1.200 1.500 V VICM_AC(4) Input Common-Mode Voltage (AC Coupling) 0.600 – 1.100 V Notes: 1. V OCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE. 2. Maximum V IDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained. 3. Input common mode voltage for DC coupled co nfigurations. EQUALIZATION = EQ_NONE (Default). 4. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4. Table 19: LVDS DC Specifications Symbol DC Parameter Conditions Min Typ Max Units VCCO Supply voltage 1.710 1.800 1.890 V VODIFF(1) Differential Output Voltage (Q – Q), Q = High (Q –Q ) , Q=H i g h RT =1 0 0Ω across Q and Q signals 247 350 600 mV VOCM(1) Output Common-Mode Voltage R T =1 0 0 Ω across Q and Q signals 1.000 1.250 1.425 V VIDIFF Differential Input Voltage (Q – Q), Q = High (Q –Q ) , Q=H i g h 100 350 600 (2) mV VICM_DC(3) Input Common-Mode Voltage (DC Coupling) 0.300 1.200 1.425 V VICM_AC(4) Input Common-Mode Voltage (AC Coupling) 0.600 – 1.100 V Notes: 1. V OCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE. 2. Maximum V IDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained. 3. Input common mode voltage for DC coupled co nfigurations. EQUALIZATION = EQ_NONE (Default). 4. External input common mode voltage specification for AC coupled configurations. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, EQ_LEVEL4. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 17 AC Switching Characteristics All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite as outlined in Table 20 . Switching characteristics are specified on a per-spee d-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance Product Specification These specifications are based on simulations only an d are typically available so on after device design specifications are frozen. Although speed grades with this designation are consider ed relatively stable and conservative, some under-rep orting might still occur. Preliminary Product Specification These specifications are based on complete ES (engin eering sample) silicon characterization. Devices and speed grades with this designation are intended to gi ve a better indication of the expected performance of production silicon. The probability of under-repo rting delays is greatly reduced as compared to Advance data. Product Specification These specifications are released once enough producti on silicon of a particular device family member has been characterized to provide full correlation be tween specifications and devices over numerous production lots. There is no under-reporting of dela ys, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to production before faster speed grades. Testing of AC Switching Characteristics Internal timing parameters are derived from meas uring internal test patt erns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. For more specific, more precise, and worst-case guar anteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex UltraScale FPGAs. Table 20: Speed Specification Version By Device

2016.4 Device

1.23 XCKU025, XCKU035, XCKU04 0, XCKU060, XQKU040, XQKU060

1.24 XCKU085, XCKU095, XCKU 115, XQKU095, XQKU115

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 18 Speed Grade Designations Since individual family members are produced at di fferent times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 21 correlates the current status of the Kintex UltraS cale FPGAs on a per speed grade basis. Table 21: Speed Grade Designations by Device Device Speed Grade and VCCINT Operating Voltages Advance Preliminary Production XCKU025 -2 (0.95V) and -1 (0.95V) -1L (0.90V)(1) -1L (0.90V)(1) -1L (0.90V)(1) -1L (0.90V)(1) XCKU095 -2 (0.95V) and -1 (0.95V) -1L (0.90V)(1) XQKU040 -2 (0.95V) and -1 (0.95V) XQKU060 -2 (0.95V) and -1 (0.95V) XQKU095 -2 (0.95V) and -1 (0.95V) XQKU115 -2 (0.95V) and -1 (0.95V) Notes: 1. The lowest power -1L devices, where V CCINT = 0.90V, are listed in the Vivado Design Suite as -1LV. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 19 Production Silicon and Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with th e correct label (Advance, Prelimin ary, Production). Any labeling discrepancies are corrected in subseq uent speed specification releases. Table 22 lists the production released Kintex UltraScale FPGAs, speed grade, and the minimum corresponding supported speed specification version an d Vivado software revisions. The Vivado software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 22: Kintex UltraScale FPGAs Production Software and Speed Specification Release(1) Device Speed Grade, Temperature Ranges, and VCCINT Operating Voltages 1.0V 0.95V 0.90V -3E -2E, -2I -1C, -1I -1M -1LI -1LI (3) XCKU025(2) N/A Vivado Tools 2015.3 v1.23 N/A N/A N/A XCKU035(2) Vivado Tools 2015.2.1 v1.23 for FBVA676 and FFVA1156 packages Vivado Tools 2015.1 v1.23 for FBVA676 and FFVA1156 packages N/A Vivado Tools 2015.3 v1.23 Vivado Tools 2015.3 v1.23 for FBVA900 N/A Vivado Tools 2015.4 v1.23 for SFVA784 N/A Vivado Tools 2015.4 v1.23 for SFVA784 XCKU040(2) Vivado Tools 2015.2.1 v1.23 for FBVA676 and FFVA1156 packages Vivado Tools 2015.1 v1.23 for FBVA676 and FFVA1156 packages N/A Vivado Tools 2015.3 v1.23 Vivado Tools 2015.3 v1.23 for FBVA900 N/A Vivado Tools 2015.4 v1.23 for SFVA784 N/A Vivado Tools 2015.4 v1.23 for SFVA784 XCKU060(2) Vivado Tools 2015.4 v1.23 Vivado Tools 2015.2 v1.23 N/A Vivado Tools 2015.3 v1.23 Vivado Tools 2015.4 v1.23 XCKU095 N/A Vivado Tools 2015.3 v1.24 N/A N/A N/A XCKU115 XQKU040 N/A Vivado Tools 2016.4 v1.23 N/A N/A XQKU060 N/A Vivado Tools 2016.4 v1.23 N/A N/A XQKU095 N/A Vivado Tools 2016.4 v1.24 N/A N/A XQKU115 N/A Vivado Tools 2016.4 v1.24 N/A N/A N/A Notes: 1. For designs developed using Vivado tools prior to 2016.4, see the design advisory answer record AR68169: Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs—New minimum production speed specification version (Speed File) required for all designs. 2. Designs with these devices that use th e dedicated System Monitor I2C (I2C_SCL and I2C_SDA) or PCIe reset (PERSTN0 or PERSTN1) I/O where the bank 65 VCCO = 3.3V must use Vivado Design Suite 2015.4 or later. 3. The lowest power -1L devices, where V CCINT = 0.90V, are listed in the Vivado Design Suite as -1LV. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 20 Performance Characteristics This section provides the performance characte ristics of some common functions and designs implemented in Kintex UltraScale FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics, page 17 . In each table, the I/O bank type is either high performance (HP) or high range (HR). Table 23: LVDS Component Mode Performance

Description

Speed Grade and VCCINT Operating Voltages Units 1.0V 0.95V 0.90V -3 -2 -1/-1L -1L Min Max Min Max Min Max Min Max LVDS TX DDR (OSERDES 4:1, 8:1) HP 0 1250 0 1250 0 1250 0 1250 Mb/s HR 0 1250 0 1250 0 1000 0 1000 Mb/s LVDS TX SDR (OSERDES 2:1, 4:1) H P 06 2 506 2 506 2 506 2 5 M b / s H R 06 2 506 2 505 0 005 0 0 M b / s LVDS RX DDR (ISERDES 1:4, 1:8)(1) HP 0 1250 0 1250 0 1250 0 1250 Mb/s HR 0 1250 0 1250 0 1000 0 1000 Mb/s LVDS RX SDR (ISERDES 1:2, 1:4)(1) H P 06 2 506 2 506 2 506 2 5 M b / s H R 06 2 506 2 505 0 005 0 0 M b / s Notes: 1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or phase-tracking algorithms are used to achieve maximum performance. Table 24: LVDS Native Mode Performance(1) Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1/-1L -1L Min Max Min Max Min Max Min Max LVDS TX DDR (TX_BITSLICE 4:1, 8:1) HP 300 1600 300 1600 300 1400 300 1400 Mb/s HR 300 1250 300 1250 300 1250 300 1250 Mb/s LVDS TX SDR (TX_BITSLICE 2:1, 4:1) HP 150 800 150 800 150 700 150 700 Mb/s HR 150 625 150 625 150 625 150 625 Mb/s LVDS RX DDR (RX_BITSLICE 1:4, 1:8)(2) HP 300 1600 300 1600 300 1400 300 1400 Mb/s HR 300 1250 300 1250 300 1250 300 1250 Mb/s LVDS RX SDR (RX_BITSLICE 1:2, 1:4)(2) HP 150 800 150 800 150 700 150 700 Mb/s HR 150 625 150 625 150 625 150 625 Mb/s Notes: 1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. 2. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) or phase-tracking algorithms are used to achieve maximum performance. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 21 Table 26 provides the maximum data rates for applicable memory standards using the Kintex UltraScale FPGAs memory PHY. Refer to Memory Interfaces for the complete list of memory interface standards supported and detailed specifications. The final perf ormance of the memory interface is determined through a complete design implemented in the Viva do Design Suite, following guidelines in the UltraScale Architecture PC B Design Guide (UG583 ), electrical analysis, and ch aracterization of the system. Table 25: LVDS Native-Mode 1000BASE-X Support(1) Description I/O Bank Type Speed Grade and VCCINT Operating Voltages 1.0V 0.95V 0.90V -3 -2 -1/-1L -1L 1000BASE-X HP Yes Yes Yes Yes Notes: 1. 1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE Std 802.3-2008). Table 26: Maximum Physical Interface (PHY) Rate for Memory Interfaces by I/O and Package Memory Standard I/O Bank Type Package DRAM Type Speed Grade, Temperature Ranges, and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3E -2E -2I -1C/I -1M -1LI -1LI DDR4 HP All FF/RF packages All FL packages FBVA900 Single rank component 2400 2400 2400 2133 2133 Mb/s 1 rank DIMM(1)(2) 2133 2133 2133 1866 1866 2 rank DIMM(1)(3) 1866 1866 1866 1600 1600 4 rank DIMM(1)(4) 1333 1333 1333 N/A N/A FBVA676 RBA676 SFVA784 Single rank component 2133 2133 2133 1866 1866 1 rank DIMM(1)(2) 1866 1866 1866 1600 1600 2 rank DIMM(1)(3) 1600 1600 1600 1333 1333 DDR3 HP All FF/RF packages All FL packages FBVA676 RBA676 FBVA900 Single rank component 2133 2133 2133 1866 1866 Mb/s 1 rank DIMM(1)(2) 1866 1866 1866 1600 1600 2 rank DIMM(1)(3) 1600 1600 1600 1333 1333 4 rank DIMM(1)(4) 1066 1066 1066 800 800 SFVA784 Single rank component 1866 1866 1866 1600 1600 1 rank DIMM(1)(2) 1600 1600 1600 1333 1333 2 rank DIMM(1)(3) 1333 1333 1333 1066 1066 4 rank DIMM(1)(4) 800 800 800 606 606 HR All Single rank component 1333(5) 1066 1066 Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 22 DDR3L HP All FF/RF packages All FL packages FBVA676 RBA676 FBVA900 Single rank component 1866 1866 1866 1600 1600 Mb/s 1 rank DIMM(1)(2) 1600 1600 1600 1333 1333 2 rank DIMM(1)(3) 1333 1333 1333 1066 1066 4 rank DIMM(1)(4) 800 800 800 606 606 SFVA784 Single rank component 1600 1600 1600 1600 1600 1 rank DIMM(1)(2) 1333 1333 1333 1333 1333 2 rank DIMM(1)(3) 1066 1066 1066 1066 1066 4 rank DIMM(1)(4) 606 606 606 606 606 HR All Single rank component 1066 1066 1066 800 800 QDR II+(6) All All Single rank component 633 600 600 550 550 MHz QDRIV-XP HP All Single rank component 800 800 800 667 667 RLDRAM III HP All FF/RF packages All FL packages FBVA676 RBA676 FBVA900 Single rank component 1066 1066 1066 933 933 SFVA784 933 933 933 800 800 LPDDR3 HP All Single rank component 1600 1600 1600 1600 1600 Mb/s HR All Single rank component 1066 1066 1066 1066 1066 Notes: 1. Dual in-line memory module (DIMM) incl udes RDIMM, SODIMM, UDIMM, and LRDIMM. 2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot. 3. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot. 4. Includes: 2 rank 2 slot, 4 rank 1 slot. 5. Memory device must be rated at 1600 or above. 6. The QDRII+ performance spec ifications are for burst-length 4 (BL = 4) implementations. Table 26: Maximum Physical Interface (PHY) Rate for Memory Interfaces by I/O and Package Memory Standard I/O Bank Type Package DRAM Type Speed Grade, Temperature Ranges, and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3E -2E -2I -1C/I -1M -1LI -1LI Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 23 IOB Pad Input, Output, and 3-State Table 27 (high-range IOB (HR)) and Table 28 (high-performance IOB (HP)) summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.

• TINBUF_DELAY_PAD_I is the delay from IOB pad through the inpu t buffer to the I-pin of an IOB pad. The delay varies depending on the capa bility of the SelectIO input buffer.
• TOUTBUF_DELAY_O_PAD is the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the ca pability of the SelectIO output buffer.
• TOUTBUF_DELAY_TD_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies de pending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI termi nation turn-on time is always faster than TOUTBUF_DELAY_TD_PAD when the DCITERMDISABLE pin is used. In HR I/O banks, the on-die termination turn-on time is always faster than T OUTBUF_DELAY_TD_PAD when the INTERMDISABLE pin is used. Table 27: IOB High Range (HR) Switching Characteristics I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD -3 -2 -1/ -1L -1M -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 24 Table 27: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD -3 -2 -1/ -1L -1M -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 25 Table 27: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD -3 -2 -1/ -1L -1M -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 26 Table 28: IOB High Performance (HP) Switching Characteristics I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD -3 -2 -1/ -1L -1M -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 27 Table 28: IOB High Performance (HP) Switching Characteristics (Cont’d) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD -3 -2 -1/ -1L -1M -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 28 Table 28: IOB High Performance (HP) Switching Characteristics (Cont’d) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD -3 -2 -1/ -1L -1M -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 29 Table 28: IOB High Performance (HP) Switching Characteristics (Cont’d) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD -3 -2 -1/ -1L -1M -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 30 Table 29 specifies the values of T OUTBUF_DELAY_TE_PAD and TINBUF_DELAY_IBUFDIS_O . TOUTBUF_DELAY_TE_PAD is the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). T INBUF_DELAY_IBUFDIS_O is the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination tu rn-off time is always faster than T OUTBUF_DELAY_TE_PAD when the DCITERMDISABLE pin is used. In HR I/O banks, the in ternal IN_TERM termination turn-off time is always faster than T OUTBUF_DELAY_TE_PAD when the INTERMDISABLE pin is used. Table 29: IOB 3-state Output Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1/-1L -1L TOUTBUF_DELAY_TE_PAD(1) T input to pad high-impedance for HR I/O banks 1.37 1.52 1.69 1.69 ns T input to pad high-impedance for HP I/O banks 0.62 0.71 0.78 0.78 ns TINBUF_DELAY_IBUFDIS_O IBUF turn-on time from IBUFDISABLE to O output for HR I/O banks 0.47 0.65 0.68 0.68 ns IBUF turn-on time from IBUFDISABLE to O output for HP I/O banks 1.06 1.21 1.49 1.49 ns Notes: 1. The T OUTBUF_DELAY_TE_PAD values are applicable to single-ended I/O standards. For true differential standards, the values are larger. Use the Vivado timing report for the most accurate timing values for your configuration. Table 28: IOB High Performance (HP) Switching Characteristics (Cont’d) I/O Standards TINBUF_DELAY_PAD_I TOUTBUF_DELAY_O_PAD TOUTBUF_DELAY_TD_PAD -3 -2 -1/ -1L -1M -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 31 I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 30 shows the test setup parameters used for measuring input delay. Table 30: Input Delay Measurement Methodology Description I/O Standard Attribute VL(1)(2) VH(1)(2) VMEAS(1)(4)(6) VREF(1)(3)(5) LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 – LVCMOS, LVDCI, HSLVDCI, 1.5V LVCMOS15, LVDCI_15, HSLVDCI_15 0.1 1.4 0.75 – LVCMOS, LVDCI, HSLVDCI, 1.8V LVCMOS18, LVDCI_18, HSLVDCI_18 0.1 1.7 0.9 – LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 – LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 – LVTTL, 3.3V LVTTL 0.1 3.2 1.65 – HSTL (high-speed transceiver logic), Class I, 1.2V HSTL_I_12 VREF –0 . 5 VREF +0 . 5 VREF 0.60 HSTL, Class I and II, 1.5V HSTL_I, HSTL_II VREF –0 . 6 5 VREF +0 . 6 5 VREF 0.75 HSTL, Class I and II, 1.8V HSTL_I_18, HSTL_II_18 VREF –0 . 8 VREF +0 . 8 VREF 0.90 HSUL (high-speed unterminated logic), 1.2V HSUL_12 VREF –0 . 5 VREF +0 . 5 VREF 0.60 SSTL (stub series terminated logic), 1.2V SSTL12 VREF –0 . 5 VREF +0 . 5 VREF 0.60 SSTL, 1.35V SSTL135, SSTL135_R VREF – 0.575 VREF +0 . 5 7 5 VREF 0.675 SSTL, 1.5V SSTL15, SSTL15_R VREF –0 . 6 5 VREF +0 . 6 5 VREF 0.75 SSTL, Class I and II, 1.8V SSTL18_I, SSTL18_II VREF –0 . 8 VREF +0 . 8 VREF 0.90 POD10, 1.0V POD10 VREF –0 . 6 VREF +0 . 6 VREF 0.70 POD12, 1.2V POD12 V REF –0 . 7 4 VREF +0 . 7 4 VREF 0.84 DIFF_HSTL, Class I and II,1.5V DIFF_HSTL_I, DIFF_HSTL_II 0.75 – 0.125 0.75 + 0.125 0(6) – DIFF_HSTL, Class I and II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 0.675 – 0.125 0.675 + 0.125 0(6) – DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 32 LVDS (low-voltage differential signaling), PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0(6) – RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0(6) – TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0(6) – Notes: 1. The input delay measuremen t methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI standards are the same for the corresponding non-DCI standards. 2. Input waveform switches between V Land VH. 3. Measurements are made at typical, minimum, and maximum V REF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 4. Input voltage level from which measurement starts. 5. This is an input voltage referenc e that bears no relation to the VREF/VMEAS parameters found in IBIS models and/or noted in Figure 1. 6. The value given is the differential input voltage. Table 30: Input Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute VL(1)(2) VH(1)(2) VMEAS(1)(4)(6) VREF(1)(3)(5) Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 34 Table 31: Output Delay Measurement Methodology Description I/O Standard Attribute RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0 LVCMOS 1.5V LVCMOS15 1M 0 0.75 0 LVCMOS 1.8V LVCMOS18 1M 0 0.9 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0 LVTTL, 3.3V LVTTL 1M 0 1.65 0 LVDCI/HSLVDCI, 1.5V LVDCI_15, HSLVDCI_15 50 0 VREF 0.75 LVDCI/HSLVDCI, 1.8V LVDCI_18, HSLVDCI_18 50 0 VREF 0.9 HSTL (high-speed transceiver logic), Class I, 1.2V HSTL_I_12 50 0 VREF 0.6 HSTL, Class I, 1.5V HSTL_I 50 0 VREF 0.75 HSTL, Class II, 1.5V HSTL_II 25 0 VREF 0.75 HSTL, Class I, 1.8V HSTL_I_18 50 0 VREF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 VREF 0.9 HSUL (high-speed unterminated logic), 1.2V HSUL_12 50 0 VREF 0.6 SSTL12, 1.2V SSTL12 50 0 VREF 0.6 SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 VREF 0.675 SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 VREF 0.75 SSTL (stub series terminated logic), Class I and Class II, 1.8V SSTL18_I, SSTL18_II 50 0 VREF 0.9 POD10, 1.0V POD10 50 0 VREF 1.0 POD12, 1.2V POD12 50 0 VREF 1.2 DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 VREF 0.6 DIFF_HSTL, Class I and II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 VREF 0.75 DIFF_HSTL, Class I and II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 VREF 0.9 DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 VREF 0.6 DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 VREF 0.6 DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 VREF 0.675 DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 VREF 0.75 DIFF_SSTL18, Class I and II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 VREF 0.9 DIFF_POD10, 1.0V DIFF_POD10 50 0 VREF 1.0 DIFF_POD12, 1.2V DIFF_POD12 50 0 VREF 1.2 LVDS (low-voltage differential signaling), 1.8V LVDS 100 0 0(2) 0 LVDS, 2.5V LVDS_25 100 0 0(2) 0 BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0(2) 0 Mini LVDS, 2.5V MINI_LVDS_25 100 0 0(2) 0 PPDS_25 PPDS_25 100 0 0(2) 0 RSDS_25 RSDS_25 100 0 0(2) 0 Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 35 Block RAM and FIFO Switching Characteristics SUB_LVDS SUB_LVDS 100 0 0(2) 0 TMDS_33 TMDS_33 50 0 0(2) 3.3 Notes: 1. C REF is the capacitance of the probe, nominally 0 pF. 2. The value given is the differential output voltage. Table 32: Block RAM and FIFO Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1/-1L -1L Maximum Frequency FMAX_WF_NC Block RAM (Write First and No Change modes) 660 585 525 525 MHz FMAX_RF Block RAM (Read First mode) 575 510 460 400 MHz FMAX_FIFO FIFO in all modes without ECC 660 585 525 525 MHz FMAX_ECC Block RAM and FIFO in ECC configuration without PIPELINE 530 450 390 390 MHz Block RAM and FIFO in ECC configuration with PIPELINE and Block RAM in Write First or No Change mode. 660 585 525 525 MHz Block RAM in ECC configuration in Read First mode with PIPELINE 575 510 460 400 MHz F MAX_ADDREN_RDADDRCHANGE Block RAM with address enable and read address change compare turned on. 575 510 460 400 MHz TPW_WF_NC(1) Block RAM in WRITE_FIRST and NO_CHANGE modes and FIFO. Clock High/Low pulse width 758 855 952 952 ps, Min T PW_RF(1) Block RAM in READ_FIRST modes. Clock High/Low pulse width 870 980 1087 1250 ps, Min Block RAM and FIFO Clock-to-Out Delays TRCKO_DO Clock CLK to DOUT output (without output register) 1.13 1.44 1.64 1.64 ns, Max TRCKO_DO_REG Clock CLK to DOUT output (with output register) 0.37 0.44 0.49 0.49 ns, Max Notes: 1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse width requirements at the higher frequencies. Table 31: Output Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 36 Input/Output Delay Switching Characteristics DSP48 Slice Switching Characteristics Table 33: Input/Output Delay Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1/-1L -1L FREFCLK REFCLK frequency for IDELAYCTRL (component mode). 200 to 800 MHz REFCLK frequency for IDELAYCTRL (native mode).(1) 200 to 2400 200 to 2400 200 to 2133 200 to 2133 MHz TMINPER_RST Minimum reset pulse width. 52.00 ns TIDELAY_RESOLUTION/ TODELAY_RESOLUTION IDELAY/ODELAY chain resolution. 2.5 to 15 ps Notes: 1. PLL settings could restrict the minimum allowable data rate. For example, when using a PLL with CLKOUTPHY_MODE = VCO_HALF, the minimum frequency is PLL_FVCOMIN/2. Table 34: DSP48 Slice Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1/-1L -1L Maximum Frequency FMAX With all registers used 741 661 594 594 MHz FMAX_PATDET With pattern detector 687 581 512 512 MHz FMAX_MULT_NOMREG Two register multiply without MREG 462 429 361 361 MHz FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect 428 387 326 326 MHz FMAX_PREADD_NOADREG Without ADREG 468 429 358 358 MHz FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG) 335 312 260 260 MHz FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect 316 286 238 238 MHz Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 37 Clock Buffers and Networks Table 35: Clock Buffers Switching Characteristics Symbol Description Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1/-1L -1L Global Clock Switching Characteristics (Including BUFGCTRL) FMAX Maximum frequency of a global clock tree (BUFG) 850 725 630 630 MHz Global Clock Buffer with Input Divide Capability (BUFGCE_DIV) FMAX Maximum frequency of a global clock buffer with input divide capability (BUFGCE_DIV) 850 725 630 630 MHz Global Clock Buffer with Clock Enable (BUFGCE) FMAX Maximum frequency of a global clock buffer with clock enable (BUFGCE) 850 725 630 630 MHz Leaf Clock Buffer with Clock Enable (BUFCE_LEAF) FMAX Maximum frequency of a leaf clock buffer with clock enable (BUFCE_LEAF) 850 725 630 630 MHz GTH/GTY Clock Buffer with Clock Enable and Clock Input Divide Capability (BUFG_GT) FMAX Maximum frequency of a serial transceiver clock buffer with clock enable and clock input divide capability 512 512 512 512 MHz Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 38 MMCM Switching Characteristics Table 36: MMCM Specification Symbol Description Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1/-1L -1L MMCM_FINMAX Maximum input clock frequency 1066 933 800 800 MHz MMCM_FINMIN Minimum input clock frequency 10 10 10 10 MHz MMCM_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max MMCM_FINDUTY Input duty cycle range: 10–49 MHz 25–75 % Input duty cycle range: 50–199 MHz 30–70 % Input duty cycle range: 200–399 MHz 35–65 % Input duty cycle range: 400–499 MHz 40–60 % Input duty cycle range: >500 MHz 45–55 % MMCM_F MIN_PSCLK Minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 MHz MMCM_FMAX_PSCLK Maximum dynamic phase shift clock frequency 550 500 450 450 MHz MMCM_FVCOMIN Minimum MMCM VCO frequency 600 600 600 600 MHz MMCM_FVCOMAX Maximum MMCM VCO frequency 1600 1440 1200 1200 MHz MMCM_FBANDWIDTH Low MMCM bandwidth at typical(1) 1.00 1.00 1.00 1.00 MHz High MMCM bandwidth at typical(1) 4.00 4.00 4.00 4.00 MHz MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs(2) 0.12 0.12 0.12 0.12 ns MMCM_TOUTJITTER MMCM output jitter Note 3 MMCM_TOUTDUTY MMCM output clock duty cycle precision(4) 0.165 0.20 0.20 0.20 ns MMCM_TLOCKMAX MMCM maximum lock time for MMCM_FPFDMIN frequencies above 20 MHz 100 100 100 100 µs MMCM maximum lock time for MMCM_FPFDMIN frequencies from 10 MHz to 20 MHz 200 200 200 200 µs MMCM_FOUTMAX MMCM maximum output frequency 850 725 630 630 MHz MMCM_FOUTMIN MMCM minimum output frequency(4)(5) 4.69 4.69 4.69 4.69 MHz MMCM_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max MMCM_RSTMINPULSE Minimum reset pulse width 5.00 5.00 5.00 5.00 ns MMCM_FPFDMAX Maximum frequency at the phase frequency detector 550 500 450 450 MHz MMCM_FPFDMIN Minimum frequency at the phase frequency detector 10 10 10 10 MHz MMCM_TFBDELAY Maximum delay in the feedback path 5 ns Max or one clock cycle MMCM_FDRPCLK_MAX Maximum DRP clock frequency 200 200 200 200 MHz Notes: 1. The MMCM does not filter typical spread-spectrum input cloc ks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any MMCM outputs with identical phase. 3. Values for this parameter are av ailable in the Clocking Wizard. 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 39 PLL Switching Characteristics Table 37: PLL Specification(1) Symbol Description Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1/-1L -1L PLL_FINMAX Maximum input clock frequency 1066 933 800 800 MHz PLL_FINMIN M i n i m u m i n p u t c l o c k f r e q u e n c y 7 07 07 07 0 M H z PLL_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max PLL_FINDUTY Input duty cycle range: 70–399 MHz 35–65 % Input duty cycle range: 400–499 MHz 40–60 % Input duty cycle range: >500 MHz 45–55 % PLL_F VCOMIN Minimum PLL VCO frequency 600 600 600 600 MHz PLL_FVCOMAX Maximum PLL VCO frequency 1335 1335 1200 1200 MHz PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs(2) 0.12 0.12 0.12 0.12 ns PLL_TOUTJITTER PLL output jitter Note 3 PLL_TOUTDUTY PLL CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B duty-cycle precision(4) 0 . 1 6 5 0 . 2 00 . 2 00 . 2 0 n s PLL_TLOCKMAX PLL maximum lock time 100 µs PLL_FOUTMAX PLL maximum output frequency at CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B 850 725 630 630 MHz PLL maximum output frequency at CLKOUTPHY 2670 2670 2400 2400 MHz PLL_FOUTMIN PLL minimum output frequency at CLKOUT0/CLKOUT0B/CLKOUT1/CLKOUT1B(5) 4.69 4.69 4.69 4.69 MHz PLL minimum output frequency at CLKOUTPHY 2 x VCO mode: 1200 1 x VCO mode: 600 0.5 x VCO mode: 300 MHz PLL_RSTMINPULSE M i n i m u m r e s e t p u l s e w i d t h 5 . 0 05 . 0 05 . 0 05 . 0 0 n s PLL_FPFDMAX Maximum frequency at the phase frequency detector 667.5 667.5 600 600 MHz PLL_FPFDMIN Minimum frequency at the phase frequency detector 70 70 70 70 MHz PLL_FBANDWIDTH P L L b a n d w i d t h a t t y p i c a l 1 51 51 51 5 M H z PLL_FDRPCLK_MAX Maximum DRP clock frequency 200 200 200 200 MHz Notes: 1. The PLL does not filter typical spread-s pectrum input clocks because they are usually far below the loop filter frequencies. 2. The static offset is measured betwee n any PLL outputs with identical phase. 3. Values for this parameter are av ailable in the Clocking Wizard. 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 40 Device Pin-to-Pin Output Parameter Guidelines The pin-to-pin numbers in Table 38 through Table 41 are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values. Table 38: Global Clock Input to Output Delay Without MMCM/PLL (Near Clock Region) Symbol Description Device Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOF Global clock input and output flip-flop without MMCM/PLL (near clock region) XCKU025 N/A 6.07 7.00 N/A N/A ns XCKU095 N/A 6.09 7.13 N/A N/A ns XQKU040 N/A 6.21 7.17 N/A N/A ns XQKU060 N/A 5.99 6.93 N/A N/A ns XQKU095 N/A 6.09 7.13 N/A N/A ns XQKU115 N/A 6.08 7.08 N/A N/A ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 41 Table 39: Global Clock Input to Output Delay Without MMCM/PLL (Far Clock Region) Symbol Description Device Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOF_FAR Global clock input and output flip-flop without MMCM/PLL (far clock region) XCKU025 N/A 6.40 7.37 N/A N/A ns XCKU095 N/A 6.67 7.69 N/A N/A ns XQKU040 N/A 6.73 7.75 N/A N/A ns XQKU060 N/A 6.84 7.91 N/A N/A ns XQKU095 N/A 6.67 7.69 N/A N/A ns XQKU115 N/A 6.98 8.12 N/A N/A ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. Table 40: Global Clock Input to Output Delay With MMCM Symbol Description Device Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. TICKOFMMCMCC Global clock input and output flip-flop with MMCM XCKU025 N/A 1.80 1.88 N/A N/A ns XCKU095 N/A 1.59 1.85 N/A N/A ns XQKU040 N/A 1.81 1.91 N/A N/A ns XQKU060 N/A 1.92 2.05 N/A N/A ns XQKU095 N/A 1.59 1.85 N/A N/A ns XQKU115 N/A 1.95 2.12 N/A N/A ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. 2. MMCM output jitter is already included in the timing calculation. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 42 Table 41: Global Clock Input to Output Delay With PLL Symbol Description Device Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. TICKOF_PLL_CC Global clock input and output flip-flop with PLL XCKU025 N/A 5.39 6.11 N/A N/A ns XCKU095 N/A 5.70 6.49 N/A N/A ns XQKU040 N/A 5.72 6.50 N/A N/A ns XQKU060 N/A 5.83 6.66 N/A N/A ns XQKU095 N/A 5.70 6.49 N/A N/A ns XQKU115 N/A 5.96 6.85 N/A N/A ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. 2. PLL output jitter is already included in the timing calculation. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 43 Device Pin-to-Pin Input Parameter Guidelines The pin-to-pin numbers in Table 42 through Table 43 are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values. Table 42: Global Clock Input Setup and Hold With MMCM Symbol Description Device Speed Grade, VCCINT Operating Voltage, and Temperature Range Units1.0V 0.95V 0.90V -3E -2E/I -1C/I -1M -1LI -1LI Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.(1)(2)(3) TPSMMCMCC_KU025 Global clock input and input flip-flop (or latch) with MMCM Setup XCKU025 N/A 2.16 2.51 N/A N/A N/A ns T PHMMCMCC_KU025 Hold N/A –0.48 –0.48 N/A N/A N/A ns TPSMMCMCC_KU035 Setup XCKU035 TPSMMCMCC_KU040 Setup XCKU040 TPSMMCMCC_KU060 Setup XCKU060 TPSMMCMCC_KU085 Setup XCKU085 TPSMMCMCC_KU095 Setup XCKU095 N/A 2.25 2.55 N/A N/A N/A ns TPHMMCMCC_KU095 Hold N/A –0.47 –0.47 N/A N/A N/A ns TPSMMCMCC_KU115 Setup XCKU115 TPSMMCMCC_KU040 Setup XQKU040 N/A 2.23 2.58 2.60 N/A N/A ns TPHMMCMCC_KU040 Hold N/A –0.45 –0.45 –0.45 N/A N/A ns TPSMMCMCC_KU060 Setup XQKU060 N/A 2.23 2.51 2.52 N/A N/A ns TPHMMCMCC_KU060 Hold N/A –0.47 –0.47 –0.47 N/A N/A ns TPSMMCMCC_KU095 Setup XQKU095 N/A 2.25 2.55 2.56 N/A N/A ns TPHMMCMCC_KU095 Hold N/A –0.47 –0.47 –0.47 N/A N/A ns TPSMMCMCC_KU115 Setup XQKU115 N/A 2.23 2.51 N/A N/A N/A ns TPHMMCMCC_KU115 Hold N/A –0.37 –0.37 N/A N/A N/A ns Notes: 1. Setup and hold times are measured over worst case conditio ns (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage. 2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. 3. Use IBIS to determine any duty-cycle di stortion incurred using various standards. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 44 Table 43: Global Clock Input Setup and Hold With PLL Symbol Description Device Speed Grade, VCCINT Operating Voltage, and Temperature Range Units1.0V 0.95V 0.90V Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard.(1)(2)(3) TPSPLLCC_KU025 Global clock input and input flip-flop (or latch) with PLL Setup XCKU025 N/A –0.48 –0.48 N/A N/A N/A ns T PHPLLCC_KU025 Hold N/A 2.42 2.70 N/A N/A N/A ns TPSPLLCC_KU035 Setup XCKU035 TPSPLLCC_KU040 Setup XCKU040 TPSPLLCC_KU060 Setup XCKU060 TPSPLLCC_KU085 Setup XCKU085 TPSPLLCC_KU095 Setup XCKU095 N/A –0.94 –0.94 N/A N/A N/A ns TPHPLLCC_KU095 Hold N/A 2.36 2.71 N/A N/A N/A ns TPSPLLCC_KU115 Setup XCKU115 TPSPLLCC_KU040 Setup XQKU040 N/A –0.67 –0.67 –0.67 N/A N/A ns TPHPLLCC_KU040 Hold N/A 2.48 2.83 2.84 N/A N/A ns TPSPLLCC_KU060 Setup XQKU060 N/A –0.70 –0.70 –0.70 N/A N/A ns TPHPLLCC_KU060 Hold N/A 2.41 2.75 2.75 N/A N/A ns TPSPLLCC_KU095 Setup XQKU095 N/A –0.94 –0.94 –0.94 N/A N/A ns TPHPLLCC_KU095 Hold N/A 2.36 2.71 2.71 N/A N/A ns TPSPLLCC_KU115 Setup XQKU115 N/A –0.66 –0.66 N/A N/A N/A ns TPHPLLCC_KU115 Hold N/A 2.46 2.83 N/A N/A N/A ns Notes: 1. Setup and hold times are measured over worst case conditio ns (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage. 2. This table lists representative values where one global clock in put drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR. 3. Use IBIS to determine any duty-cycle di stortion incurred using various standards. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 45 Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for clock transmitter and receiver data-valid windows. Table 44: Sampling Window Speed Grade and VCCINT Operating Voltages Units1.0V 0.95V 0.90V TSAMP_BUFG(1) 510 560 610 610 610 610 ps TSAMP_NATIVE_DPA 100 100 100 125 125 150 ps TSAMP_NATIVE_BISC 60 60 60 85 85 110 ps Notes: 1. This parameter indicates the total sampling error of the Ki ntex UltraScale FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew. Table 45: Package Skew Symbol Description Device Package Value Units XCKU025 FFVA1156 162 ps XCKU035 FBVA676 173 ps SFVA784 134 ps FBVA900 184 ps FFVA1156 168 ps XCKU040 FBVA676 173 ps SFVA784 134 ps FBVA900 184 ps FFVA1156 168 ps XCKU060 FFVA1156 168 ps FFVA1517 169 ps XCKU085 FLVA1517 217 ps FLVB1760 175 ps FLVF1924 143 ps XCKU095 FFVA1156 162 ps FFVC1517 181 ps FFVB1760 128 ps FFVB2104 191 ps Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 46 PKGSKEW (cont’d) Package Skew XCKU115 FLVA1517 217 ps FLVD1517 143 ps FLVB1760 177 ps FLVD1924 172 ps FLVF1924 143 ps FLVA2104 184 ps FLVB2104 198 ps XQKU040 RBA676 178 ps RFA1156 164 ps XQKU060 RFA1156 170 ps XQKU095 RFA1156 163 ps XQKU115 RLD1517 147 ps RLF1924 146 ps Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. 2. Package delay information is available for these device/package combinations. This information can be used to deskew the package. Table 45: Package Skew (Cont’d) Symbol Description Device Package Value Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 47 GTH Transceiver Specifications GTH Transceiver DC Input and Output Levels Table 46 summarizes the DC specifications of the GTH transc eivers in Kintex UltraSca le FPGAs. Consult the UltraScale Architecture GT H Transceiver User Guide (UG576 ) for further details. Table 46: GTH Transceiver DC Specifications Symbol DC Parameter Conditions Min Typ Max Units DVPPIN Differential peak-to-peak input voltage (external AC coupled) >10.3125 Gb/s 150 – 1250 mV 6.6 Gb/s to 10.3125 Gb/s 150 – 1250 mV ≤ 6.6 Gb/s 150 – 2000 mV V IN Single-ended input voltage. Voltage measured at the pin referenced to GND. DC coupled V MGTAVTT =1 . 2 V –400 – V MGTAVTT mV VCMIN Common mode input voltage DC coupled VMGTAVTT =1 . 2 V –2 / 3 V MGTAVTT –m V DVPPOUT Differential peak-to-peak output voltage(1) Transmitter output swing is set to 1100 800 – – mV V CMOUTDC Common mode output voltage: DC coupled (equation based) When remote RX is terminated to GND VMGTAVTT/2 – DVPPOUT/4 mV When remote RX termination is floating VMGTAVTT – DVPPOUT/2 mV When remote RX is terminated to VRX_TERM(2) mV VCMOUTAC Common mode output voltage: AC coupled (equation based) V MGTAVTT – DVPPOUT/2 mV RIN Differential input resistance – 100 – Ω ROUT Differential output resistance – 100 – Ω TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew (All packages) –– 1 0 p s CEXT Recommended external AC coupling capacitor(3) – 100 – nF Notes: 1. The output swing and pre-emphas is levels are programmable using the attributes discussed in the UltraScale Architecture GTH Transceiver User Guide (UG576), and can result in values lower than reported in this table. 2. V RX_TERM is the remote RX termination voltage. 3. Other values can be used as appropriate to conform to specific protocols and standards. VMGTAVTT DVPPOUT VMGTAVTT VRX_TERM– – Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 49 GTH Transceiver Switching Characteristics Consult the UltraScale Architecture GT H Transceiver User Guide (UG576 ) for further information. Table 49: GTH Transceiver Performance Symbol Description Output Divider Speed Grade, Temperature Ranges, and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -1LI -1LI Package Type FF/FL FB/SF FF/FL RF FB/SF RB All Packages All Packages Min Max Min Max Min Max Min Max FGTHCRANGE CPLL line rate range(2)

16 N/A Gb/s

Min Max Min Max Min Max Min Max FGTHQRANGE1 QPLL0 line rate range(3) Min Max Min Max Min Max Min Max FGTHQRANGE2 QPLL1 line rate range(4) Min Max Min Max Min Max Min Max Notes: 2. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider. 3. The values listed are the rounded results of the ca lculated equation (QPLL0_Frequency)/Output_Divider. 4. The values listed are the rounded results of the ca lculated equation (QPLL1_Frequency)/Output_Divider. Table 50: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Symbol Description All Devices Units FGTHDRPCLK GTHDRPCLK maximum frequency 250 MHz Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 50 Table 51: GTH Transceiver Reference Clock Switching Characteristics Symbol Description Conditions Min Typ Max Units FGCLK Reference clock frequency range 60 – 820 MHz TRCLK Reference clock rise time 20% – 80% – 200 – ps TFCLK Reference clock fall time 80% – 20% – 200 – ps TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 % X-Ref Target - Figure 5 Figure 5: Reference Clock Timing Parameters Table 52: GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask Symbol Description Offset Frequency Min Typ Max Units QPLLREFCLKMASK(1)(2) QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz. 10 kHz – – –105 dBc/Hz100 kHz – – –124

1 MHz – – –130

REFCLKMASK(1)(2) CPLL reference clock select phase noise mask at REFCLK frequency = 312.5 MHz. 10 kHz – – –105 dBc/Hz 100 kHz – – –124

50 MHz – – –140

Notes: 1. For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 x Log(N/312.5) where N is the new reference clock frequency in MHz. 2. This reference clock phase-noise mask is superseded by an y reference clock phase-noise mask that is specified in a supported protocol, e.g., PCIe. Table 53: GTH Transceiver PLL/Lock Time Adaptation Symbol Description Conditions Min Typ Max Units TLOCK Initial PLL lock – – 1 ms TDLOCK Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE). After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. – 50,000 37 x 10 6 UI Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled. –5 0 , 0 0 0 2 . 3 x 1 0 6 UI ds892_05_120414 80% 20% TFCLK TRCLK Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 51 Table 54: GTH Transceiver User Clock Switching Characteristics(1) Symbol Description Data Width Conditions (Bit) Speed Grade, Temperature Ranges, and VCCINT Operating Voltages Units1.0V 0.95V 0.90V Internal Logic Interconnect Logic -3E -2E, -2I -1C, -1I, -1M, -1LI -1LI FTXOUTPMA TXOUTCLK maximum frequency sourced from OUTCLKPMA 511.719 511.719 390.625 390.625 MHz FRXOUTPMA RXOUTCLK maximum frequency sourced from OUTCLKPMA 511.719 511.719 390.625 390.625 MHz FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from TXPROGDIVCLK 511.719 511.719 511.719 511.719 MHz FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from RXPROGDIVCLK 511.719 511.719 511.719 511.719 MHz FTXIN TXUSRCLK maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 MHz 32 32, 64 511.719 511.719 390.625 390.625 MHz 20 20, 40 409.375 409.375 312.500 312.500 MHz 40 40, 80 409.375 409.375 312.500 312.500 MHz F RXIN RXUSRCLK maximum frequency 16 16, 32 511.719 511.719 390.625 390.625 MHz 32 32, 64 511.719 511.719 390.625 390.625 MHz 20 20, 40 409.375 409.375 312.500 312.500 MHz 40 40, 80 409.375 409.375 312.500 312.500 MHz F TXIN2 TXUSRCLK2 maximum frequency 16 16 511.719 511.719 390.625 390.625 MHz 16, 32 32 511.719 511.719 390.625 390.625 MHz 32 64 255.860 255.860 195.313 195.313 MHz 20 20 409.375 409.375 312.500 312.500 MHz 20, 40 40 409.375 409.375 312.500 312.500 MHz 40 80 204.688 204.688 156.250 156.250 MHz F RXIN2 RXUSRCLK2 maximum frequency 16 16 511.719 511.719 390.625 390.625 MHz 16, 32 32 511.719 511.719 390.625 390.625 MHz 32 64 255.860 255.860 195.313 195.313 MHz 20 20 409.375 409.375 312.500 312.500 MHz 20, 40 40 409.375 409.375 312.500 312.500 MHz 40 80 204.688 204.688 156.250 156.250 MHz Notes: 1. Clocking must be implemented as described in UltraScale Architecture GTH Transceiver User Guide (UG576). Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 52 Table 55: GTH Transceiver Transmitter Switching Characteristics Symbol Description Condition Min Typ Max Units FGTHTX Serial data rate range 0.500 – F GTHMAX Gb/s TRTX TX rise time 20%–80% – 40 – ps TFTX TX fall time 80%–20% – 40 – ps TLLSKEW TX lane-to-lane skew(1) –– 5 0 0 p s TJ16.3_QPLL Total jitter(2)(4)

16.3 Gb/s

– – 0.28 UI DJ16.3_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ15_QPLL Total jitter(2)(4)

15.0 Gb/s

– – 0.28 UI DJ15_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ14.1_QPLL Total jitter(2)(4)

14.1 Gb/s

– – 0.28 UI DJ14.1_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ14.025_QPLL Total jitter(2)(4)

14.025 Gb/s

– – 0.28 UI DJ14.025_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ13.1_QPLL Total jitter(2)(4)

13.1 Gb/s

– – 0.28 UI DJ13.1_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ12.5_QPLL Total jitter(2)(4)

12.5 Gb/s

– – 0.28 UI DJ12.5_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ12.5_CPLL Total jitter(3)(4) – – 0.33 UI DJ12.5_CPLL Deterministic jitter(3)(4) – – 0.17 UI TJ11.3_QPLL Total jitter(2)(4)

11.3 Gb/s

– – 0.28 UI DJ11.3_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ10.3_QPLL Total jitter(2)(4)

10.3 Gb/s

– – 0.28 UI DJ10.3_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ10.3_CPLL Total jitter(3)(4) – – 0.33 UI DJ10.3_CPLL Deterministic jitter(3)(4) – – 0.17 UI TJ9.8_QPLL Total jitter(2)(4)

9.8 Gb/s

– – 0.28 UI DJ9.8_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ9.8_CPLL Total jitter(3)(4) – – 0.28 UI DJ9.8_CPLL Deterministic jitter(3)(4) – – 0.17 UI TJ8.0_CPLL Total jitter(3)(4)

8.0 Gb/s

– – 0.32 UI DJ8.0_CPLL Deterministic jitter(3)(4) – – 0.17 UI TJ6.6_CPLL Total jitter(3)(4)

6.6 Gb/s

– – 0.30 UI DJ6.6_CPLL Deterministic jitter(3)(4) – – 0.15 UI TJ5.0 Total jitter(3)(4)

5.0 Gb/s

– – 0.30 UI DJ5.0 Deterministic jitter(3)(4) – – 0.15 UI TJ4.25 Total jitter(3)(4)

4.25 Gb/s

– – 0.30 UI DJ4.25 Deterministic jitter(3)(4) – – 0.15 UI TJ4.0L Total jitter(3)(4) DJ4.0L Deterministic jitter(3)(4) – – 0.16 UI Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 53 TJ3.2 Total jitter(3)(4) DJ3.2 Deterministic jitter(3)(4) – – 0.10 UI TJ2.5 Total jitter(3)(4) DJ2.5 Deterministic jitter(3)(4) – – 0.10 UI TJ1.25 Total jitter(3)(4) DJ1.25 Deterministic jitter(3)(4) – – 0.06 UI TJ500 Total jitter(3)(4) DJ500 Deterministic jitter(3)(4) – – 0.03 UI Notes: 1. Using same REFCLK input with TX phase alignment enabled for up to four fully populated GTH Quads at maximum line rate. 2. Using QPLL_FBDIV = 40, 40-bit internal data width. These va lues are NOT intended for protocol specific compliance determinations. 3. Using CPLL_FBDIV = 2, 40-bit internal da ta width. These values are NOT intended for protocol specific compliance determinations. 4. All jitter values are based on a bit-error ratio of 10 -12. 5. CPLL frequency at 2.0 GHz and TXOUT_DIV = 1 6. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. 7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. 8. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4. 9. CPLL frequency at 2.0 GHz and TXOUT_DIV = 4. Table 56: GTH Transceiver Receiver Switching Characteristics Symbol Description Condition Min Typ Max Units FGTHRX Serial data rate 0.500 – F GTHMAX Gb/s TRXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data –1 0– n s RXOOBVDPP OOB detect threshold peak-to-peak 60 – 150 mV RXSST Receiver spread-spectrum tracking(1) Modulated at 33 kHz –5000 – 0 ppm RXRL Run length (CID) – – 256 UI RXPPMTOL Data/REFCLK PPM offset tolerance Bit rates ≤ 6.6 Gb/s –1250 – 1250 ppm Bit rates > 6.6 Gb/s and ≤ 8.0 Gb/s –700 – 700 ppm Bit rates > 8.0 Gb/s –200 – 200 ppm SJ Jitter Tolerance(2) JT_SJ16.3 Sinusoidal jitter (QPLL)(3) 16.3 Gb/s 0.30 – – UI JT_SJ15 Sinusoidal jitter (QPLL)(3) 15.0 Gb/s 0.30 – – UI JT_SJ14.1 Sinusoidal jitter (QPLL)(3) 14.1 Gb/s 0.30 – – UI JT_SJ13.1 Sinusoidal jitter (QPLL)(3) 13.1 Gb/s 0.30 – – UI JT_SJ12.5 Sinusoidal jitter (QPLL)(3) 12.5 Gb/s 0.30 – – UI JT_SJ11.3 Sinusoidal jitter (QPLL)(3) 11.3 Gb/s 0.30 – – UI JT_SJ10.3_QPLL Sinusoidal jitter (QPLL)(3) 10.3 Gb/s 0.30 – – UI JT_SJ10.3_CPLL Sinusoidal jitter (CPLL)(3) 10.3 Gb/s 0.30 – – UI JT_SJ9.8 Sinusoidal jitter (QPLL)(3) 9.8 Gb/s 0.30 – – UI JT_SJ8.0_QPLL Sinusoidal jitter (QPLL)(3) 8.0 Gb/s 0.44 – – UI Table 55: GTH Transceiver Transmitter Switching Characteristics (Cont’d) Symbol Description Condition Min Typ Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 54 JT_SJ8.0_CPLL Sinusoidal jitter (CPLL)(3) 8.0 Gb/s 0.42 – – UI JT_SJ6.6_CPLL Sinusoidal jitter (CPLL)(3) 6.6 Gb/s 0.44 – – UI JT_SJ5.0 Sinusoidal jitter (CPLL)(3) 5.0 Gb/s 0.44 – – UI JT_SJ4.25 Sinusoidal jitter (CPLL)(3) 4.25 Gb/s 0.44 – – UI JT_SJ4.0L Sinusoidal jitter (CPLL)(3) 4.0 Gb/s(4) 0.45 – – UI JT_SJ3.75 Sinusoidal jitter (CPLL)(3) 3.75 Gb/s 0.44 – – UI JT_SJ3.2 Sinusoidal jitter (CPLL)(3) 3.2 Gb/s(5) 0.45 – – UI JT_SJ2.5 Sinusoidal jitter (CPLL)(3) 2.5 Gb/s(6) 0.50 – – UI JT_SJ1.25 Sinusoidal jitter (CPLL)(3) 1.25 Gb/s(7) 0.50 – – UI JT_SJ500 Sinusoidal jitter (CPLL)(3) 500 Mb/s 0.40 – – UI SJ Jitter Tolerance with Stressed Eye(2) JT_TJSE3.2 Total jitter with stressed eye(8) 3.2 Gb/s 0.70 – – UI JT_TJSE6.6 6.6 Gb/s 0.70 – – UI JT_SJSE3.2 Sinusoidal jitter with stressed eye(8) 3.2 Gb/s 0.10 – – UI JT_SJSE6.6 6.6 Gb/s 0.10 – – UI Notes: 1. Using RXOUT_DIV = 1, 2, and 4. 2. All jitter values are based on a bit error ratio of 10 –12. 3. The frequency of the injected sinusoidal jitter is 10 MHz. 4. CPLL frequency at 2.0 GHz and RXOUT_DIV = 1 5. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. 6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. 7. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. 8. Composite jitter with RX equalizer enabled. DFE disabled. Table 56: GTH Transceiver Receiver Switching Characteristics (Cont’d) Symbol Description Condition Min Typ Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 55 GTH Transceiver Electrical Compliance The UltraScale Architecture GTH Transceiver User Guide (UG576 ) contains recommend ed use modes that ensure compliance for the protocols listed in Table 57 . The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. Table 57: GTH Transceiver Protocol List Protocol Specification Serial Rate (Gb/s) Electrical Compliance CAUI-10 IEEE 802.3-2012 10.3125 Compliant nPPI IEEE 802.3-2012 10.3125 Compliant 10GBASE-KR IEEE 802.3-2012 10.3125 Compliant SFP+ SFF-8431 (SR and LR) 9.95328–11.10 Compliant XFP INF-8077i, revision 4.5 10.3125 Compliant RXAUI CEI-6G-SR 6.25 Compliant 5.0G Ethernet IEEE 802.3bx (PAR) 5.0 Compliant QSGMII QSGMII v1.2 (Cisco Systems, ENG-46158) 5.0 Compliant XAUI IEEE 802.3-2012 3.125 Compliant 2.5G Ethernet IEEE 802.3bx (PAR) 2.5 Compliant 1000BASE-X IEEE 802.3-2012 1.25 Compliant OTU2 ITU G.8251 10.709225 Compliant OTU4 (OTL4.10) OIF-CEI-11G-SR 11.180997 Compliant OC-3/12/48/192 GR-253-CORE 0.1555–9.956 Compliant Interlaken OIF-CEI-6G, OIF-CEI-11G-SR 4.25–12.5 Compliant PCIe Gen1, 2, 3 PCI Express Base 3.0 2.5, 5.0, and 8.0 Compliant UHD-SDI (1) SMPTE ST-2081 6G, SMPTE St-2082 12G 6 and 12 Compliant SDI(1) SMPTE 424M-2006 0.27—2.97 Compliant Hybrid Memory Cube (HMC) HMC -15G-SR 12.5 and 15.0 Compliant CPRI CPRI_v_6_1_2014-07-01 0.6144–12.165 Compliant HDMI(2) HDMI 2.0 All Compliant Passive Optical Network (PON) 10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G-PON 0.155–10.3125 Compliant JESD204a/b OIF-CEI-6G, OIF-CEI-11G 3.125–12.5 Compliant Serial RapidIO RapidIO Specification 3.1 1.25–10.3125 Compliant DisplayPort (Source Only) DP 1.2B CTS 1.62–5.4 Compliant Fibre Channel FC-PI-4 1.0625–14.025 Compliant SATA Gen1, 2, 3 Serial ATA Revision 3.0 Specification 1.5, 3.0, and 6.0 Compliant SAS Gen1, 2, 3 T10/BSR INCITS 519 3.0, 6.0, and 12.0 Compliant SFI-5 OIF-SFI5-01.0 0.625–12.5 Compliant Notes: 1. SDI protocols require external circuitry to achieve compliance. 2. HDMI protocols require external circuitry to achieve compliance. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 56 GTH Transceiver Protocol Jitter Characteristics For Table 58 through Table 63 , the UltraScale Architecture GT H Transceiver User Guide (UG576 ) contains recommended settings for optimal usage of protocol specific characteristics. Table 58: Gigabit Ethernet Protocol Characteristics (GTH Transceivers) Description Line Rate (Mb/s) Min Max Units Gigabit Ethernet Transmitter Jitter Generation Total transmitter jitter (T_TJ) 1250 – 0.24 UI Gigabit Ethernet Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 1250 0.749 – UI Table 59: XAUI Protocol Characteristics (GTH Transceivers) Description Line Rate (Mb/s) Min Max Units XAUI Transmitter Jitter Generation Total transmitter jitter (T_TJ) 3125 – 0.35 UI XAUI Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 3125 0.65 – UI Table 60: PCI Express Protocol Characteristics (GTH Transceivers)(1) Standard Description Condition Line Rate (Mb/s) Min Max Units PCI Express Transmitter Jitter Generation PCI Express Gen 1 Total transmitter jitter 2500 – 0.25 UI PCI Express Gen 2 Total transmitter jitter 5000 – 0.25 UI PCI Express Gen 3(2) Total transmitter jitter uncorrelated 8000 – 31.25 ps Deterministic transmitter jitter uncorrelated – 12 ps PCI Express Receiver High Frequency Jitter Tolerance PCI Express Gen 1 Total receiver jitter tolerance 2500 0.65 – UI PCI Express Gen 2(2) Receiver inherent timing error 5000 0.40 – UI Receiver inherent deterministic timing error 0.30 – UI PCI Express Gen 3(2) Receiver sinusoidal jitter tolerance 0.03 MHz–1.0 MHz 8000 1.00 – UI 1 . 0M H z – 1 0M H z Note 3 –U I 10 MHz–100 MHz 0.10 – UI Notes: 1. Tested per card electrom echanical (CEM) methodology. 2. Using common REFCLK. 3. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 57 Table 61: CEI-6G and CEI-11G Protocol Characteristics (GTH Transceivers) Description Line Rate (Mb/s) Interface Min Max Units CEI-6G Transmitter Jitter Generation Total transmitter jitter(1) 4976–6375 CEI-6G-SR – 0.3 UI CEI-6G-LR – 0.3 UI CEI-6G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(1) 4976–6375 CEI-6G-SR 0.6 – UI CEI-6G-LR 0.95 – UI CEI-11G Transmitter Jitter Generation Total transmitter jitter(2) 9950–11100 CEI-11G-SR – 0.3 UI CEI-11G-LR/MR – 0.3 UI CEI-11G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(2) 9950–11100 CEI-11G-SR 0.65 – UI CEI-11G-MR 0.65 – UI CEI-11G-LR 0.825 – UI Notes: 1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock. 2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock. Table 62: SFP+ Protocol Characteristics (GTH Transceivers) Description Line Rate (Mb/s) Min Max Units SFP+ Transmitter Jitter Generation Total transmitter jitter 9830.40(1) –0 . 2 8 U I 9953.00 10312.50 10518.75 11100.00 SFP+ Receiver Frequency Jitter Tolerance Total receiver jitter tolerance 9830.40(1) 0.7 – UI 9953.00 10312.50 10518.75 11100.00 Notes: 1. Line rated used for CPRI over SFP+ applications. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 58 Table 63: CPRI Protocol Characteristics (GTH Transceivers) Description Line Rate (Mb/s) Min Max Units CPRI Transmitter Jitter Generation Total transmitter jitter 614.4 – 0.35 UI 1228.8 – 0.35 UI 2457.6 – 0.35 UI 3072.0 – 0.35 UI 4915.2 – 0.3 UI 6144.0 – 0.3 UI 9830.4 – Note 1 UI CPRI Receiver Frequency Jitter Tolerance Total receiver jitter tolerance 614.4 0.65 – UI 1228.8 0.65 – UI 2457.6 0.65 – UI 3072.0 0.65 – UI 4915.2 0.95 – UI 6144.0 0.95 – UI

9830.4 Note 1 –U I

Notes: 1. Tested per SFP+ specification, see Table 62. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 59 GTY Transceiver Specifications (XCKU095 and XQKU095) GTY Transceiver DC Input and Output Levels (XCKU095 and XQKU095) Table 64 summarizes the DC specifications of the GTY transceivers in the XCKU095 and XQKU095 devices (only). Consult www.xilinx.com/products/technology/high-speed-serial for further details. Table 64: GTY Transceiver DC Specifications Symbol DC Parameter Conditions Min Typ Max Units DVPPIN Differential peak-to-peak input voltage (external AC coupled) >10.3125 Gb/s 150 – 1250 mV 6.6 Gb/s to 10.3125 Gb/s 150 – 1250 mV ≤ 6.6 Gb/s 150 – 2000 mV V IN Single-ended input voltage. Voltage measured at the pin referenced to GND. DC coupled V MGTAVTT =1 . 2 V –400 – V MGTAVTT mV VCMIN Common mode input voltage DC coupled VMGTAVTT =1 . 2 V –2 / 3 V MGTAVTT –m V DVPPOUT Differential peak-to-peak output voltage(1) Transmitter output swing is set to 0x1F 800 – – mV V CMOUTDC Common mode output voltage: DC coupled (equation based) When remote RX is terminated to GND VMGTAVTT/2 – DVPPOUT/4 mV When remote RX termination is floating VMGTAVTT – DVPPOUT/2 mV When remote RX is terminated to VRX_TERM(2) mV VCMOUTAC Common mode output voltage: AC coupled Equation based V MGTAVTT – DVPPOUT/2 mV RIN Differential input resistance – 100 – Ω ROUT Differential output resistance – 100 – Ω TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew – – 5 ps CEXT Recommended external AC coupling capacitor(3) – 100 – nF Notes: 1. The output swing and pre-emphasis levels are programmable using the GTY transceiver attributes and can result in values lower than reported in this table. 2. V RX_TERM is the remote RX termination voltage. 3. Other values can be used as appropriate to conform to specific protocols and standards. VMGTAVTT DVPPOUT VMGTAVTT VRX_TERM– – Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 61 GTY Transceiver Switching Characteristics for the XCKU095 and XQKU095 Consult www.xilinx.com/products/tec hnology/high-speed-serial for further information. Table 67: GTY Transceiver Performance Symbol Description Output Divider Speed Grades and Temperature Range Units FGTYMAX GTY maximum line rate 16.375 12.5 Gb/s FGTYMIN GTY minimum line rate 0.5 0.5 Gb/s Min Max Min Max FGTYCRANGE CPLL line rate range(1) 1 4.0 12.5 4.0 8.5 Gb/s 2 2.0 6.25 2.0 4.25 Gb/s 4 1.0 3.125 1.0 2.125 Gb/s 8 0.5 1.5625 0.5 1.0625 Gb/s Min Max Min Max FGTYQRANGE1 QPLL0 line rate range 1(2) 9.8 16.375 9.8 12.5 Gb/s 2(2) 4.9 8.1875 4.9 8.1875 Gb/s 4(2) 2.45 4.09375 2.45 4.09375 Gb/s 8(2) 1.225 2.04688 1.225 2.04688 Gb/s 16(2) 0.6125 1.02344 0.6125 1.02344 Gb/s Min Max Min Max FGTYQRANGE2 QPLL1 line rate range 1(3) 8 . 01 3 . 08 . 0 1 2 . 5 G b / s 4(3) 2 . 03 . 2 52 . 0 3 . 2 5 G b / s 8(3) 1.0 1.625 1.0 1.625 Gb/s 16(3) 0.5 0.8125 0.5 0.8125 Gb/s Min Max Min Max FCPLLRANGE CPLL frequency range 2.0 6.25 2.0 4.25 GHz FQPLL0RANGE QPLL0 frequency range 9.8 16.375 9.8 16.375 GHz FQPLL1RANGE QPLL1 frequency range 8.0 13.0 8.0 13.0 GHz Notes: 1. The values listed are the rounded results of the calculated equation (2 x CPLL_Frequency)/Output_Divider. 2. The values listed are rounded results from calc ulated equation (QPLL0_Frequency)/Output_Divider. 3. The values listed are rounded results from calc ulated equation (QPLL1_Frequency)/Output_Divider. Table 68: GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Symbol Description XCKU095 and XQKU095 Units FGTYDRPCLK GTYDRPCLK maximum frequency 250 MHz Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 62 Table 69: GTY Transceiver Reference Clock Switching Characteristics Symbol Description Conditions Min Typ Max Units FGCLK Reference clock frequency range 60 – 820 MHz TRCLK Reference clock rise time 20% – 80% – 200 – ps TFCLK Reference clock fall time 80% – 20% – 200 – ps TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 % X-Ref Target - Figure 8 Figure 8: Reference Clock Timing Parameters Table 70: GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask(1) Symbol Description Offset Frequency Min Typ Max Units QPLLREFCLKMASK QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 156.25 MHz. 10 kHz – – –112 dBc/Hz100 kHz – – –128

1 MHz – – –145

QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz. 10 kHz – – –103 dBc/Hz100 kHz – – –123

1 MHz – – –143

QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency =625 MHz. 10 kHz – – –98 dBc/Hz100 kHz – – –117

1 MHz – – –140

CPLL reference clock select phase noise mask at REFCLK frequency = 156.25 MHz. 10 kHz – – –112 dBc/Hz 100 kHz – – –128

50 MHz – – –145

CPLL reference clock select phase noise mask at REFCLK frequency = 312.5 MHz. 10 kHz – – –103 dBc/Hz 100 kHz – – –123 CPLL reference clock select phase noise mask at REFCLK frequency = 625 MHz. 10 kHz – – –98 dBc/Hz 100 kHz – – –117

50 MHz – – –144

Notes: 1. For reference clock frequencies not in this table, use th e phase-noise mask for the nearest reference clock frequency. ds892_05_120414 80% 20% TFCLK TRCLK Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 63 Table 71: GTY Transceiver PLL/Lock Time Adaptation Symbol Description Conditions Min Typ Max Units TLOCK Initial PLL lock – – 1 ms TDLOCK Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE). After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. – 50,000 37 x 10 6 UI Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled. –5 0 , 0 0 0 2 . 3 x 1 0 6 UI Table 72: GTY Transceiver User Clock Switching Characteristics(1) Symbol Description Data Width Conditions (Bit) Speed Grades and Temperature Ranges Units Internal Logic Interconnect Logic -2E, -2I -1C, -1I, -1M FTXOUTPMA TXOUTCLK maximum frequency sourced from OUTCLKPMA 511.719 390.625 MHz FRXOUTPMA RXOUTCLK maximum frequency sourced from OUTCLKPMA 511.719 390.625 MHz FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from TXPROGDIVCLK 511.719 511.719 MHz FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from RXPROGDIVCLK 511.719 511.719 MHz FTXIN TXUSRCLK maximum frequency 16 16, 32 511.719 390.625 MHz 32 32, 64 511.719 390.625 MHz 20 20, 40 409.375 312.500 MHz 40 40, 80 409.375 312.500 MHz FRXIN RXUSRCLK maximum frequency 16 16, 32 511.719 390.625 MHz 32 32, 64 511.719 390.625 MHz 20 20, 40 409.375 312.500 MHz 40 40, 80 409.375 312.500 MHz F TXIN2 TXUSRCLK2 maximum frequency 16 16 511.719 390.625 MHz 20 20 409.375 312.500 MHz 16, 32 32 511.719 390.625 MHz 20, 40 40 409.375 312.500 MHz 32 64 255.860 195.313 MHz 40 80 204.688 156.250 MHz F RXIN2 RXUSRCLK2 maximum frequency 16 16 511.719 390.625 MHz 20 20 409.375 312.500 MHz 16, 32 32 511.719 390.625 MHz 20, 40 40 409.375 312.500 MHz 32 64 255.860 195.313 MHz 40 80 204.688 156.250 MHz Notes: 1. Clocking must be implem ented as described in the UltraScale Architecture GTY Transceiver User Guide (UG578). Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 64 Table 73: GTY Transceiver Transmitter Switching Characteristics Symbol Description Condition Min Typ Max Units FGTYTX Serial data rate range 0.500 – F GTYMAX Gb/s TRTX TX rise time 20%–80% – 40 – ps TFTX TX fall time 80%–20% – 40 – ps TLLSKEW TX lane-to-lane skew(1) –– 5 0 0 p s TJ16.375_QPLL Total jitter(2)(4)

16.375 Gb/s

– – 0.28 UI DJ16.375_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ15.0_QPLL Total jitter(2)(4) – – 0.28 UI DJ15.0_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ14.1_QPLL Total jitter(2)(4) – – 0.28 UI DJ14.1_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ14.025_QPLL Total jitter(2)(4) – – 0.28 UI DJ14.025_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ13.1_QPLL Total jitter(2)(4) – – 0.28 UI DJ13.1_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ12.5_QPLL Total jitter(2)(4) – – 0.28 UI DJ12.5_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ12.5_CPLL Total jitter(2)(4) – – 0.33 UI DJ12.5_CPLL Deterministic jitter(2)(4) – – 0.17 UI TJ11.3_QPLL Total jitter(2)(4) – – 0.28 UI DJ11.3_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ10.3125_QPLL Total jitter(2)(4)

10.3125 Gb/s

– – 0.28 UI DJ10.3125_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ10.3125_CPLL Total jitter(3)(4) – – 0.33 UI DJ10.3125_CPLL Deterministic jitter(3)(4) – – 0.17 UI TJ9.953_QPLL Total jitter(2)(4)

9.953 Gb/s

– – 0.28 UI DJ9.953_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ9.8_QPLL Total jitter(2)(4) – – 0.28 UI DJ9.8_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ8.0_QPLL Total jitter(2)(4) – – 0.28 UI DJ8.0_QPLL Deterministic jitter(2)(4) – – 0.17 UI TJ8.0_CPLL Total jitter(3)(4) – – 0.32 UI DJ8.0_CPLL Deterministic jitter(3)(4) – – 0.17 UI TJ6.6_CPLL Total jitter(3)(4) – – 0.30 UI DJ6.6_CPLL Deterministic jitter(3)(4) – – 0.15 UI TJ5.0 Total jitter(3)(4) – – 0.30 UI DJ5.0 Deterministic jitter(3)(4) – – 0.15 UI TJ4.25 Total jitter(3)(4) – – 0.30 UI DJ4.25 Deterministic jitter(3)(4) – – 0.15 UI Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 65 TJ4.00L Total jitter(3)(4)

4.00 Gb/s

– – 0.32 UI DJ4.00L Deterministic jitter(3)(4) – – 0.16 UI TJ3.75 Total jitter(3)(4)

3.75 Gb/s

– – 0.20 UI DJ3.75 Deterministic jitter(3)(4) – – 0.10 UI TJ3.20 Total jitter(3)(4) DJ3.20 Deterministic jitter(3)(4) – – 0.10 UI TJ2.5 Total jitter(3)(4) DJ2.5 Deterministic jitter(3)(4) – – 0.10 UI TJ1.25 Total jitter(3)(4) DJ1.25 Deterministic jitter(3)(4) – – 0.05 UI TJ500 Total jitter(3)(4)

500 Mb/s

– – 0.10 UI DJ500 Deterministic jitter(3)(4) – – 0.05 UI Notes: 1. Using same REFCLK input with TX phas e alignment enabled for up to four fully-populated GTY Quads at maximum line rate. 2. Using QPLL_FBDIV = 40, 20-bit internal data width. These va lues are NOT intended for protocol specific compliance determinations. 3. Using CPLL_FBDIV = 2, 20-bit internal da ta width. These values are NOT intended for protocol specific compliance determinations. 4. All jitter values are based on a bit-error ratio of 10 -12. 5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. 6. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. 7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4. Table 74: GTY Transceiver Receiver Switching Characteristics Symbol Description Condition Min Typ Max Units FGTYRX Serial data rate 0.500 – F GTYMAX Gb/s TRXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data –1 0– n s RXOOBVDPP OOB detect threshold peak-to-peak 60 – 150 mV RXSST Receiver spread-spectrum tracking(1) Modulated at 33 kHz –5000 – 0 ppm RXRL Run length (CID) – – 256 UI RXPPMTOL Data/REFCLK PPM offset tolerance Bit rates ≤ 6.6 Gb/s –1250 – 1250 ppm Bit rates > 6.6 Gb/s and ≤ 8.0 Gb/s –700 – 700 ppm Bit rates > 8.0 Gb/s –200 – 200 ppm SJ Jitter Tolerance(2) JT_SJ16.375 Sinusoidal jitter (CPLL)(3) 16.375 Gb/s – – 0.30 UI JT_SJ15.0 Sinusoidal jitter (CPLL)(3) 15.0 Gb/s – – 0.30 UI JT_SJ14.1 Sinusoidal jitter (CPLL)(3) 14.1 Gb/s – – 0.30 UI JT_SJ13.1 Sinusoidal jitter (CPLL)(3) 13.1 Gb/s – – 0.30 UI JT_SJ12.5_QPLL Sinusoidal jitter (CPLL)(3) 12.5 Gb/s – – 0.30 UI JT_SJ12.5_CPLL Sinusoidal jitter (CPLL)(3) 12.5 Gb/s – – 0.30 UI JT_SJ11.3 Sinusoidal jitter (CPLL)(3) 11.3 Gb/s – – 0.30 UI JT_SJ10.32_QPLL Sinusoidal jitter (CPLL)(3) 10.32 Gb/s – – 0.30 UI Table 73: GTY Transceiver Transmitter Switching Characteristics (Cont’d) Symbol Description Condition Min Typ Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 66 JT_SJ10.32_CPLL Sinusoidal jitter (CPLL)(3) 10.32 Gb/s – – 0.30 UI JT_SJ9.8 Sinusoidal jitter (CPLL)(3) 9.8 Gb/s – – 0.30 UI JT_SJ8.0_QPLL Sinusoidal jitter (CPLL)(3) 8.0 Gb/s – – 0.44 UI JT_SJ8.0_CPLL Sinusoidal jitter (CPLL)(3) 8.0 Gb/s – – 0.42 UI JT_SJ6.6_CPLL Sinusoidal jitter (CPLL)(3) 6.6 Gb/s – – 0.44 UI JT_SJ5.0 Sinusoidal jitter (CPLL)(3) 5.0 Gb/s – – 0.44 UI JT_SJ4.25 Sinusoidal jitter (CPLL)(3) 4.25 Gb/s – – 0.44 UI JT_SJ4.00L Sinusoidal jitter (CPLL)(3) 4.0 Gb/s – – 0.45 UI JT_SJ3.75 Sinusoidal jitter (CPLL)(3) 3.75 Gb/s – – 0.45 UI JT_SJ3.20 Sinusoidal jitter (CPLL)(3) 3.2 Gb/s(4) –– 0 . 4 5 U I JT_SJ2.5 Sinusoidal jitter (CPLL)(3) 2.5 Gb/s(5) –– 0 . 5 0 U I JT_SJ1.25 Sinusoidal jitter (CPLL)(3) 1.25 Gb/s(6) –– 0 . 5 0 U I JT_SJ500 Sinusoidal jitter (CPLL)(3) 500 Mb/s – – 0.50 UI SJ Jitter Tolerance with Stressed Eye(2) JT_TJSE3.2 Total jitter with stressed eye(7) 3.2 Gb/s – – 0.7 UI JT_TJSE6.6 6.6 Gb/s – – 0.7 UI JT_SJSE3.2 Sinusoidal jitter with stressed eye(7) 3.2 Gb/s – 0.7 UI JT_SJSE6.6 6.6 Gb/s – 0.7 UI Notes: 1. Using RXOUT_DIV = 1, 2, and 4. 2. All jitter values are based on a bit error ratio of 10 –12. 3. The frequency of the injected sinusoidal jitter is 80 MHz. 4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. 5. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. 6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. 7. Composite jitter with RX equalizer enabled. DFE disabled. Table 74: GTY Transceiver Receiver Switching Characteristics (Cont’d) Symbol Description Condition Min Typ Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 67 GTY Transceiver Electrical Compliance for the XCKU095 and XQKU095 The UltraScale Archit ecture GTY Transceiver User Guide (UG578 ) contains recommended use modes that ensure compliance for the protocols listed in Table 75 . The transceiver wizard provides the recommended settings for those use cases and for protocol specific characteristics. Table 75: GTY Transceiver Protocol List Protocol Specification Serial Rate (Gb/s) Electrical Compliance Interlaken OIF-CEI-6G, OIF- CEI-11GSR 4.25–12.5 Compliant CAUI-10 IEEE 802.3-2012 10.3125 Compliant nPPI IEEE 802.3-2012 10.3125 Compliant 10GBASE-KR IEEE 802.3-2012 10.3125 Compliant SFP+ SFF-8431 (SR and LR) 9.95328–11.10 Compliant XFP INF-8077i, Revision 4.5 10.3125 Compliant RXAUI CEI-6G-SR 6.25 Compliant XAUI IEEE 802.3-2012 3.125 Compliant 1000BASE-X IEEE 802.3-2012 1.25 Compliant OTU2 ITU G.8251 10.709225 Compliant OTU4 (OTL4.10) OIF-CEI-11G-SR 11.180997 Compliant OC-3/12/48/192 GR-253-CORE 0.1555–9.956 Compliant PCIe Gen1, 2, 3 PCI Express Base 3.0 2.5, 5.0, and 8.0 Compliant SDI SMPTE 424M-2006 0.27–2.97 Compliant Hybrid Memory Cube (HMC) HMC-15G-SR 12.5 and 15.0 Compliant CPRI CPRI_v_6_1_2014-07-01 0.6144–12.165 Compliant Passive Optical Network (PON) 10G-EPON, 1G-EPON, NG-PON2, XG-PON, and 2.5G-PON 0.155–10.3125 Compliant JESD204a/b OIF-CEI-6G, OIF-CEI-11G 3.125–12.5 Compliant Serial RapidIO RapidIO Specification 3.1 1.25–10.3125 Compliant DisplayPort (Source Only) DP 1.2B CTS 1.62–5.4 Compliant Fibre Channel FC-PI-4 1.0625–14.025 Compliant SATA Gen1, 2, 3 Serial ATA Revision 3.0 Specification 1.5, 3.0, and 6.0 Compliant SAS Gen1, 2, 3 T10/BSR INCITS 519 3.0, 6.0, and 12.0 Compliant SFI-5 OIF-SFI5-01.0 0.625 - 12.5 Compliant Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 68 GTY Transceiver Protocol Jitter Ch aracteristics (XCKU095 and XQKU095) For Table 76 through Table 80 , the UltraScale Architecture GTY Transceiver User Guide (UG578 ) contains recommended settings for optimal usage of protocol specific characteristics. Table 76: Gigabit Ethernet Protocol Characteristics (GTY Transceivers) Description Line Rate (Mb/s) Min Max Units Gigabit Ethernet Transmitter Jitter Generation Total transmitter jitter (T_TJ) 1250 – 0.24 UI Gigabit Ethernet Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 1250 0.749 – UI Table 77: XAUI Protocol Characteristics (GTY Transceivers) Description Line Rate (Mb/s) Min Max Units XAUI Transmitter Jitter Generation Total transmitter jitter (T_TJ) 3125 – 0.35 UI XAUI Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 3125 0.65 – UI Table 78: CEI-6G and CEI-11G Protocol Characteristics (GTY Transceivers) Description Line Rate (Mb/s) Interface Min Max Units CEI-6G Transmitter Jitter Generation Total transmitter jitter(1) 4976–6375 CEI-6G-SR – 0.3 UI CEI-6G-LR – 0.3 UI CEI-6G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(1) 4976–6375 CEI-6G-SR 0.6 – UI CEI-6G-LR 0.95 – UI CEI-11G Transmitter Jitter Generation Total transmitter jitter(2) 9950–11100 CEI-11G-SR – 0.3 UI CEI-11G-LR/MR – 0.3 UI CEI-11G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(2) 9950–11100 CEI-11G-SR 0.65 – UI CEI-11G-MR 0.65 – UI CEI-11G-LR 0.825 – UI Notes: 1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock. 2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 69 Table 79: SFP+ Protocol Characteristics (GTY Transceivers) Description Line Rate (Mb/s) Min Max Units SFP+ Transmitter Jitter Generation Total transmitter jitter 9830.40(1) –0 . 2 8 U I 9953.00 10312.50 10518.75 11100.00 SFP+ Receiver Frequency Jitter Tolerance Total receiver jitter tolerance 9830.40(1) 0.7 – UI 9953.00 10312.50 10518.75 11100.00 Notes: 1. Line rated used for CPRI over SFP+ applications. Table 80: CPRI Protocol Characteristics (GTY Transceivers) Description Line Rate (Mb/s) Min Max Units CPRI Transmitter Jitter Generation Total transmitter jitter 614.4 – 0.35 UI 1228.8 – 0.35 UI 2457.6 – 0.35 UI 3072.0 – 0.35 UI 4915.2 – 0.3 UI 6144.0 – 0.3 UI 9830.4 – Note 1 UI CPRI Receiver Frequency Jitter Tolerance Total receiver jitter tolerance 614.4 0.65 – UI 1228.8 0.65 – UI 2457.6 0.65 – UI 3072.0 0.65 – UI 4915.2 0.95 – UI 6144.0 0.95 – UI Notes: 1. Tested per SFP+ specification, see Table 79. Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 70 Integrated Interface Block for Interlaken for the XCKU095 and XQKU095 More information and documentation on solutions usin g the integrated interface block for Interlaken can be found at UltraScale Interlaken . Integrated Interface Block for 100G Ethernet MAC and PCS for the XCKU095 and XQKU095 More information and documentation on solutions us ing the integrated 100 Gb/s Ethernet block can be found at UltraScale Integrated 100G Ethernet MAC/PCS . Table 81: Maximum Performance for Interlaken Designs Symbol Description Speed Grades and VCCINT Operating Voltage Units0.95V -2 -1 FRX_SERDES_CLK Receive serializer/ deserializer clock 195.32 195.32 MHz FTX_SERDES_CLK Transmit serializer/ deserializer clock 195.32 195.32 MHz FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 MHz Min Max Min Max FCORE_CLK Interlaken core clock 300.00 322.27 300.00 322.27 MHz FLBUS_CLK Interlaken local bus clock 300.00 322.27 300.00 322.27 MHz Table 82: Maximum Performance for 100G Ethernet Designs Symbol Description Speed Grades and VCCINT Operating Voltage Units0.95V -2 -1 FTX_CLK Transmit clock 322.27 322.27 MHz FRX_CLK Receive clock 322.27 322.27 MHz FRX_SERDES_CLK Receive serializer/deserializer clock 322.27 322.27 MHz FDRP_CLK Dynamic reconfiguration port clock 250.00 250.00 MHz Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 71 Integrated Interface Block for PCI Express Designs More information and documentation on soluti ons for PCI Express designs can be found at PCI Express . System Monitor Specifications Table 83: Maximum Performance for PCI Express Designs Symbol Description Speed Grades and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L Notes: 1. PCI Express x8 Gen 3 operation is supported in -2 and -3 speed grades. Refer to the UltraScale Architecture Gen3 Integrated Block for PCI Express v4.0 User Guide (PG156) for information regarding x8 Gen 3 operation in the -1 speed grade. Table 84: SYSMON Specifications Parameter Symbol Comments/Conditions Min Typ Max Units VCCADC = 1.8V ±3%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 5.2 MHz, Tj = –40°C to 100°C, typical values at Tj = 40°C ADC Accuracy(1) Resolution 10 – – Bits Integral nonlinearity(2) INL – – ±2 LSBs Differential nonlinearity DNL No missing codes, guaranteed monotonic –– ± 1 L S B s Offset error Offset calibration enabled – – ±2 LSBs Gain error –– ± 0 . 4 % Sample rate –– 0 . 2 M S / s RMS code noise External 1.25V reference – – 1 LSBs On-chip reference – 1 – LSBs ADC Accuracy at Extended Temperatures Resolution T j = –55°C to 125°C 10 – – Bits Integral nonlinearity INL T j = –55°C to 125°C – – ±2 LSBs Differential nonlinearity DNL No missing codes, guaranteed monotonic T j = –55°C to 125°C –– ± 1 Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 72 Analog Inputs(2) ADC input ranges Unipolar operation 0 – 1 V Bipolar operation –0.5 – +0.5 V Unipolar common mode range (FS input) 0 – +0.5 V Bipolar common mode range (FS input) +0.5 – +0.6 V Maximum external channel input ranges Adjacent channels set within these ranges should not corrupt measurements on adjacent channels –0.1 – V CCADC V On-Chip Sensor Accuracy Temperature sensor error(1) Tj = –40°C to 100°C (with external REF) – – ±4 °C Tj = –55°C to 125°C (with external REF) – – ±4.5 °C Tj = –40°C to 100°C (with internal REF) – – ±5 °C Tj = –55°C to 125°C (with internal REF) – – ±6.5 °C Supply sensor error(3) Tj = –40°C to 100°C (with external REF) – – ±1 % Tj = –55°C to 125°C (with external REF) – – ±2 % Tj = –40°C to 100°C (with internal REF) – – ±1.5 % Tj = –55°C to 125°C (with internal REF) – – ±2.5 % Conversion Rate(4) Conversion time—continuous t CONV Number of ADCCLK cycles 26 – 32 Cycles Conversion time—event t CONV Number of ADCCLK cycles – – 21 Cycles DRP clock frequency DCLK DRP clock frequency 8 – 250 MHz ADC clock frequency ADCCLK Derived from DCLK 1 – 5.2 MHz DCLK duty cycle 40 – 60 % SYSMON Reference(5) External reference V REFP Externally supplied reference voltage 1.20 1.25 1.30 V On-chip reference Ground VREFP pin to AGND, -2 and -3 speed grade T j = –40°C to 100°C 1.2375 1.25 1.2625 V Ground VREFP pin to AGND, -1 and -1L speed grade T j = –40°C to 100°C 1.23125 1.25 1.26875 V Ground VREFP pin to AGND, Tj = –55°C to 125°C 1.225 1.25 1.275 V Notes: 1. ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is enabled. 2. See the Analog Input section in the UltraScale Architecture System Monitor User Guide (UG580). 3. Supply sensor offset and gain errors ar e removed by enabling the automatic offset and gain calibration feature. The values are specified for when this feature is enabled. 4. See the Adjusting the Acquisition Settling Time section in the UltraScale Architecture System Monitor User Guide (UG580). 5. Any variation in the reference voltage from the nominal V REFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. Table 84: SYSMON Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 74 Configuration Switching Characteristics Table 87: Configuration Switching Characteristics Symbol Description Speed Grades and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L Power-up Timing Characteristics TPOR Power-on reset (40 ms ramp rate time) 57 57 57 57 57 ms, Max 00000 m s , M i n Power-on reset with POR override (2 ms ramp rate time) 15 15 15 15 15 ms, Max 55555 m s , M i n TPROGRAM Program pulse width 250 250 250 250 250 ns, Min CCLK Output (Master Mode) TICCK Master CCLK output delay from INIT_B 150 150 150 150 150 ns, Min TMCCKL(1) Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max TMCCKH Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max FMCCK Master CCLK frequency SPI x2/x4/x8 BPI x8/x16 150 150 150 150 150 MHz, Max SPI x1 and serial SLR-based devices 125 125 125 125 125 MHz, Max SPI x1 and serial all other devices 150 150 150 150 150 MHz, Max SelectMAP 125 125 125 125 125 MHz, Max FMCCK_START Master CCLK frequency at start of configuration 33333 M H z , T y p FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK ±35 ±35 ±35 ±35 ±35 %, Max CCLK Input (Slave Modes) FSCCK Slave CCLK frequency Serial SLR-based 125 125 125 125 125 MHz, Max Serial All other devices 150 150 150 150 150 MHz, Max SelectMAP 125 125 125 125 125 MHz, Max Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 75 EMCCLK Input (Master Mode) FEMCCK External master CCLK frequency SPI x2/x4/x8 BPI x8/x16 150 150 150 150 150 MHz, Max SPI x1, Serial SLR-based 125 125 125 125 125 MHz, Max SPI x1, Serial All other devices 150 150 150 150 150 MHz, Max SelectMAP 125 125 125 125 125 MHz, Max Internal Configuration Access Port FICAPCK Internal configuration access port (ICAPE3) Master SLR ICAP accessing the entire device 125 125 125 125 125 MHz, Max SLR ICAP accessing the local SLR 200 200 200 200 200 MHz, Max All other devices 200 200 200 200 200 MHz, Max Master/Slave Serial Mode Programming Switching TCCO DOUT c l o c k t o o u t 88888 n s , M a x SelectMAP Mode Programming Switching TSMCKCSO CSO_B clock to out (330Ω pull-up resistor required) 77777 n s , M a x TSMCO D [ 3 1 : 0 0 ] c l o c k t o o u t i n r e a d b a c k 88888 n s , M a x FRBCCK Readback frequency SLR-based 125 125 125 125 125 MHz, Max All other devices 125 125 125 125 125 MHz, Max Boundary-Scan Port Timing Specifications TTAPTCK/TTCKTAP TMS and TDI setup/hold SLR-based 7.0/ 2.0 7.0/ 2.0 7.0/ 2.0 7.0/ 2.0 7.0/ 2.0 ns, Min All other devices 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 3.0/ 2.0 ns, Min TTCKTDO TCK falling edge to TDO output S L R - b a s e d 1 01 01 01 01 0n s , M a x A l l o t h e r d e v i c e s 77777 n s , M a x FTCK TCK frequency S L R - b a s e d 2 02 02 02 02 0 M H z , M a x X C K U 0 9 5 5 05 05 05 05 0 M H z , M a x A l l o t h e r d e v i c e s6 66 66 66 66 6 M H z , M a x Table 87: Configuration Switching Characteristics (Cont’d) Symbol Description Speed Grades and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 76 BPI Master Flash Mode Programming Switching TBPICCO A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B clock to out 10 10 10 10 10 ns, Max SPI Master Flash Mode Programming Switching DNA Port Switching FDNACK DNA port frequency 200 200 200 200 200 MHz, Max STARTUPE3 Ports TUSRCCLKO STARTUPE3 USRCCLKO input port to CCLK pin output delay 1.00/ 6.00 1.00/ 6.70 1.00/ 7.50 1.00/ 7.50 1.00/ 7.50 ns, Min/Max TDO DO[3:0] ports to D03-D00 pins output delay 1.00/ 6.70 1.00/ 7.70 1.00/ 8.40 1.00/ 8.40 1.00/ 8.40 ns, Min/Max TDTS DTS[3:0] ports to D03-D00 pins 3-state delays 1.00/ 7.30 1.00/ 8.30 1.00/ 9.00 1.00/ 9.00 1.00/ 9.00 ns, Min/Max TFCSBO FCSBO port to FCS_B pin output delay 1.00/ 6.90 1.00/ 8.00 1.00/ 8.60 1.00/ 8.60 1.00/ 8.60 ns, Min/Max TFCSBTS FCSBTS port to FCS_B pin 3-state delay 1.00/ 6.90 1.00/ 8.00 1.00/ 8.60 1.00/ 8.60 1.00/ 8.60 ns, Min/Max TUSRDONEO USRDONEO port to DONE pin output delay 1.00/ 8.50 1.00/ 9.60 1.00/ 10.40 1.00/ 10.40 1.00/ 10.40 ns, Min/Max TUSRDONETS USRDONETS port to DONE pin 3-state delay 1.00/ 8.50 1.00/ 9.60 1.00/ 10.40 1.00/ 10.40 1.00/ 10.40 ns, Min/Max TDI D03-D00 pins to DI[3:0] ports input delay 0.5/ 2.6 0.5/ 3.1 0.5/ 3.5 0.5/ 3.5 0.5/ 3.5 ns, Min/Max FCFGMCLK S T A R T U P E 3 C F G M C L K o u t p u t f r e q u e n c y 5 05 05 05 05 0 M H z , T y p FCFGMCLKTOL STARTUPE3 CFGMCLK output frequency tolerance ±15 ±15 ±15 ±15 ±15 %, Max Startup Timing TDCI_MATCH Specifies a stall in the startup cycle until the digitally controlled impedance (DCI) match signals are asserted. 44444 m s , M a x Notes: 1. When the CCLK is sourced from the EMCCLK pin with a di vide-by-one setting, the external EMCCLK must meet this duty-cycle requirement. Table 87: Configuration Switching Characteristics (Cont’d) Symbol Description Speed Grades and VCCINT Operating Voltages Units1.0V 0.95V 0.90V -3 -2 -1 -1L -1L Send Feedback

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics DS892 (v1.14) February 2, 2017 www.xilinx.com Product Specification 77 eFUSE Programming Conditions

Revision History

The following table shows the revision history for this document. Table 88: eFUSE Programming Conditions(1) Symbol Description Min Typ Max Units IFS VCCAUX supply current – – 115 mA Tj Temperature range –40 – 125 °C Notes: 1. Do not program eFUSE during device conf iguration (e.g., during configuration, during configuration readback, or when readback CRC is active). Date Version Description of Revisions 02/02/2017 1.14 Updated Table 21 and Table 22 to production release for the following devices/speed/ temperature grades in the XQ Kintex UltraScale family in Vivado Design Suite 2016.4. XQKU040: -1M, -2I, -2E, -1I (0.95V) devices XQKU060: -1M, -2I, -2E, -1I (0.95V) devices XQKU095: -1M, -2I, -2E, -1I (0.95V) devices XQKU115: -2I, -2E, -1I (0.95V) devices Updated Table 24 with clarifications to the SDR minimums. Updated MMCM_F DRPCLK_MAX in Table 36 and PLL_FDRPCLK_MAX in Table 37. 12/22/2016 1.13 The Vivado Design Suite version is updated to the latest version listed in Table 20 (either v1.23 or v1.24). Per the Kintex UltraScale and Virtex UltraScale FPGA Speed Specification Changes (XCN16031), Table 22 changes the minimum speed specification versions for designing with devices listed in this data sheet per the design advisory answer record AR68169: Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs—New minimum production speed specification version (Speed File) required for all designs. Added the XQ devices to applicable tables including Table 20, Table 21, and Table 22. Clarified the maximum IDC and TSOL in Table 1. Updated IL in Table 3 to include XQ devices. Added HP and HR minimum values to Table 23 and Table 24. Added TMINPER_CLK and Note 1 to Table 33. Added MMCM_FDRPCLK_MAX to Table 36 and PLL_FDRPCLK_MAX to Table 37. In the Table 49 package type row, added SF for -3 and -2 speed specifications. This information is already reflected in the UltraScale Architecture and Product Overview (DS890). Added Table 66. Updated the Automotive Applications Disclaimer. 04/01/2016 1.12 Updated Table 20, Table 21, and Table 22 to production release in Vivado Design Suite 2016.1 of the following devices/speed/temperature grades. With these changes, the XC Kintex UltraScale family is production released. XCKU085: -1L (0.95V) and -1L (0.90V) devices XCKU115: -1L (0.95V) and -1L (0.90V) devices In Table 26, added LPDDR3, updated the package fields, increased the DDR4 and DDR3L memory PHY rates in the FBVA676/ SFVA784 packages, added LRDIMMs to the notes, and removed Note 7. In addition, the QDRIV-XP is only for HP I/O banks. Updated V MEAS for LVCMOS and LVTTL in Table 30. In Table 32, added the Block RAM and FIFO Clock-to-Out Delays section. Added Table 70. 12/16/2015 1.11 Updated the Power-On/Off Power Supply Sequencing section. Updated Table 20 to speed specification 2015.4.1. Increased the FGTHMAX for -1LI (0.90V) in Table 49 and added Note 1. Updated the -1LI (0.90V) column in Table 54. Send Feedback

In Table 45, added the value for package skew on the XCKU095 FFVA1156. 10/12/2015 1.9 Updated data in Table 6 (XCKU025, XCKU085, and XCKU095) and Table 7 (XCKU095). Updated the description in Power-On/Off Power Supply Sequencing. Table 43, and Table 87 with speed specifications for Vivado Design Suite 2015.3. Updated Table 45 with package skew data. Added Startup Timing to Table 87. 09/22/2015 1.8 Added GTY tables to support the XCKU095. Added the XCKU025 device. power supply operating range. Updated description of ICCADC. Table 87 with speed specifications for Vivado Design Suite 2015.2.1. Updated Table 26 with more delineated values including adding package variations. In Table 45 added the XCKU095 FFVA1156 package and updated skew values. Updated protocols in Table 57. Revised the values in Table 81 and removed Note 1. Updated Table 84: Sample rate. other devices), added values by speed grade, and updated -1L specifications. Table 87 with speed specifications for Vivado Design Suite 2015.2 v1.17. Added Table 52: GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask. Added the GTH Transceiver Electrical Compliance section. Table 87. Updated Note 1 in Table 88.

Table 43. Also, in Table 29, revised the HR I/O values for TOUTBUF_DELAY_TE_PAD and added Table 84. In Table 87, added more specifications to the STARTUPE3 Ports section. section including adding Note 9. MINI_LVDS_25 and RSDS_25 in Table 12. Revised the VICM specifications in Table 14. Table 21, Table 22, Table 45, and Table 49. Removed Table 27. Vivado Design Suite 2014.4.1. Table 33. Revised MMCM_TLOCKMAX in Table 36. Revised the FINMAX in Table 36 and Table 37. Updated Table 44. Updated devices listed, packages listed, and package skew TUSRCCLKO specifications in Table 87. parameter tables on page 40 and page 43. Revised the values for FLBUS_CLK in Table 81. FMCCKTOL, and FRBCCK, added the STARTUPE3 Ports section, and added Note 1. 07/10/2014 1.3 Updated LVDCI_15 information in Table 10. Revised the SLVS_400 values in Table 12. Removed RLDRAM II from Table 26 and Table 27. Also added FBV Package to Table 27. Figure 4. Updated Note 1 in Table 55. Added two new sections for the Integrated Interface for 100G Ethernet MAC and PCS for the XCKU095 and XQKU095.

IOH specifications. Removed the POD standards from Table 10 and Table 14. notes in Table 42 and Table 43. Table 35. In Table 84, updated On-Chip Sensor Accuracy section, removed Gain error conditions, updated Note 1, and added Note 3. TTAPTCK/TTCKTAP, TTCKTDO, and FTCK. 04/09/2014 1.1 Added IDC and IRMS to Table 1. specifications for DDR4. Updated the speed specifications in Table 27 and Table 28. Table 33 especially FREFCLK, TMINPER_RST, and the IDELAY/ODELAY chain resolution. Table 47. In Table 49, increased the FGTHQRANGE1 maximum for the 16 output dividers in TLLSKEW value and units in Table 55. Updated the notes in Table 60. updated some of the On-Chip Sensor Accuracy maximum values. Revised FMCCK and updated the ramp rate for TPOR in Table 87. 12/10/2013 1.0 Initial Xilinx release.

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