XC7S100

XC7S6-2CPGA196I AMD | Alldatasheet

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DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 1 Introduction Spartan®-7 FPGAs are available in -2, -1, and -1L spee d grades, with -2 having the highest performance. The Spartan-7 FPGAs predominantly operate at a 1.0V core voltage. The -1L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 devices. The -1L devices operate only at V CCINT =V CCBRAM = 0.95V and have the same speed specifications as the -1 speed grade. Spartan-7 FPGA DC and AC characteristics are specified in commercial (C), industri al (I), and expanded (Q) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular sp eed grade (that is, the timing characteristics of a -1Q expanded speed grade device are the same as for a -1C commercial speed grade device). However, only selected speed grades and/or devices are available in each temperature range. For example, the -1L speed grade is only available in the industrial (I) temperature range. All supply voltage and junction temp erature specifications are representative of worst-case conditions. The parameters included are common to po pular designs and typical applications. Available device and package combinations can be found in:

• 7 Series FPGAs Overview (DS180) [Ref 1]
• XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2] This Spartan-7 FPGA data sheet, part of an overall se t of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/documentation . DC Characteristics Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 Product Specification Table 1: Absolute Maximum Ratings(1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage. –0.5 1.1 V VCCAUX Auxiliary supply voltage. –0.5 2.0 V VCCBRAM Supply voltage for the block RAM memories. –0.5 1.1 V VCCO Output drivers supply voltage for HR I/O banks. –0.5 3.6 V VREF Input reference voltage. –0.5 2.0 V Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 2 VIN(2)(3)(4) I/O input voltage. –0.4 V CCO +0 . 5 5 V I/O input voltage (when VCCO =3 . 3 V ) f o r VREF and differential I/O standards except TMDS_33.(5) –0.4 2.625 V VCCBATT Key memory battery backup supply. –0.5 2.0 V XADC VCCADC XADC supply relative to GNDADC. –0.5 2.0 V VREFP XADC reference input relative to GNDADC. –0.5 2.0 V Temperature TSTG Storage temperature (ambient). –65 150 °C TSOL Maximum soldering temperature for Pb/Sn component bodies.(6) –+ 2 2 0 ° C Maximum soldering temperature for Pb-free component bodies.(6) –+ 2 6 0 ° C Tj Maximum junction temperature.(6) –+ 1 2 5 ° C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. The lower absolute voltage specification always applies. 3. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3]. 4. The maximum limit applies to DC signals. For maxi mum undershoot and overshoot AC specifications, see Table 4. 5. See Table 9 for TMDS_33 specifications. 6. For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4]. Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 3 Table 2: Recommended Operating Conditions(1)(2) Symbol Description Min Typ Max Units FPGA Logic VCCAUX Auxiliary supply voltage. 1.71 1.80 1.89 V VCCO(4)(5) Supply voltage for HR I/O banks. 1.14 – 3.465 V VIN(6) I/O input voltage. –0.20 – V CCO +0 . 2 0 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33.(7) –0.20 – 2.625 V IIN(8) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. –– 1 0 m A VCCBATT(9) Battery voltage. 1.0 – 1.89 V XADC VCCADC XADC supply relative to GNDADC. 1.71 1.80 1.89 V VREFP Externally supplied reference voltage. 1.20 1.25 1.30 V Temperature Tj Junction temperature operating range for commercial (C) temperature devices. 0– 8 5 ° C Junction temperature operating range for industrial (I) temperature devices. –40 – 100 °C Junction temperature operating range for expanded (Q) temperature devices. –40 – 125 °C Notes: 1. All voltages are relative to ground. 2. For the design of the power distribution system consult the 7 Series FPGAs PCB Design Guide (UG483) [Ref 5]. 3. If V CCINT and VCCBRAM are operating at the same voltage, VCCINT and VCCBRAM should be connected to the same supply. 4. Configuration data is retained even if V CCO drops to 0V. 6. The lower absolute voltage specification always applies. 7. See Table 9 for TMDS_33 specifications. 8. A total of 200 mA per bank should not be exceeded. 9. V CCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 4 Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ (1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost). 0.75 – – V VDRI Data retention VCCAUX voltage (below which configuration data might be lost). 1.5 – – V IREF VREF leakage current per pin. – – 15 µA IL Input or output leakage current per pin (sample-tested). – – 15 µA CIN(2) Die input capacitance at the pad. – – 8 pF IRPU Pad pull-up (when selected) at VIN = 0V, VCCO =3 . 3 V . 9 0 – 3 3 0 µ A Pad pull-up (when selected) at VIN = 0V, VCCO =2 . 5 V . 6 8 – 2 5 0 µ A Pad pull-up (when selected) at VIN = 0V, VCCO =1 . 8 V . 3 4 – 2 2 0 µ A Pad pull-up (when selected) at VIN = 0V, VCCO =1 . 5 V . 2 3 – 1 5 0 µ A Pad pull-up (when selected) at VIN = 0V, VCCO =1 . 2 V . 1 2 – 1 2 0 µ A IRPD Pad pull-down (when selected) at VIN =3 . 3 V . 6 8 – 3 3 0 µ A ICCADC Analog supply current, analog circuits in powered up state. – – 25 mA IBATT(3) Battery supply current. – – 150 nA RIN_TERM(4) Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40). 28 40 55 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50). 35 50 65 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60). 44 60 83 Ω n Temperature diode idea lity factor. – 1.010 – – r Temperature diode series resistance. – 2 – Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. This measurement represents the die capacitance at the pad, not including the package. 3. Maximum value specified for worst case process at 25°C. 4. Termination resistance to a V CCO/2 level. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 5 Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) AC Voltage Overshoot % of UI at –40°C to 125°C AC Voltage Undershoot % of UI at –40°C to 125°C VCCO +0 . 5 5 1 0 0 –0.40 100 –0.45 61.7 –0.50 25.8 –0.55 11.0 V CCO + 0.60 46.6 –0.60 4.77 VCCO + 0.65 21.2 –0.65 2.10 VCCO + 0.70 9.75 –0.70 0.94 VCCO + 0.75 4.55 –0.75 0.43 VCCO + 0.80 2.15 –0.80 0.20 VCCO + 0.85 1.02 –0.85 0.09 VCCO + 0.90 0.49 –0.90 0.04 VCCO + 0.95 0.24 –0.95 0.02 Notes: 1. A total of 200 mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above V CCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. Table 5: Typical Quiescent Supply Current(1)(2)(3) Symbol Description Device Speed Grade Units1.0V 0.95V -2C -2I -1C -1I -1Q -1LI ICCINTQ Quiescent VCCINT supply current. X C 7 S 6 3 63 63 63 63 63 2 m A XC7S15 36 36 36 36 36 32 mA XC7S25 48 48 48 48 48 43 mA XC7S50 95 95 95 95 95 59 mA XC7S75 148 148 148 148 148 134 mA XC7S100 148 148 148 148 148 134 mA XA7S6 N/A 36 N/A 36 36 N/A mA XA7S15 N/A 36 N/A 36 36 N/A mA XA7S25 N/A 48 N/A 48 48 N/A mA XA7S50 N/A 95 N/A 95 95 N/A mA XA7S75 N/A 148 N/A 148 148 N/A mA XA7S100 N/A 148 N/A 148 148 N/A mA Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 6 ICCOQ Quiescent VCCO supply current. X C 7 S 6 111111 m A X C 7 S 1 5 111111 m A X C 7 S 2 5 111111 m A X C 7 S 5 0 111111 m A X C 7 S 7 5 444444 m A X C 7 S 1 0 0 444444 m A XA7S6 N/A 1 N/A 1 1 N/A mA XA7S15 N/A 1 N/A 1 1 N/A mA XA7S25 N/A 1 N/A 1 1 N/A mA XA7S50 N/A 1 N/A 1 1 N/A mA XA7S75 N/A 4 N/A 4 4 N/A mA XA7S100 N/A 4 N/A 4 4 N/A mA I CCAUXQ Quiescent VCCAUX supply current. X C 7 S 6 1 01 01 01 01 01 0 m A XC7S15 10 10 10 10 10 10 mA XC7S25 13 13 13 13 13 13 mA XC7S50 22 22 22 22 22 20 mA XC7S75 43 43 43 43 43 43 mA X C 7 S 1 0 0 4 34 34 34 34 34 3 m A XA7S6 N/A 10 N/A 10 10 N/A mA XA7S15 N/A 10 N/A 10 10 N/A mA XA7S25 N/A 13 N/A 13 13 N/A mA XA7S50 N/A 22 N/A 22 22 N/A mA XA7S75 N/A 43 N/A 43 43 N/A mA XA7S100 N/A 43 N/A 43 43 N/A mA Table 5: Typical Quiescent Supply Current(1)(2)(3) (Cont’d) Symbol Description Device Speed Grade Units1.0V 0.95V -2C -2I -1C -1I -1Q -1LI Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 7 Power-On/Off Power Supply Sequencing The recommended power-on sequence is V CCINT , VCCBRAM , VCCAUX , and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If V CCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supp ly and ramped simultaneously. If V CCAUX and V CCO have the same recommended voltage levels then both can be powe red by the same supply and ramped simultaneously. For V CCO voltages of 3.3V in HR I/O banks and config uration bank 0 the following conditions apply.

• The voltage difference between V CCO and V CCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to ma intain device reliability levels.
• The T VCCO2VCCAUX time can be allocated in any percenta ge between the power-on and power-off ramps. There is no recommended sequence for supplies not discussed in this section. ICCBRAMQ Quiescent VCCBRAM supply current. X C 7 S 6 111111 m A X C 7 S 1 5 111111 m A X C 7 S 2 5 111111 m A X C 7 S 5 0 222221 m A X C 7 S 7 5 999998 m A X C 7 S 1 0 0 999998 m A XA7S6 N/A 1 N/A 1 1 N/A mA XA7S15 N/A 1 N/A 1 1 N/A mA XA7S25 N/A 1 N/A 1 1 N/A mA XA7S50 N/A 2 N/A 2 2 N/A mA XA7S75 N/A 9 N/A 9 9 N/A mA XA7S100 N/A 9 N/A 9 9 N/A mA Notes: 1. Typical values are specified at nomina l voltage, 85°C junction temperature (Tj) with single-ended SelectIO™ resources. 2. Typical values are for blank co nfigured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. Use the Xilinx Power Estimator spreadsheet tool [Ref 6] to estimate static power consumption for conditions other than those specified. Table 5: Typical Quiescent Supply Current(1)(2)(3) (Cont’d) Symbol Description Device Speed Grade Units1.0V 0.95V -2C -2I -1C -1I -1Q -1LI Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 8 Table 6 shows the minimum current, in addition to I CCQ maximum, that is required by Spartan-7 devices for proper power-on and configuration. If the current minimums shown in Table 6 are met, the device powers on after all four supplies have passed through their po wer-on reset threshold voltages. The FPGA must not be configured until after V CCINT is applied. Once initialized and configured, use the Xilinx Power Estimator spreadsheet tool [Ref 6] to estimate current drain on these supplies. Table 6: Power-On Current Device I CCINTMIN ICCAUXMIN ICCOMIN ICCBRAMMIN Units XC7S6 I CCINTQ + 120 I CCAUXQ + 40 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XC7S15 I CCINTQ + 120 I CCAUXQ + 40 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XC7S25 I CCINTQ + 120 I CCAUXQ + 40 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XC7S50 I CCINTQ + 120 I CCAUXQ + 40 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XC7S75 I CCINTQ + 300 I CCAUXQ + 140 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XC7S100 I CCINTQ + 300 I CCAUXQ + 140 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XA7S6 I CCINTQ + 120 I CCAUXQ + 40 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XA7S15 I CCINTQ + 120 I CCAUXQ + 40 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XA7S25 I CCINTQ + 120 I CCAUXQ + 40 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XA7S50 I CCINTQ + 120 I CCAUXQ + 40 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XA7S75 I CCINTQ + 300 I CCAUXQ + 140 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA XA7S100 I CCINTQ + 300 I CCAUXQ + 140 I CCOQ + 40 mA per bank I CCBRAMQ + 60 mA Table 7: Power Supply Ramp Time Symbol Description Conditions Min Max Units TVCCINT Ramp time from GND to 90% of VCCINT.0 . 2 5 0 m s TVCCO Ramp time from GND to 90% of VCCO.0 . 2 5 0 m s TVCCAUX Ramp time from GND to 90% of VCCAUX.0 . 2 5 0 m s TVCCBRAM Ramp time from GND to 90% of VCCBRAM.0 . 2 5 0 m s TVCCO2VCCAUX Allowed time per power cycle for VCCO –V CCAUX > 2.625V. TJ =1 2 5 ° C(1) – 300 ms TJ =1 0 0 ° C(1) – 500 ms TJ =8 5 ° C(1) – 800 ms Notes: 1. Based on 240,000 power cycles with a nominal V CCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 9 DC Input and Output Levels Values for V IL and V IH are recommended input voltages. Values for I OL and I OH are guaranteed over the recommended operating conditions at the V OL and V OH test points. Only selected standards are tested. These are chosen to ensure that all standards meet th eir specifications. The selected standards are tested at a minimum V CCO with the respective V OL and V OH voltage levels shown. Other standards are sample tested. Table 8: SelectIO DC Input and Output Levels(1)(2)(3) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min LVCMOS12 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.400 V CCO –0 . 4 0 0 Note 4 Note 4 LVCMOS15 –0.300 35% V CCO 65% VCCO VCCO + 0.300 25% V CCO 75% VCCO Note 5 Note 5 LVCMOS18 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.450 V CCO –0 . 4 5 0 Note 6 Note 6 MOBILE_DDR –0.300 20% V CCO 80% VCCO VCCO + 0.300 10% V CCO 90% VCCO 0.10 –0.10 PCI33_3 –0.400 30% V CCO 50% VCCO VCCO + 0.500 10% V CCO 90% VCCO 1.50 –0.50 Notes: 1. Tested according to relevant specifications. 2. 3.3V and 2.5V standards are only supported in HR I/O banks. 3. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3]. 4. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks. 5. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks. 6. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 10 Table 9: Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) VID(2) VOCM(3) VOD(4) Min Typ Max Min Typ Max Min Typ Max Min Typ Max Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage (Q – Q). 3. V OCM is the output common mode voltage. 4. V OD is the output differential voltage (Q – Q). 5. V OD for BLVDS will vary significantly depending on topology and loading. Table 10: Complementary Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH V, Min V, Typ V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage (Q – Q). 3. V OL is the single-ended low-output voltage. 4. V OH is the single-ended high-output voltage. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 11 LVDS DC Specifications (LVDS_25) Table 11: LVDS_25 DC Specifications(1) Symbol DC Parameter Conditions Min Typ Max Units VCCO Supply voltage. 2.375 2.500 2.625 V VOH Output High voltage for Q and Q.R T =1 0 0Ω across Q and Q signals. – – 1.675 V VOL Output Low voltage for Q and Q.R T =1 0 0Ω across Q and Q signals. 0.700 – – V VODIFF Differential output voltage: (Q – Q), Q = High (Q – Q), Q =H i g h RT =1 0 0Ω across Q and Q signals. 247 350 600 mV VIDIFF Differential input voltage: (Q – Q), Q = High (Q – Q), Q =H i g h 100 350 600 mV VICM Input common-mode voltage. 0.300 1.200 1.500 V Notes: 1. Differential inputs for LVDS_25 can be placed in banks with V CCO levels that are different from the required level for outputs. Consult the 7 Series FPGAs SelectIO Resources User Guide (UG471) [Ref 3] for more information. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 12 AC Switching Characteristics All values represented in this data sheet are based on the speed specifications from the Vivado® Design Suite as outlined in Table 12 . Switching characteristics are specified on a per-spee d-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows. Advance Product Specification These specifications are based on simulations only an d are typically available so on after device design specifications are frozen. Although speed grades with this designation are consider ed relatively stable and conservative, some under-rep orting might still occur. Preliminary Product Specification These specifications are based on complete ES (engin eering sample) silicon characterization. Devices and speed grades with this designation are intended to gi ve a better indication of the expected performance of production silicon. The probability of under-repo rting delays is greatly reduced as compared to Advance data. Production Product Specification These specifications are released once enough producti on silicon of a particular device family member has been characterized to provide full correlation be tween specifications and devices over numerous production lots. There is no under-reporting of dela ys, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Testing of AC Switching Characteristics Internal timing parameters are derived from meas uring internal test patt erns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. For more specific, more precise, and worst-case guar anteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Spartan-7 FPGAs. Table 12: Speed Specification Version By Device

2018.2.1 Device

1.23 XC7S6, XC7S15, XC7S25, XC7S50, XC7S75, XC7S100

1.16 XA7S6, XA7S15, XA7S25, XA7S50, XA7S75, XA7S100

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 13 Speed Grade Designations Since individual family members are produced at di fferent times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Spartan-7 device on a per speed grade basis. Production Silicon and Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with th e correct label (Advance, Prelimin ary, Production). Any labeling discrepancies are corrected in subseq uent speed specification releases. Table 14 lists the production released Spartan-7 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for producti on. All subsequent releases of software and speed specifications are valid. Table 13: Spartan-7 Device Speed Grade Designations Device Speed Grade, Temperature Range, and VCCINT Operating Voltage Advance Preliminary Production Notes: 1. The lowest power -1LI devices, where V CCINT = 0.95V, are listed in the Vivado Design Suite as -1IL. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 14 Performance Characteristics This section provides the performance characte ristics of some common functions and designs implemented in Spartan-7 FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics, page 12 . Table 14: Spartan-7 Device Production Software and Speed Specification Release Device VCCINT Operating Voltage, Speed Grade, and Temperature Range 1.0V 0.95V -2C -2I -1C -1I -1Q -1LI XC7S6 Vivado tool s 2018.2 v1.22 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.2 v1.22 XC7S15 Vivado tools 2018.2 v1.22 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.2 v1.22 XC7S25 Vivado tools 2017.4 v1.20 Vivado tools 2018.1 v1.21 Vivado tools 2017.4 v1.20 XC7S50 Vivado tools 2017.2 v1.17 Vivado tools 2017.3 v1.19 Vivado tools 2017.2 v1.17 XC7S75 Vivado tools 2018.1 v1.21 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.1 v1.21 XC7S100 Vivado tool s 2018.1 v1.21 Vivado tools 2018.2.1 v1.23 Vivado tools 2018.1 v1.21 XA7S6 N/A Vivado tools XA7S15 N/A Vivado tools XA7S25 N/A Vivado tools 2018.1 v1.15 N/A Vivado tools 2018.1 v1.15 N/A XA7S50 N/A Vivado tools 2017.3 v1.12 N/A Vivado tools 2017.3 v1.12 N/A XA7S75 N/A Vivado tools XA7S100 N/A Vivado tools Table 15: Networking Applications Interface Performances

Description

VCCINT Operating Voltage, Speed Grade, and Temperature Range Units1.0V 0.95V -2C/-2I -1C/-1I/-1Q -1LI SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) 680 600 600 Mb/s DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) 1250 950 950 Mb/s SDR LVDS receiver(1) 680 600 600 Mb/s Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 15 IOB Pad Input/Output/3-State Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.

• TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capa bility of the SelectIO input buffer.
• TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the ca pability of the SelectIO output buffer.
• TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The dela y varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM termination turn-on time is always faster than T IOTP when the INTERMDISABLE pin is used. DDR LVDS receiver(1) 1250 950 950 Mb/s Notes: 1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance. Table 16: Maximum Physical Interface (PHY) Rate for Memory Interface IP available with the Memory Interface Generator(1) Memory Standard VCCINT Operating Voltage, Speed Grade, and Temperature Range Units1.0V 0.95V -2C/-2I -1C/-1I/-1Q -1LI 4:1 Memory Controllers DDR3 800 (2) 667 667 Mb/s DDR3L 800 (2) 667 667 Mb/s DDR2 800 (2) 667 667 Mb/s 2:1 Memory Controllers DDR3 800 (2) 667 667 Mb/s DDR3L 800 (2) 667 667 Mb/s DDR2 800 (2) 667 667 Mb/s LPDDR2 667 533 533 Mb/s Notes: 1. V REF tracking is required. For more information, see the Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586) [Ref 7]. 2. The maximum PHY rate is 667 Mb/s in the FTGB196 package. Table 15: Networking Applications Interface Performances (Cont’d)

VCCINT Operating Voltage, Speed Grade, and Temperature Range Units1.0V 0.95V -2C/-2I -1C/-1I/-1Q -1LI Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 16 Table 17: IOB High Range (HR) Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Units VCCINT Operating Voltage and Speed Grade Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 17 Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units VCCINT Operating Voltage and Speed Grade Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 18 Table 18 specifies the values of T IOTPHZ and TIOIBUFDISABLE . TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). T IOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than T IOTPHZ when the INTERMDISABLE pin is used. Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units VCCINT Operating Voltage and Speed Grade Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 19 Table 18: IOB 3-state Output Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L TIOTPHZ T input to pad high-impedance. 2.19 2.37 2.37 ns TIOIBUFDISABLE IBUF turn-on time from IBUFDISABLE to O output. 2.30 2.60 2.60 ns Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 20 I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 19 shows the test setup parameters used for measuring input delay. Table 19: Input Delay Measurement Methodology Description I/O Standard Attribute V L(1) VH(1) VMEAS(3)(5) VREF(2)(4) LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 – LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 – LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 – LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 – LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 – LVTTL, 3.3V LVTTL 0.1 3.2 1.65 – MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9 – PCI33, 3.3V PCI33_3 0.1 3.2 1.65 – HSTL (high-speed transceiver logic), Class I, 1.2V HSTL_I_12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 HSTL, Class I & II, 1.5V HSTL_I, HSTL_II V REF –0 . 6 5 V REF +0 . 6 5 V REF 0.75 HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 VREF –0 . 8 V REF +0 . 8 V REF 0.90 HSUL (high-speed unterminated logic), 1.2V HSUL_12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 SSTL (stub-terminated transceiver logic), 1.2V SSTL12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 SSTL, 1.35V SSTL135, SSTL135_R V REF –0 . 5 7 5 VREF +0 . 5 7 5 V REF 0.675 SSTL, 1.5V SSTL15, SSTL15_R V REF –0 . 6 5 V REF +0 . 6 5 V REF 0.75 SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II V REF –0 . 8 V REF +0 . 8 V REF 0.90 DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I, DIFF_HSTL_II 0.75 – 0.125 0.75 + 0.125 0 (5) – DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_SSTL135/ DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 0.675 – 0.125 0.675 + 0.125 0 (5) – DIFF_SSTL15/ DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 0.75 – 0.125 0.75 + 0.125 0 (5) – DIFF_SSTL18_I/ DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 0.9 – 0.125 0.9 + 0.125 0 (5) – Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 21 PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0 (5) – RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0 (5) – TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0 (5) – Notes: 1. Input waveform switches between V L and VH. 2. Measurements are made at ty pical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 3. Input voltage level from which measurement starts. 4. This is an input voltage reference that bears no relation to the V REF / VMEAS parameters found in IBIS models and/or noted in Figure 1. 5. The value given is the differential input voltage. Table 19: Input Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute V L(1) VH(1) VMEAS(3)(5) VREF(2)(4) Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 23 Table 20: Output Delay Measurement Methodology Description I/O Standard Attribute RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0 LVCMOS, 1.5V LVCMOS15 1M 0 0.75 0 LVCMOS, 1.8V LVCMOS18 1M 0 0.9 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0 LVTTL, 3.3V LVTTL 1M 0 1.65 0 PCI33, 3.3V PCI33_3 25 10 1.65 0 HSTL (high-speed transceiver logic), Class I, 1.2V HSTL_I_12 50 0 V REF 0.6 HSTL, Class I, 1.5V HSTL_I 50 0 V REF 0.75 HSTL, Class II, 1.5V HSTL_II 25 0 V REF 0.75 HSTL, Class I, 1.8V HSTL_I_18 50 0 V REF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 V REF 0.9 HSUL (high-speed unterminated logic), 1.2V HSUL_12 50 0 V REF 0.6 SSTL12, 1.2V SSTL12 50 0 V REF 0.6 SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 V REF 0.675 SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 V REF 0.75 SSTL (stub-series terminated logic), Class I & Class II, 1.8V SSTL18_I, SSTL18_II 50 0 V REF 0.9 DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 V REF 0.9 DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 V REF 0.6 DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 V REF 0.75 DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 50 0 V REF 0.9 DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 V REF 0.6 DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 V REF 0.675 DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R 50 0 V REF 0.75 DIFF_SSTL18, Class I & II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II 50 0 V REF 0.9 LVDS, 2.5V LVDS_25 100 0 0 (2) 0 BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0 (2) 0 Mini LVDS, 2.5V MINI_LVDS_25 100 0 0 (2) 0 PPDS_25 PPDS_25 100 0 0 (2) 0 RSDS_25 RSDS_25 100 0 0 (2) 0 TMDS_33 TMDS_33 50 0 0 (2) 3.3 Notes: 1. C REF is the capacitance of the probe, nominally 0 pF. 2. The value given is the differential output voltage. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 24 Input/Output Logic Switching Characteristics Table 21: ILOGIC Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Setup/Hold TIDOCK/TIOCKD D pin setup/hold with respect to CLK without TIDOCKD/TIOCKDD DDLY pin setup/hold with respect to CLK (using Combinatorial TIDI D pin to O pin propagation delay, no delay. 0.11 0.13 0.13 ns TIDID DDLY pin to O pin propagation delay (using IDELAY). 0.12 0.14 0.14 ns Sequential Delays TIDLO D pin to Q1 pin using flip-flop as a latch without delay. 0.44 0.51 0.51 ns TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY). 0.44 0.51 0.51 ns TICKQ CLK to Q outputs. 0.57 0.66 0.66 ns TRQ_ILOGIC SR pin to OQ/TQ out. 1.08 1.32 1.32 ns TGSRQ_ILOGIC Global set/reset to Q outputs. 7.60 10.51 10.51 ns Set/Reset TRPW_ILOGIC Minimum pulse width, SR inputs. 0.72 0.72 0.72 ns, Min Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 25 Table 22: OLOGIC Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Setup/Hold Combinatorial TODQ D1 to OQ out or T1 to TQ out. 0.96 1.16 1.16 ns Sequential Delays TOCKQ CLK to OQ/TQ out. 0.49 0.56 0.56 ns TRQ_OLOGIC SR pin to OQ/TQ out. 0.80 0.95 0.95 ns TGSRQ_OLOGIC Global set/reset to Q outputs. 7.60 10.51 10.51 ns Set/Reset TRPW_OLOGIC Minimum pulse width, SR inputs. 0.74 0.74 0.74 ns, Min Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 26 Input Serializer/Deserializer Switching Characteristics Table 23: ISERDES Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin setup/hold with respect to T ISCCK_CE/ TISCKC_CE CE pin setup/hold with respect to CLK T ISCCK_CE2/ TISCKC_CE2 CE pin setup/hold with respect to CLKDIV Setup/Hold for Data Lines TISDCK_D/ TISCKD_D TISDCK_DDLY/ TISCKD_DDLY DDLY pin setup/hold with respect to CLK (using IDELAY). TISDCK_D_DDR/ TISCKD_D_DDR D pin setup/hold with respect to CLK at T ISDCK_DDLY_DDR/ TISCKD_DDLY_DDR D pin setup/hold with respect to CLK at DDR mode (using IDELAY). Sequential Delays TISCKO_Q CLKDIV to out at Q pin. 0.54 0.66 0.66 ns Propagation Delays TISDO_DO D input to DO output pin. 0.11 0.13 0.13 ns Notes: 1. Recorded at 0 tap value. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 27 Output Serializer/Deserializer Switching Characteristics Table 24: OSERDES Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Setup/Hold TOSDCK_D/ TOSCKD_D TOSDCK_T/ TOSCKD_T TOSDCK_T2/ TOSCKD_T2 TOSCCK_OCE/ TOSCKC_OCE TOSCCK_S SR (reset) input setup with respect to CLKDIV. 0.52 0.85 0.85 ns TOSCCK_TCE/ TOSCKC_TCE Sequential Delays TOSCKO_OQ Clock to out from CLK to OQ. 0.42 0.48 0.48 ns TOSCKO_TQ Clock to out from CLK to TQ. 0.49 0.56 0.56 ns Combinatorial TOSDO_TTQ T input to TQ out. 0.92 1.11 1.11 ns Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 28 Input/Output Delay Switching Characteristics Table 25: Input/Output Delay Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L IDELAYCTRL TDLYCCO_RDY Reset to ready for IDELAYCTRL. 3.67 3.67 3.67 µs FIDELAYCTRL_REF Attribute REFCLK frequency = 400.00.(1) 400.00 N/A N/A MHz IDELAYCTRL_REF_ PRECISION REFCLK precision ±10 ±10 ±10 MHz TIDELAYCTRL_RPW Minimum reset pulse width. 59.28 59.28 59.28 ns IDELAY TIDELAYRESOLUTION IDELAY chain delay resolution. 1/(32 x 2 x F REF)µ s TIDELAYPAT_JIT Pattern dependent period jitter in delay chain for clock pattern.(2) 000 ps per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23).(3) ±5 ±5 ±5 ps per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23).(4) ±9 ±9 ±9 ps per tap TIDELAY_CLK_MAX Maximum frequency of CLK input to IDELAY. 680.00 600.00 600.00 MHz TIDCCK_CE / TIDCKC_CE TIDCCK_INC/ TIDCKC_INC TIDCCK_RST/ TIDCKC_RST TIDDO_IDATAIN Propagation delay through IDELAY. Note 5 Note 5 Note 5 ps Notes: 1. Average tap delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps. 2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. 3. When HIGH_PERFORMANCE mode is set to TRUE. 4. When HIGH_PERFORMANCE mode is set to FALSE. 5. Delay depends on IDELAY tap setting. See the timing report for actual values. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 29 Table 26: IO_FIFO Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L IO_FIFO Clock to Out Delays TOFFCKO_DO RDCLK to Q outputs. 0.60 0.68 0.68 ns TCKO_FLAGS Clock to IO_FIFO flags. 0.61 0.77 0.77 ns Setup/Hold TIFFCCK_WREN/ TIFFCKC_WREN TOFFCCK_RDEN/ TOFFCKC_RDEN Minimum Pulse Width TPWH_IO_FIFO RESET, RDCLK, WRCLK. 2.15 2.15 2.15 ns TPWL_IO_FIFO RESET, RDCLK, WRCLK. 2.15 2.15 2.15 ns Maximum Frequency F MAX RDCLK and WRCLK. 200.00 200.00 200.00 MHz Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 30 CLB Switching Characteristics Table 27: CLB Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Combinatorial Delays TILO An – Dn LUT address to A. 0.11 0.13 0.13 ns, Max TILO_2 An – Dn LUT address to AMUX/CMUX. 0.30 0.36 0.36 ns, Max TILO_3 An – Dn LUT address to BMUX_A. 0.46 0.55 0.55 ns, Max TITO An – Dn inputs to A – D Q outputs. 1.05 1.27 1.27 ns, Max TAXA AX inputs to AMUX output. 0.69 0.84 0.84 ns, Max TAXB AX inputs to BMUX output. 0.66 0.83 0.83 ns, Max TAXC AX inputs to CMUX output. 0.68 0.82 0.82 ns, Max TAXD AX inputs to DMUX output. 0.75 0.90 0.90 ns, Max TBXB BX inputs to BMUX output. 0.57 0.69 0.69 ns, Max TBXD BX inputs to DMUX output. 0.69 0.82 0.82 ns, Max TCXC CX inputs to CMUX output. 0.48 0.58 0.58 ns, Max TCXD CX inputs to DMUX output. 0.59 0.71 0.71 ns, Max TDXD DX inputs to DMUX output. 0.58 0.70 0.70 ns, Max Sequential Delays TCKO Clock to AQ – DQ outputs. 0.44 0.53 0.53 ns, Max TSHCKO Clock to AMUX – DMUX outputs. 0.53 0.66 0.66 ns, Max Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TDICK/TCKDI AX – DX input through MUXs and/or carry logic to TCECK_CLB/ TCKCE_CLB Set/Reset TSRMIN SR input minimum pulse width. 0.78 1.04 1.04 ns, Min TRQ Delay from SR input to AQ – DQ flip-flops. 0.59 0.71 0.71 ns, Max TCEO Delay from CE input to AQ – DQ flip-flops. 0.58 0.70 0.70 ns, Max FTOG Toggle frequency (for expor t c o n t r o l ) . 1 2 8 61 0 9 81 0 9 8 M H z Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 31 CLB Distributed RAM Switching Characteristics (SLICEM Only) CLB Shift Register Switching Characteristics (SLICEM Only) Table 28: CLB Distributed RAM Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Sequential Delays TSHCKO Clock to A – B outputs. 1.09 1.32 1.32 ns, Max TSHCKO_1 Clock to AMUX – BMUX outputs. 1.53 1.86 1.86 ns, Max Setup and Hold Times Before/After Clock CLK TAS_LRAM/TAH_LRAM Address An inputs through MUXs and/or Clock CLK TMPW_LRAM Minimum pulse width. 1.13 1.25 1.25 ns, Min TMCP Minimum clock period. 2 . 2 62 . 5 02 . 5 0 n s , M i n Notes: 1. T SHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path. Table 29: CLB Shift Register Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Sequential Delays TREG Clock to A – D outputs. 1.33 1.61 1.61 ns, Max TREG_MUX Clock to AMUX – DMUX output. 1.77 2.15 2.15 ns, Max TREG_M31 Clock to DMUX output via M31 output. 1.23 1.46 1.46 ns, Max Setup and Hold Times Before/After Clock CLK TCECK_SHFREG/ TCKCE_SHFREG Clock CLK TMPW_SHFREG Minimum pulse width. 0.86 0.98 0.98 ns, Min Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 32 Block RAM and FIFO Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Block RAM and FIFO Clock-to-Out Delays TRCKO_DO and TRCKO_DO_REG Clock CLK to DOUT output (without output register).(1)(2) 2.13 2.46 2.46 ns, Max Clock CLK to DOUT output (with output register).(3)(4) 0.74 0.89 0.89 ns, Max TRCKO_DO_ECC and TRCKO_DO_ECC_REG Clock CLK to DOUT output with ECC (without output register). Clock CLK to DOUT output with ECC (with output register).(3)(4) 0.81 0.94 0.94 ns, Max TRCKO_DO_CASCOUT and TRCKO_DO_CASCOUT_REG Clock CLK to DOUT output with cascade (without output register).(1) 2.88 3.30 3.30 ns, Max Clock CLK to DOUT output with cascade (with output register).(3) 1.28 1.46 1.46 ns, Max TRCKO_FLAGS Clock CLK to FIFO flags outputs.(5) 0.87 1.05 1.05 ns, Max TRCKO_POINTERS Clock CLK to FIFO pointers outputs.(6) 1.02 1.15 1.15 ns, Max TRCKO_PARITY_ECC Clock CLK to ECCPARITY in ECC encode only mode. 0.85 0.94 0.94 ns, Max TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG Clock CLK to BITERR (without output register). 2.81 3.55 3.55 ns, Max Clock CLK to BITERR (with output register). 0.76 0.89 0.89 ns, Max T RCKO_RDADDR_ECC and TRCKO_RDADDR_ECC_REG Clock CLK to RDADDR output with ECC (without output register). 0.88 1.07 1.07 ns, Max Clock CLK to RDADDR output with ECC (with output register). 0.93 1.08 1.08 ns, Max Setup and Hold Times Before/After Clock CLK TRCCK_ADDRA/ TRCKC_ADDRA TRDCK_DI_WF_NC/ TRCKD_DI_WF_NC Data input setup/hold time when block RAM is configured in WRITE_FIRST or NO_CHANGE mode. (8) TRDCK_DI_RF/ TRCKD_DI_RF Data input setup/hold time when block RAM is configured in READ_FIRST mode.(8) TRDCK_DI_ECC/ TRCKD_DI_ECC DIN inputs with block RAM ECC in standard mode. TRDCK_DI_ECCW/ TRCKD_DI_ECCW DIN inputs with block RAM ECC encode only. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 33 TRDCK_DI_ECC_FIFO/ TRCKD_DI_ECC_FIFO DIN inputs with FIFO ECC in standard mode. TRCCK_INJECTBITERR/ TRCKC_INJECTBITERR Inject single/double bit error in ECC T TRCCK_REGCE/ TRCKC_REGCE TRCCK_RSTREG/ TRCKC_RSTREG TRCCK_RSTRAM/ TRCKC_RSTRAM TRCCK_WEA/TRCKC_WEA Write enable (WE) input (block RAM TRCCK_WREN/ TRCKC_WREN TRCCK_RDEN/ TRCKC_RDEN Reset Delays TRCO_FLAGS Reset RST to FIFO flags/pointers.(9) 0.98 1.10 1.10 ns, Max TRREC_RST/TRREM_RST FIFO reset recovery and removal Maximum Frequency FMAX_BRAM_WF_NC Block RAM (write first and no change modes) when not in SDP RF mode. 460.83 388.20 388.20 MHz FMAX_BRAM_RF_ PERFORMANCE Block RAM (read first, performance mode) when in SDP RF mode but no address overlap between port A and port B. 460.83 388.20 388.20 MHz F MAX_BRAM_RF_ DELAYED_WRITE Block RAM (read first, delayed write mode) when in SDP RF mode and there is possibility of overlap between port A and port B addresses. 404.53 339.67 339.67 MHz F MAX_CAS_WF_NC Block RAM cascade (write first, no change mode) when cascade but not in RF mode. 418.59 345.78 345.78 MHz F MAX_CAS_RF_ PERFORMANCE Block RAM cascade (read first, performance mode) when in cascade with RF mode and no possibility of address overlap/one port is disabled. 418.59 345.78 345.78 MHz Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 34 FMAX_CAS_RF_ DELAYED_WRITE When in cascade RF mode and there is a possibility of address overlap between port A and port B. 362.19 297.35 297.35 MHz FMAX_FIFO FIFO in all modes without ECC. 460.83 388.20 388.20 MHz FMAX_ECC Block RAM and FIFO in ECC configuration. 365.10 297.53 297.53 MHz Notes: 1. T RCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. 2. These parameters also apply to synchronous FIFO with DO_REG = 0. 3. T RCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. 4. These parameters also apply to multi-rate (asy nchronous) and synchronous FIFO with DO_REG = 1. 5. T RCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. 6. T RCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. 7. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 8. These parameters include both A and B inputs as well as the parity inputs of A and B. 9. T RCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 10. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK). Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 35 DSP48E1 Switching Characteristics Table 31: DSP48E1 Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units 1.0V 0.95V -2 -1 -1L Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK. 0.30/ 0.13 0.37/ 0.14 0.37/ 0.14 ns TDSPDCK_B_BREG/ TDSPCKD_B_BREG B input to B register CLK. 0.38/ 0.16 0.45/ 0.18 0.45/ 0.18 ns TDSPDCK_C_CREG/ TDSPCKD_C_CREG C input to C register CLK. 0.20/ 0.19 0.24/ 0.21 0.24/ 0.21 ns TDSPDCK_D_DREG/ TDSPCKD_D_DREG D input to D register CLK. 0.32/ 0.27 0.42/ 0.27 0.42/ 0.27 ns TDSPDCK_ACIN_AREG/ TDSPCKD_ACIN_AREG ACIN input to A register CLK. 0.27/ 0.13 0.32/ 0.14 0.32/ 0.14 ns TDSPDCK_BCIN_BREG/ TDSPCKD_BCIN_BREG BCIN input to B register CLK. 0.29/ 0.16 0.36/ 0.18 0.36/ 0.18 ns Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{A, B}_MREG_MULT/ {A, B} input to M register CLK using multiplier. 2.76/ –0.01 3.29/ –0.01 3.29/ –0.01 ns T DSPDCK_{A, D}_ADREG/ TDSPCKD_{A, D}_ADREG {A, D} input to AD register CLK. 1.48/ –0.02 1.76/ –0.02 1.76/ –0.02 ns Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{A, B}_PREG_MULT/ TDSPCKD_{A, B} _PREG_MULT {A, B} input to P register CLK using multiplier. 4.60/ –0.28 5.48/ –0.28 5.48/ –0.28 ns T DSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT D input to P register CLK using multiplier. 4.50/ –0.73 5.35/ –0.73 5.35/ –0.73 ns TDSPDCK_{A, B} _PREG/ TDSPCKD_{A, B} _PREG A or B input to P register CLK not using multiplier. 1.98/ –0.28 2.35/ –0.28 2.35/ –0.28 ns T DSPDCK_C_PREG/ TDSPCKD_C_PREG C input to P register CLK not using multiplier. 1.76/ –0.26 2.10/ –0.26 2.10/ –0.26 ns TDSPDCK_PCIN_PREG/ TDSPCKD_PCIN_PREG PCIN input to P register CLK. 1.51/ –0.15 1.80/ –0.15 1.80/ –0.15 ns Setup and Hold Times of the CE Pins TDSPDCK_{CEA;CEB}_{AREG;BREG}/ {CEA; CEB} input to {A; B} register CLK. 0.42/ 0.08 0.52/ 0.11 0.52/ 0.11 ns TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG CEC input to C register CLK. 0.34/ 0.11 0.42/ 0.13 0.42/ 0.13 ns TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG CED input to D register CLK. 0.43/ –0.03 0.52/ –0.03 0.52/ –0.03 ns Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 36 TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG CEM input to M register CLK. 0.21/ 0.20 0.27/ 0.23 0.27/ 0.23 ns TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG CEP input to P register CLK. 0.43/ 0.01 0.53/ 0.01 0.53/ 0.01 ns Setup and Hold Times of the RST Pins TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG} {RSTA, RSTB} input to {A, B} register CLK. 0.46/ 0.13 0.55/ 0.15 0.55/ 0.15 ns TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG RSTC input to C register CLK. 0.08/ 0.11 0.09/ 0.12 0.09/ 0.12 ns TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG RSTD input to D register CLK 0.50/ 0.08 0.59/ 0.09 0.59/ 0.09 ns TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG RSTM input to M register CLK 0.23/ 0.24 0.27/ 0.28 0.27/ 0.28 ns TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG RSTP input to P register CLK 0.30/ 0.01 0.35/ 0.01 0.35/ 0.01 ns Combinatorial Delays from Input Pins to Output Pins TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output using multiplier. 4.35 5.18 5.18 ns TDSPDO_D_P_MULT D input to P output using multiplier. 4.26 5.07 5.07 ns TDSPDO_B_P B input to P output not using multiplier. 1.75 2.08 2.08 ns TDSPDO_C_P C input to P output. 1.53 1.82 1.82 ns Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT, BCOUT} output. 0.63 0.74 0.74 ns TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to CARRYCASCOUT output using multiplier. 4.65 5.54 5.54 ns TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT output using multiplier. 4.54 5.40 5.40 ns TDSPDO_{A, B}_CARRYCASCOUT {A, B} input to CARRYCASCOUT output not using multiplier. 2.03 2.41 2.41 ns TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT output. 1.81 2.15 2.15 ns Combinatorial Delays from Cascading Input Pins to All Output Pins TDSPDO_ACIN_P_MULT ACIN input to P output using multiplier. 4.19 5.00 5.00 ns TDSPDO_ACIN_P ACIN input to P output not using multiplier. 1.57 1.88 1.88 ns TDSPDO_ACIN_ACOUT ACIN input to ACOUT output. 0.44 0.53 0.53 ns TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to CARRYCASCOUT output using multiplier. 4.47 5.33 5.33 ns TDSPDO_ACIN_CARRYCASCOUT ACIN input to CARRYCASCOUT output not using multiplier. 1.85 2.21 2.21 ns TDSPDO_PCIN_P PCIN input to P output. 1.28 1.52 1.52 ns Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade Units 1.0V 0.95V -2 -1 -1L Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 37 TDSPDO_PCIN_CARRYCASCOUT PCIN input to CARRYCASCOUT output. 1.56 1.85 1.85 ns Clock to Outs from Output Register Clock to Output Pins TDSPCKO_P_PREG CLK PREG to P output. 0.37 0.44 0.44 ns TDSPCKO_CARRYCASCOUT_PREG CLK PREG to CARRYCASCOUT output. 0.59 0.69 0.69 ns Clock to Outs from Pipeline Register Clock to Output Pins TDSPCKO_P_MREG CLK MREG to P output. 1.93 2.31 2.31 ns TDSPCKO_CARRYCASCOUT_MREG CLK MREG to CARRYCASCOUT output. 2.21 2.64 2.64 ns TDSPCKO_P_ADREG_MULT CLK ADREG to P output using multiplier. 3.10 3.69 3.69 ns TDSPCKO_CARRYCASCOUT_ADREG_MULT CLK ADREG to CARRYCASCOUT output using multiplier. 3.38 4.02 4.02 ns Clock to Outs from Input Register Clock to Output Pins TDSPCKO_P_AREG_MULT CLK AREG to P output using multiplier. 4.51 5.37 5.37 ns TDSPCKO_P_BREG CLK BREG to P output not using multiplier. 1.87 2.22 2.22 ns TDSPCKO_P_CREG CLK CREG to P output not using multiplier. 1.93 2.30 2.30 ns TDSPCKO_P_DREG_MULT CLK DREG to P output using multiplier. 4.48 5.32 5.32 ns Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUT; BCOUT}_ {AREG; BREG} CLK (ACOUT, BCOUT) to {A,B} register output. 0.73 0.87 0.87 ns TDSPCKO_CARRYCASCOUT_ {AREG, BREG}_MULT CLK (AREG, BREG) to CARRYCASCOUT output using multiplier. 4.79 5.70 5.70 ns TDSPCKO_CARRYCASCOUT_ BREG CLK BREG to CARRYCASCOUT output not using multiplier. 2.15 2.55 2.55 ns TDSPCKO_CARRYCASCOUT_ DREG_MULT CLK DREG to CARRYCASCOUT output using multiplier. 4.76 5.65 5.65 ns TDSPCKO_CARRYCASCOUT_ CREG CLK CREG to CARRYCASCOUT output. 2.21 2.63 2.63 ns Maximum Frequency FMAX With all registers used. 550.66 464.25 464.25 MHz FMAX_PATDET With pattern detector. 465.77 392.93 392.93 MHz FMAX_MULT_NOMREG Two register multiply without MREG. 305.62 257.47 257.47 MHz FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect. 277.62 233.92 233.92 MHz FMAX_PREADD_MULT_NOADREG Without ADREG. 346.26 290.44 290.44 MHz FMAX_PREADD_MULT_NOADREG_PATDET Without ADREG with pattern detect. 346.26 290.44 290.44 MHz FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG). 227.01 190.69 190.69 MHz FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect. 211.15 177.43 177.43 MHz Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade Units 1.0V 0.95V -2 -1 -1L Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 38 Clock Buffers and Networks Table 32: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L TBCCKO_O(2) BUFGCTRL delay from I0/I1 to O. 0.09 0.10 0.10 ns Maximum Frequency FMAX_BUFG Global clock tree (BUFG). 628.00 464.00 464.00 MHz Notes: 1. T BCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. 2. T BGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. Table 33: Input/Output Clock Switching Characteristics (BUFIO) Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L TBIOCKO_O Clock to out delay from I to O. 1.26 1.54 1.54 ns Maximum Frequency FMAX_BUFIO I/O clock tree (BUFIO). 680.00 600.00 600.00 MHz Table 34: Regional Clock Buffer Switching Characteristics (BUFR) Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L TBRCKO_O Clock to out delay from I to O. 0.76 0.99 0.99 ns TBRCKO_O_BYP Clock to out delay from I to O with Divide Bypass attribute set. 0.39 0.52 0.52 ns TBRDO_O Propagation delay from CLR to O. 0.85 1.09 1.09 ns Maximum Frequency FMAX_BUFR(1) Regional clock tree (BUFR). 375.00 315.00 315.00 MHz Notes: 1. The maximum input frequency to the BUFR is the BUFIO F MAX frequency. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 39 Table 35: Horizontal Clock Buffer Switching Characteristics (BUFH) Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L TBHCKO_O BUFH delay from I to O. 0.11 0.13 0.13 ns Maximum Frequency FMAX_BUFH Horizontal clock buffer (BUFH). 628.00 464.00 464.00 MHz Table 36: Duty Cycle Distortion and Clock-Tree Skew Symbol Description Device VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L TDCD_CLK Global clock tree duty-cycle distortion.(1) All 0.20 0.20 0.20 ns TCKSKEW Global clock tree skew.(2) XC7S6 0.05 0.06 0.06 ns XC7S15 0.05 0.06 0.06 ns XC7S25 0.26 0.26 0.26 ns XC7S50 0.26 0.26 0.26 ns XC7S75 0.33 0.36 0.36 ns XC7S100 0.33 0.36 0.36 ns XA7S6 0.05 0.06 N/A ns XA7S15 0.05 0.06 N/A ns XA7S25 0.26 0.26 N/A ns XA7S50 0.26 0.26 N/A ns XA7S75 0.33 0.36 N/A ns XA7S100 0.33 0.36 N/A ns T DCD_BUFIO I/O clock tree duty cycle distortion. All 0.14 0.14 0.14 ns TBUFIOSKEW I/O clock tree skew across one clock region. All 0.03 0.03 0.03 ns TDCD_BUFR Regional clock tree duty cycle distortion. All 0.18 0.18 0.18 ns Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. The T CKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx timing analysis tools to evaluate clock skew specific to your application. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 40 MMCM Switching Characteristics Table 37: MMCM Specification Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L MMCM_FINMAX Maximum input clock frequency. 800.00 800.00 800.00 MHz MMCM_FINMIN Minimum input clock frequency. 10.00 10.00 10.00 MHz MMCM_FINJITTER Maximum input clock period jitter. < 20% of clock input period or 1 ns Max MMCM_FINDUTY Allowable input duty cycle: 10—49 MHz. 25 25 25 % Allowable input duty cycle: 50—199 MHz. 30 30 30 % Allowable input duty cycle: 200—399 MHz. 35 35 35 % Allowable input duty cycle: 400—499 MHz. 40 40 40 % Allowable input duty cycle: > 500 MHz. 45 45 45 % MMCM_FMIN_PSCLK Minimum dynamic phase-shift clock frequency. 0.01 0.01 0.01 MHz MMCM_FMAX_PSCLK Maximum dynamic phase-shift clock frequency. 500.00 450.00 450.00 MHz MMCM_FVCOMIN Minimum MMCM VCO frequency. 600.00 600.00 600.00 MHz MMCM_FVCOMAX Maximum MMCM VCO frequency. 1440.00 1200.00 1200.00 MHz MMCM_FBANDWIDTH Low MMCM bandwidth at typical.(1) 1.00 1.00 1.00 MHz High MMCM bandwidth at typical.(1) 4.00 4.00 4.00 MHz MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs.(2) 0.12 0.12 0.12 ns MMCM_TOUTJITTER MMCM output jitter. Note 3 MMCM_TOUTDUTY MMCM output clock duty-cycle precision.(4) 0.20 0.20 0.20 ns MMCM_TLOCKMAX MMCM maximum lock time. 100.00 100.00 100.00 µs MMCM_FOUTMAX MMCM maximum output frequency. 800.00 800.00 800.00 MHz MMCM_FOUTMIN MMCM minimum output frequency.(5)(6) 4.69 4.69 4.69 MHz MMCM_TEXTFDVAR External clock feedback variation. < 20% of clock in put period or 1 ns Max MMCM_RSTMINPULSE Minimum reset pulse width. 5.00 5.00 5.00 ns MMCM_FPFDMAX Maximum frequency at the phase frequency detector. 500.00 450.00 450.00 MHz MMCM_FPFDMIN Minimum frequency at the phase frequency detector. 10.00 10.00 10.00 MHz MMCM_TFBDELAY Maximum delay in the feedback path. 3 ns Max or one CLKIN cycle MMCM Switching Characteristics Setup and Hold TMMCMDCK_PSEN/ TMMCMCKD_PSEN Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 41 PLL Switching Characteristics TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC Setup and hold of phase-shift T MMCMCKO_PSDONE Phase shift clock-to-out o f P S D O N E . 0 . 6 80 . 8 10 . 8 1 n s Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK TMMCMDCK_DADDR/ TMMCMCKD_DADDR TMMCMDCK_DI/ TMMCMCKD_DI TMMCMDCK_DEN/ TMMCMCKD_DEN TMMCMDCK_DWE/ TMMCMCKD_DWE TMMCMCKO_DRDY CLK to out of DRDY. 0.72 0.99 0.99 ns, Max FDCK DCLK frequency. 200.00 200.00 200.00 MHz, Max Notes: 1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any MMCM outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard [Ref 8]. 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. 6. When CLKOUT4_CAS CADE = TRUE, MMCM_FOUTMIN is 0.036 MHz. Table 38: PLL Specification Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L PLL_FINMAX Maximum input clock frequency. 800.00 800.00 800.00 MHz PLL_FINMIN Minimum input clock frequency. 19.00 19.00 19.00 MHz PLL_FINJITTER Maximum input clock period jitter. < 20 % of clock input period or 1 ns Max PLL_FINDUTY Allowable input duty cycle: 19—49 MHz. 25 25 25 % Allowable input duty cycle: 50—199 MHz. 30 30 30 % Allowable input duty cycle: 200—399 MHz. 35 35 35 % Allowable input duty cycle: 400—499 MHz. 40 40 40 % Allowable input duty cycle: >500 MHz. 45 45 45 % PLL_F VCOMIN Minimum PLL VCO frequency. 800.00 800.00 800.00 MHz PLL_FVCOMAX Maximum PLL VCO frequency. 1866.00 1600.00 1600.00 MHz Table 37: MMCM Specification (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 42 PLL_FBANDWIDTH Low PLL bandwidth at typical. 1.00 1.00 1.00 MHz High PLL bandwidth at typical.(1) 4.00 4.00 4.00 MHz PLL_TSTATPHAOFFSET Static phase offset of the PLL outputs.(2) 0.12 0.12 0.12 ns PLL_TOUTJITTER PLL output jitter. Note 3 PLL_TOUTDUTY PLL output clock duty-cycle precision.(4) 0.20 0.20 0.20 ns PLL_TLOCKMAX PLL maximum lock time. 100.00 100.00 100.00 µs PLL_FOUTMAX PLL maximum output frequency. 800.00 800.00 800.00 MHz PLL_FOUTMIN PLL minimum output frequency.(5) 6.25 6.25 6.25 MHz PLL_TEXTFDVAR External clock feedback variation. < 20% of clock input period or 1 ns Max PLL_RSTMINPULSE Minimum reset pulse width. 5.00 5.00 5.00 ns PLL_FPFDMAX Maximum frequency at the phase frequency detector. 500.00 450.00 450.00 MHz PLL_FPFDMIN Minimum frequency at the phase frequency detector. 19.00 19.00 19.00 MHz PLL_TFBDELAY Maximum delay in the feedback path. 3 ns Max or one CLKIN cycle Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK TPLLDCK_DADDR/ TPLLCKD_DADDR TPLLDCK_DI/ TPLLCKD_DI TPLLDCK_DEN/ TPLLCKD_DEN TPLLDCK_DWE/ TPLLCKD_DWE TPLLCKO_DRDY CLK to out of DRDY. 0.72 0.99 0.99 ns, Max FDCK DCLK frequency. 200.00 200.00 200.00 MHz, Max Notes: 1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any PLL outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard [Ref 8]. 4. Includes global clock buffer. 5. Calculated as FVCO/128 assumi ng output duty cycle is 50%. Table 38: PLL Specification Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 43 Device Pin-to-Pin Output Parameter Guidelines Table 39: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1) Symbol Description Device VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOF Clock-capable clock input and OUTFF at pins/banks closest to the BUFGs without MMCM/PLL (near clock region).(2) X C 7 S 6 5 . 5 56 . 5 06 . 5 0 n s XC7S15 5.55 6.50 6.50 ns XC7S25 5.55 6.44 6.44 ns XC7S50 5.71 6.62 6.62 ns XC7S75 5.73 6.71 6.71 ns X C 7 S 1 0 0 5 . 7 36 . 7 16 . 7 1 n s XA7S6 5.55 6.50 N/A ns XA7S15 5.55 6.50 N/A ns XA7S25 5.55 6.44 N/A ns XA7S50 5.71 6.62 N/A ns XA7S75 5.73 6.71 N/A ns XA7S100 5.73 6.71 N/A ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4]. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 44 Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1) Symbol Description Device VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOFFAR Clock-capable clock input and OUTFF at pins/banks farthest from the BUFGs without MMCM/PLL (far clock region).(2) XC7S6 5.55 6.50 6.50 ns XC7S15 5.55 6.50 6.50 ns XC7S25 5.55 6.44 6.44 ns XC7S50 5.71 6.62 6.62 ns XC7S75 6.01 7.02 7.02 ns XC7S100 6.01 7.02 7.02 ns XA7S6 5.55 6.50 N/A ns XA7S15 5.55 6.50 N/A ns XA7S25 5.55 6.44 N/A ns XA7S50 5.71 6.62 N/A ns XA7S75 6.01 7.02 N/A ns XA7S100 6.01 7.02 N/A ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475) [Ref 4]. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 45 Table 41: Clock-Capable Clock Input to Output Delay With MMCM(1) Symbol Description Device VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM.(2) XC7S6 1.03 1.03 1.03 ns XC7S15 1.03 1.03 1.03 ns XC7S25 1.00 1.00 1.00 ns XC7S50 1.00 1.00 1.00 ns XC7S75 1.00 1.00 1.00 ns XC7S100 1.00 1.00 1.00 ns XA7S6 1.03 1.03 N/A ns XA7S15 1.03 1.03 N/A ns XA7S25 1.00 1.00 N/A ns XA7S50 1.00 1.00 N/A ns XA7S75 1.00 1.00 N/A ns XA7S100 1.00 1.00 N/A ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. MMCM output jitter is already included in the timing calculation. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 46 Table 42: Clock-Capable Clock Input to Output Delay With PLL(1) Symbol Description Device VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. TICKOFPLLCC Clock-capable clock input and OUTFF with PLL.(2) XC7S6 0.85 0.85 0.85 ns XC7S15 0.85 0.85 0.85 ns XC7S25 0.83 0.83 0.83 ns XC7S50 0.83 0.83 0.83 ns XC7S75 0.83 0.83 0.83 ns XC7S100 0.83 0.83 0.83 ns XA7S6 0.85 0.85 N/A ns XA7S15 0.85 0.85 N/A ns XA7S25 0.83 0.83 N/A ns XA7S50 0.83 0.83 N/A ns XA7S75 0.83 0.83 N/A ns XA7S100 0.83 0.83 N/A ns Notes: 1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is already included in the timing calculation. Table 43: Pin-to-Pin, Clock-to-Out using BUFIO Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO. TICKOFCS Clock to out of I/O clock. 5.61 6.64 6.64 ns Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 47 Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Values are expressed in nanoseco nds unless otherwise noted. Table 44: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks Symbol Description Device VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) TPSFD/ TPHFD Full delay (legacy delay or default delay) global clock input and IFF (2) without MMCM/PLL with ZHOLD_DELAY on HR I/O banks. XA7S100 2.91/–0.33 3.36/–0.33 N/A ns Notes: 1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input flip-flop or latch. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 48 Table 45: Clock-Capable Clock Input Setup and Hold With MMCM Symbol Description Device VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)(2) TPSMMCMCC/ TPHMMCMCC No delay clock-capable clock input and IFF (3) with MMCM. XA7S100 2.81/–0.62 3.36/–0.62 N/A ns Notes: 1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. Use IBIS to determine any duty-cycle distortion incurred using various standards. 3. IFF = Input flip-flop or latch. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 49 Table 46: Clock-Capable Clock Input Setup and Hold With PLL Symbol Description Device VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)(2) TPSPLLCC/ TPHPLLCC No delay clock-capable clock input and IFF (3) with PLL. XA7S100 3.15/–0.19 3.78/–0.19 N/A ns Notes: 1. Setup and hold times are measured over wo rst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. Use IBIS to determine any duty-cycle distortion incurred using various standards. 3. IFF = Input flip-flop or latch. Table 47: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 50 Table 48: Sample Window Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L TSAMP Sampling error at receiver pins.(1) 0.64 0.70 0.70 ns TSAMP_BUFIO Sampling error at receiver pins using BUFIO.(2) 0.40 0.46 0.46 ns Notes: 1. This parameter indicates the total sampling error of the Sparta n-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to captur e the DDR input registers’ edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. 2. This parameter indicates the total sampling error of the Sparta n-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 51 Additional Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timi ng budgets for Spartan-7 FPGA clock transmitter and re ceiver data-valid windows. Table 49: Package Skew(1) Symbol Description Device Package Value Units XC7S6 CPGA196 44 ps CSGA225 83 ps FTGB196 65 ps XC7S15 CPGA196 44 ps CSGA225 83 ps FTGB196 65 ps XC7S25 CSGA225 93 ps CSGA324 62 ps FTGB196 83 ps XC7S50 CSGA324 80 ps FGGA484 110 ps FTGB196 103 ps XC7S75 FGGA484 117 ps FGGA676 110 ps XC7S100 FGGA484 117 ps FGGA676 110 ps XA7S6 CPGA196 44 ps CSGA225 83 ps FTGB196 65 ps XA7S15 CPGA196 44 ps CSGA225 83 ps FTGB196 65 ps XA7S25 CSGA225 93 ps CSGA324 62 ps FTGB196 83 ps XA7S50 CSGA324 80 ps FGGA484 110 ps FTGB196 103 ps XA7S75 FGGA484 117 ps FGGA676 110 ps XC7S100 FGGA484 117 ps FGGA676 110 ps Notes: 1. Package delay information is available for these device/package combinations. This information can be used to deskew the package. 2. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 52 XADC Specifications The 7 Series FPGAs Overview (DS180) [Ref 1] and XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2] list the devices that contain a 7 series XADC dual 12-Bit 1 MSPS analog-to-digital converter. Table 50: XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units VCCADC = 1.8V ± 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, –55°C ≤ Tj ≤ 125°C. Typical values at Tj = +40°C. ADC Accuracy(1) Resolution 12 – – Bits Integral nonlinearity(2) INL –40°C ≤ Tj ≤ 100°C – – ±2 LSBs Differential nonlinearity DNL No missing codes, guaranteed monotonic. – – ±1 LSBs Offset error Unipolar –40°C ≤ Tj ≤ 100°C – – ±8 LSBs Bipolar –55°C ≤ Tj ≤ 125°C – – ±4 LSBs Gain error –– ± 0 . 5 % Offset matching ––4 L S B s Gain matching –– 0 . 3 % Sample rate ––1 M S / s Signal to noise ratio(2) SNR F SAMPLE = 500 KS/s, FIN = 20 kHz 60 – – dB RMS code noise External 1.25V reference. – – 2 LSBs On-chip reference. – 3 – LSBs Total harmonic distortion(2) THD F SAMPLE = 500 KS/s, FIN = 20 kHz 70 – – dB Analog Inputs(3) ADC input ranges Unipolar operation. 0 – 1 V Bipolar operation. –0.5 – +0.5 V Unipolar common mode range (FS input). 0 – +0.5 V Bipolar common mode range (FS input). +0.5 – +0.6 V Maximum external channel input ranges Adjacent analog channels set within these ranges should not corrupt measurements on adjacent channels. –0.1 – V CCADC V Full-resolution bandwidth FRBW Auxiliary channel full resolution bandwidth. 250 – – kHz On-chip Sensors Temperature sensor error Supply sensor error Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 53 Conversion Rate(4) Conversion time: continuous tCONV Number of ADCCLK cycles. 26 – 32 Cycles Conversion time: event t CONV Number of CLK cycles. – – 21 Cycles DRP clock frequency DCLK DRP clock frequency. 8 – 250 MHz ADC clock frequency ADCCLK Derived from DCLK. 1 – 26 MHz DCLK duty cycle 40 – 60 % XADC Reference(5) External reference V REFP Externally supplied reference voltage. 1.20 1.25 1.30 V On-chip reference Ground VREFP pin to AGND, –40°C ≤ Tj ≤ 100°C 1.2375 1.25 1.2625 V Ground VREFP pin to AGND, –55°C ≤ Tj < –40°C; 100°C < Tj ≤ 125°C 1 . 2 2 51 . 2 51 . 2 7 5 V Notes: 1. Offset and gain errors are removed by enabling the XADC automa tic gain calibration feature. The values are specified for when this feature is enabled. 2. Only specified for bitstream op tion XADCEnhancedLinearity = ON. 3. For a detailed description, see the ADC chapter in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 9]. 4. For a detailed description, see the Timing chapter in the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 9]. 5. Any variation in the reference voltage from the nominal V REFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. Table 50: XADC Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 54 Configuration Switching Characteristics Table 51: Configuration Switching Characteristics Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Power-up Timing Characteristics TPL(1) Program latency. 5.00 5.00 5.00 ms, Max TPOR(2) Power-on reset (50 ms ramp rate time). 10/50 10/50 10/50 ms, Min/Max Power-on reset (1 ms ramp rate time). 10/35 10/35 10/35 ms, Min/Max TPROGRAM Program pulse width. 250.00 250.00 250.00 ns, Min CCLK Output (Master Mode) TICCK Master CCLK output delay. 150.00 150.00 150.00 ns, Min TMCCKL Master CCLK clock Low time duty cycle. 40/60 40/60 40/60 %, Min/Max TMCCKH Master CCLK clock High time duty cycle. 40/60 40/60 40/60 %, Min/Max FMCCK Master CCLK frequency. 100.00 100.00 100.00 MHz, Max Master CCLK frequency for AES encrypted x16.(2) 50.00 50.00 50.00 MHz, Max FMCCK_START Master CCLK frequency at start of configuration. 3.00 3.00 3.00 MHz, Typ FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK. ±50 ±50 ±50 %, Max CCLK Input (Slave Modes) TSCCKL Slave CCLK clock minimum Low time. 2.50 2.50 2.50 ns, Min TSCCKH Slave CCLK clock minimum High time. 2.50 2.50 2.50 ns, Min FSCCK Slave CCLK frequency. 100.00 100.00 100.00 MHz, Max EMCCLK Input (Master Mode) TEMCCKL External master CCLK Low time. 2.50 2.50 2.50 ns, Min TEMCCKH External master CCLK High time. 2.50 2.50 2.50 ns, Min FEMCCK External master CCLK frequency. 100.00 100.00 100.00 MHz, Max Internal Configuration Access Port FICAPCK Internal configuration access port (ICAPE2) clock frequency. 100.00 100.00 100.00 MHz, Max Master/Slave Serial Mode Programming Switching TDCCK/ TCCKD TCCO DOUT clock to out. 8.00 8.00 8.00 ns, Max SelectMAP Mode Programming Switching TSMDCCK/ TSMCCKD Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 55 TSMCSCCK/ TSMCCKCS TSMWCCK/ TSMCCKW TSMCKCSO CSO_B clock to out (330 Ω pull-up resistor required). 7.00 7.00 7.00 ns, Max TSMCO D[31:00] clock to out in readback. 8.00 8.00 8.00 ns, Max FRBCCK Readback frequency. 100.00 100.00 100.00 MHz, Max Boundary-Scan Port Timing Specifications TTAPTCK/ TTCKTAP TTCKTDO TCK falling edge to TDO output. 7.00 7.00 7.00 ns, Max FTCK TCK frequency. 66.00 66.00 66.00 MHz, Max SPI Flash Master Mode Programming Switching TSPIDCC/ TSPICCD TSPICCM MOSI clock to out. 8.00 8.00 8.00 ns, Max TSPICCFC FCS_B clock to out. 8.00 8.00 8.00 ns, Max STARTUPE2 Ports FCFGMCLK STARTUPE2 CFGMCLK output frequency. 65.00 65.00 65.00 MHz, Typ FCFGMCLKTOL STARTUPE2 CFGMCLK output frequency tolerance. ±50 ±50 ±50 %, Max Device DNA Access Port FDNACK DNA access port (DNA_PORT). 100.00 100.00 100.00 MHz, Max Notes: 1. To support longer delays in configuration, use the design solutions described in the 7 Series FPGA Configuration User Guide (UG470) [Ref 10]. 2. See the 7 Series FPGAs Overview (DS180) [Ref 1] and XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) [Ref 2] for a list of devices that support bitstream encryption. Table 51: Configuration Switching Characteristics (Cont’d) Symbol Description VCCINT Operating Voltage and Speed Grade Units1.0V 0.95V -2 -1 -1L Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 56 eFUSE Programming Conditions Table 52 lists the programming conditio ns specifically for eFUSE. For more information, see the 7S e r i e s FPGA Configuration User Guide (UG470) [Ref 10] . References 1. 7 Series FPGAs Overview (DS180 ) 2. XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171 ) 3. 7 Series FPGAs SelectIO Resources User Guide (UG471 ) 4. 7 Series FPGA Packaging and Pinout Specification (UG475 ) 5. 7 Series FPGAs PCB Design Guide (UG483 ) 6. Xilinx Power Estimator spreadsheet tool ( XPE) 7. Zynq-7000 SoC and 7 Series Devices Memo ry Interface Solutions User Guide (UG586 ) 8. See the Clocking Wizard in Vivado software. 9. 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digita l Converter User Guide (UG480 ) 10. 7 Series FPGA Configuration User Guide (UG470 ) Table 52: eFUSE Programming Conditions(1) Symbol Description Min Typ Max Units IFS VCCAUX supply current – – 115 mA Tj Temperature range 15 – 125 °C Notes: 1. The FPGA must not be configured during eFUSE programming. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 57

Revision History

The following table shows the revision history for this document: Date Version Description of Revisions 09/28/2018 1.8 Removed description of -1Q speed gr ade only being available in XA Spartan-7 FPGAs from second paragraph of Introduction. 07/31/2018 1.7 In Table 12, updated Vivado tools version to 2018.2.1. In Table 13, moved all speed grades for all devices to Production. In Table 14, added Vivado tools version for XC7S6, XC7S15, XC7S75, XC7S100, XA7S6, XA7S15, XA7S75, and XA7S100. 06/18/2018 1.6 In Table 12, updated Vivado tools version to 2018.2. In Table 13, moved all speed grades except -1Q (1.0V) for XC7S6 and XC7S15 to Production. In Table 14, added Vivado tools version for XC7S6 and XC7S15. 04/04/2018 1.5 Added XA7S6, XA7S15, XA7S25, XA7S75, and XA7S100 devices throughout. In Table 5, updated typical quiescent supply current values for XC7S25 and XC7S50 devices, and added values for XC7S6, XC7S15, XC7S75, and XC7S100 devices. In Table 6, updated table title and ICCINTMIN and ICCAUXMIN for XC7S75 and XC7S100 devices. In Table 13, moved all speed grades for XC7S6 and XC7S15 to Preliminary, moved -1LI (0.95V) speed grade for XC7S25 to Production, and moved all speed grades except -1Q (1.0V) for XC7S75 and XC7S100 from Preliminary to Production. In Table 14, added Vivado tools version for XC7S25, XC7S75, and XC7S100. In Table 36, Table 39, Table 40, Table 41, Table 42, Table 44, Table 45, and Table 46, changed parameter value for XA7S50 to N/A. In Table 49, added package skew values for XC7S6 and XC7S15 devices. 12/22/2017 1.4 In Table 12, updated Vivado tools version to 2017.4. In Table 13, moved all speed grades for XC7S75 and XC7S100 from Advance to Preliminary and all speed grades except -1LI (0.95V) for XC7S25 from Advance to Production. In Table 14, added Vivado tools version for XC7S25. Added Note 2 to Table 16. In Table 49, added package skew values for XC7S25 device in CSGA324 package and XC7S75 and XC7S100 devices in FGGA676 package. 11/20/2017 1.3 Added XA7S50 device throughout . Updated description of offered temperature ranges in second paragraph of Introduction. Added row for junction temperature (Tj) at expanded (Q) temperature to Table 2. Added -1Q (1.0V) speed grade to Table 5, and Table 13 to Table 16. In Table 12, updated Vivado tools version to 2017.3. In Table 49, added package skew values for XC7S25, XC7S50, XC7S75, and XC7S100 devices in CSGA225, FTGB196, and FGGA484 packages. Added XA Spartan-7 Automotive FPGA Data Sheet: Overview (DS171) to References. 06/20/2017 1.2 Updated paragraph before Table 6. In Table 12, updated Vivado tools version to 2017.2. In Table 13, moved all speed grades for XC7S50 from Preliminary to Production and updated Note 1. In Table 14, added Vivado tools version for XC7S50. In Table 49, added package skew value for XC7S50 device in FGGA484 package. Send Feedback

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS189 (v1.8) September 28, 2018 www.xilinx.com Product Specification 58 Please Read: Important Legal Notices The information disclosed to you hereunder (the “Materials”) is provided solely for the selectio n and use of Xilinx products. T o the maximum extent permitted by applicable law: (1) Materials are ma de available “AS IS” and with all faults, Xilinx hereby DISCLAI MS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NO T LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PART ICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) fo r any loss or damage of any kind or nature related to, arising under, or in connection with, th e Materials (including your use of the Ma terials), including for any direct, indire ct, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx h ad been advised of the possibility of the same . Xilinx assumes no obligation to correct an y errors contained in the Materials or t o notify you of updates to the Mate rials or to product specifications. You may not reproduce, modify, distribute, or publicly dis play the Materials without prior written consent. Certain products are subject to the terms and conditio ns of Xilinx’s limited warra nty, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos ; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-saf e performance; you assume sole risk and lia bility for use of Xilinx products in su ch critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos . Automotive Applications Disclaimer AUTOMOTIVE PRODUCTS (IDENTIF IED AS "XA" IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS TH AT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WI TH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBU TING ANY SYSTEMS THAT INCO RPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. © Copyright 2016–2018 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex , Vivado, Zynq, and other design ated brands included herein are trademarks of Xilinx in the United States and other countr ies. All other trademarks are the property of their respective owners. 04/07/2017 1.1 Added 1.35V to Note 5 in Table 2. In Table 12, updated Vivado tools version to 2016.4. In Table 13, moved all speed grades for XC7S50 from Advance to Preliminary. Removed SFI-4.1 and SPI-4.2 from descriptions of SDR LVDS receiver and DDR LVDS receiver, respectively, in Table 15. In Table 25, changed TIDELAYRESOLUTION units from ps to µs. Removed BUFMR from Note 1 in Table 34. In Table 49, replaced TQGA144 with FTGB196 for XC7S6, XC7S15, and XC7S25 devices, added FTGB196 package for XC7S50 device, and added package skew value for XC7S50 device in CSGA324 package. 09/27/2016 1.0 Initial Xilinx release. Date Version Description of Revisions Send Feedback