XC7K160T

XC7K160T-1FB676I AMD | Alldatasheet

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DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 1 © 2011–2017 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Introduction Kintex®-7 FPGAs are available in -3, -2, -1, -1L, and -2L speed grades, with -3 having the highest performance. The -2L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -2 devices. The -2L industrial (I) temperature devices operate only at V CCINT = 0.95V. The -2L extended (E) temperature devices can operate at either VCCINT =0 . 9 V o r 1.0V. The -2LE devices when operated at VCCINT =1 . 0 V , a n d the -2LI devices when operated at VCCINT = 0.95V, have the same speed specifications as the -2 speed grade, except where noted. When the -2LE devices are operated at V CCINT = 0.9V, the speed specifications, static power, and dynamic power are reduced. The -1L military (M) temperature devices have the same speed specifications as the -1 military temperature devices and are screened for lower maximum static power. Kintex-7 FPGA DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Except for the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade military temperature device are the same as for a -1 speed grade commercial temperature device). However, only selected speed grades and/or devices are available in each temperature range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Available device and package combinations can be found in:

• 7 Series FPGAs Overview (DS180)
• Defense-Grade 7 Series FPGAs Overview (DS185) This Kintex-7 FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/documentation DC Characteristics Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 Product Specification Table 1: Absolute Maximum Ratings (1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage –0.5 1.1 V VCCAUX Auxiliary supply voltage –0.5 2.0 V VCCBRAM Supply voltage for the block RAM memories –0.5 1.1 V VCCO Output drivers supply voltage for HR I/O banks –0.5 3.6 V Output drivers supply voltage for HP I/O banks –0.5 2.0 V VCCAUX_IO Auxiliary supply voltage –0.5 2.06 V VREF Input reference voltage –0.5 2.0 V VIN(2)(3)(4) I/O input voltage for HR I/O banks –0.40 V CCO +0 . 5 5 V I/O input voltage for HP I/O banks –0.55 V CCO +0 . 5 5 V I/O input voltage (when VCCO =3 . 3 V ) f o r VREF and differential I/O standards except TMDS_33(5) –0.40 2.625 V VCCBATT Key memory battery backup supply –0.5 2.0 V Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 2 GTX Transceiver VMGTAVCC Analog supply voltage for the GTX transmitter and receiver circuits –0.5 1.1 V VMGTAVTT Analog supply voltage for the GTX transmitter and receiver termination circuits –0.5 1.32 V VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX transceivers –0.5 1.935 V VMGTREFCLK GTX transceiver reference clock absolute input voltage –0.5 1.32 V VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTX transceiver column –0.5 1.32 V VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating – 14 mA IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT – 12 mA IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND – 6.5 mA IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating – 14 mA IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT – 12 mA XADC VCCADC XADC supply relative to GNDADC –0.5 2.0 V VREFP XADC reference input relative to GNDADC –0.5 2.0 V Temperature TSTG Storage temperature (ambient) –65 150 °C TSOL Maximum soldering temperature for Pb/Sn component bodies (6) –+ 2 2 0 ° C Maximum soldering temperature for Pb-free component bodies (6) –+ 2 6 0 ° C Tj Maximum junction temperature(6) –+ 1 2 5 ° C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. The lower absolute voltage specification always applies. 3. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471 4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5. 5. See Table 10 for TMDS_33 specifications. 6. For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475). Table 2: Recommended Operating Conditions (1)(2) Symbol Description Min Typ Max Units FPGA Logic VCCINT(3) For -3, -2, -2LE (1.0V), -1, -1M, -1LM devices: internal supply voltage 0.97 1.00 1.03 V For -2LE (0.9V) devices: internal supply voltage 0.87 0.90 0.93 V For -2LI (0.95V) devices: internal supply voltage 0.93 0.95 0.97 V VCCBRAM(3) For -3, -2, -2LE (1.0V), -1, -1M, -1LM devices: block RAM supply voltage 0.97 1.00 1.03 V For -2LE (0.9V) devices: block RAM supply voltage 0.87 0.90 1.03 V For -2LI (0.95V) devices: block RAM supply voltage 0.93 0.95 0.97 V VCCAUX Auxiliary supply voltage 1.71 1.80 1.89 V VCCO(4)(5) Supply voltage for HR I/O banks 1.14 – 3.465 V Supply voltage for HP I/O banks 1.14 – 1.89 V Table 1: Absolute Maximum Ratings (1) (Cont’d) Symbol Description Min Max Units Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 3 VCCAUX_IO(6) Auxiliary supply voltage when set to 1.8V 1.71 1.80 1.89 V Auxiliary supply voltage when set to 2.0V 1.94 2.00 2.06 V VIN(7) I/O input voltage –0.20 – V CCO +0 . 2 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(8) –0.20 – 2.625 V IIN(9) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. –– 1 0 m A VCCBATT(10) Battery voltage 1.0 – 1.89 V GTX Transceiver VMGTAVCC(11) Analog supply voltage for the GTX transceiver QPLL frequency range ≤ 10.3125 GHz(12)(13) 0.97 1.0 1.08 V Analog supply voltage for the GTX transceiver QPLL frequency range > 10.3125 GHz 1.02 1.05 1.08 V VMGTAVTT(11) Analog supply voltage for the GTX transmitter and receiver termination circuits 1.17 1.2 1.23 V VMGTVCCAUX(11) Auxiliary analog QPLL voltage supply for the transceivers 1.75 1.80 1.85 V VMGTAVTTRCAL(11) Analog supply voltage for the resistor calibration circuit of the GTX transceiver column 1.17 1.2 1.23 V XADC VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V VREFP Externally supplied reference voltage 1.20 1.25 1.30 V Temperature Tj Junction temperature operating range for commercial (C) temperature devices 0– 8 5 ° C Junction temperature operating range for extended (E) temperature devices 0– 1 0 0 ° C Junction temperature operating range for industrial (I) temperature devices –40 – 100 °C Junction temperature operating range for military (M) temperature devices –55 – 125 °C Notes: 1. All voltages are relative to ground. 2. For the design of the power distribution system, consult the 7 Series FPGAs PCB Design and Pin Planning Guide (UG483). 3. V CCINT and VCCBRAM should be connected to the same supply. 4. Configuration data is retained even if V CCO drops to 0V. 6. For more informatio n, refer to the VCCAUX_IO section of 7 Series FPGAs SelectIO Resources User Guide (UG471). 7. The lower absolute voltage specification always applies. 8. See Table 10 for TMDS_33 specifications. 9. A total of 200 mA per bank should not be exceeded. 10. V CCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. 11. Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476). 12. For data rates ≤ 10.3125 Gb/s, VMGTAVCC should be 1.0V ±3% for lower power consumption. 13. For lower power consumption, V MGTAVCC should be 1.0V ±3% over the entire CPLL frequency range. Table 2: Recommended Operating Conditions (1)(2) (Cont’d) Symbol Description Min Typ Max Units Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 4 Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ (1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 – – V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 – – V IREF VREF leakage current per pin – – 15 µA IL Input or output leakage current per pin (sample-tested) – – 15 µA CIN(2) Die input capacitance at the pad – – 8 pF IRPU Pad pull-up (when selected) @ VIN =0 V , VCCO =3 . 3 V 9 0 – 3 3 0 µ A Pad pull-up (when selected) @ VIN =0 V , VCCO =2 . 5 V 6 8 – 2 5 0 µ A Pad pull-up (when selected) @ VIN =0 V , VCCO =1 . 8 V 3 4 – 2 2 0 µ A Pad pull-up (when selected) @ VIN =0 V , VCCO =1 . 5 V 2 3 – 1 5 0 µ A Pad pull-up (when selected) @ VIN =0 V , VCCO =1 . 2 V 1 2 – 1 2 0 µ A IRPD Pad pull-down (when selected) @ VIN =3 . 3 V 6 8 – 3 3 0 µ A Pad pull-down (when selected) @ VIN =1 . 8 V 4 5 – 1 8 0 µ A ICCADC Analog supply current, analog circuits in powered up state – – 25 mA IBATT(3) Battery supply current – – 150 nA RIN_TERM(4) Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40) 28 40 55 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50) 35 50 65 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60) 44 60 83 Ω n Temperature diode ideality factor – 1.010 – – r Temperature diode series resistance – 2 – Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. This measurement represents the die capacitance at the pad, not including the package. 3. Maximum value specified for worst case process at 25°C. 4. Termination resistance to a V CCO/2 level. Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) AC Voltage Overshoot % of UI at –55°C to 125° C AC Voltage Undershoot % of UI at –55°C to 125°C VCCO + 0.55 100 –0.40 100 –0.45 61.7 –0.50 25.8 –0.55 11.0 VCCO + 0.60 46.6 –0.60 4.77 VCCO + 0.65 21.2 –0.65 2.10 VCCO + 0.70 9.75 –0.70 0.94 VCCO + 0.75 4.55 –0.75 0.43 VCCO + 0.80 2.15 –0.80 0.20 VCCO + 0.85 1.02 –0.85 0.09 VCCO + 0.90 0.49 –0.90 0.04 Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 5 VCCO + 0.95 0.24 –0.95 0.02 Notes: 1. A total of 200 mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above V CCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HP I/O Banks(1)(2) AC Voltage Overshoot % of UI at –55°C to 125° C AC Voltage Undershoot % of UI at –55°C to 125°C VCCO + 0.55 100 –0.55 100 VCCO + 0.85 4.51 –0.85 28.4 VCCO + 0.90 2.12 –0.90 12.7 VCCO + 0.95 1.01 –0.95 5.79 Notes: 1. A total of 200 mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above V CCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. 3. For UI lasting less than 20 µs. Table 6: Typical Quiescent Supply Current Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LM -1M -2LI -2LE ICCINTQ Quiescent VCCINT supply current XC7K70T 241 241 241 N/A N/A N/A 187 mA XC7K160T 474 474 474 N/A N/A 271 368 mA XC7K325T 810 810 810 N/A N/A 463 629 mA XC7K355T 993 993 993 N/A N/A 568 771 mA XC7K410T 1080 1080 1080 N/A N/A 618 838 mA XC7K420T 1313 1313 1313 N/A N/A 751 1019 mA XC7K480T 1313 1313 1313 N/A N/A 751 1019 mA XQ7K325T N/A 810 810 810 810 463 629 mA XQ7K410T N/A 1080 1080 N/A 1080 618 838 mA Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) (Cont’d) AC Voltage Overshoot % of UI at –55°C to 125° C AC Voltage Undershoot % of UI at –55°C to 125°C Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 6 ICCOQ Quiescent VCCO supply current XC7K70T 1 1 1 N/A N/A N/A 1 mA XC7K160T 1 1 1 N/A N/A 1 1 mA XC7K325T 1 1 1 N/A N/A 1 1 mA XC7K355T 1 1 1 N/A N/A 1 1 mA XC7K410T 1 1 1 N/A N/A 1 1 mA XC7K420T 1 1 1 N/A N/A 1 1 mA XC7K480T 1 1 1 N/A N/A 1 1 mA XQ7K325T N/A 1 1 1 1 1 1 mA XQ7K410T N/A 1 1 N/A 1 1 1 mA I CCAUXQ Quiescent VCCAUX supply current XC7K70T 21 21 21 N/A N/A N/A 21 mA XC7K160T 40 40 40 N/A N/A 36 40 mA XC7K325T 68 68 68 N/A N/A 61 68 mA XC7K355T 75 75 75 N/A N/A 67 75 mA XC7K410T 85 85 85 N/A N/A 76 85 mA XC7K420T 99 99 99 N/A N/A 89 99 mA XC7K480T 99 99 99 N/A N/A 89 99 mA XQ7K325T N/A 68 68 68 68 68 68 mA XQ7K410T N/A 85 85 N/A 85 85 85 mA I CCAUX_IOQ Quiescent VCCAUX_IO supply current XC7K70T N/A N/A N/A N/A N/A N/A N/A mA XC7K160T 2 2 2 N/A N/A 1 2 mA XC7K325T 2 2 2 N/A N/A 1 2 mA X C 7 K 3 5 5 T N / AN / AN / AN / AN / AN / AN / A m A XC7K410T 2 2 2 N/A N/A 1 2 mA X C 7 K 4 2 0 T N / AN / AN / AN / AN / AN / AN / A m A X C 7 K 4 8 0 T N / AN / AN / AN / AN / AN / AN / A m A XQ7K325T N/A 2 2 2 2 2 2 mA XQ7K410T N/A 2 2 N/A 2 2 2 mA Table 6: Typical Quiescent Supply Current (Cont’d) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LM -1M -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 7 Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously. For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:

• The voltage difference between V CCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.
• T h e T VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps. The recommended power-on sequence to achieve minimum current draw for the GTX transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power- up and power-down.
• W h e n V MGTAVTT is powered before VMGTAVCC and VMGTAVTT –V MGTAVCC > 150 mV and VMGTAVCC <0 . 7 V , t h e VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
• W h e n V MGTAVTT is powered before VCCINT and VMGTAVTT –V CCINT > 150 mV and VCCINT <0 . 7 V , t h e VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down. There is no recommended sequence for supplies not shown. Table 7 shows the minimum current, in addition to I CCQ, that are required by Kintex-7 devices for proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. ICCBRAMQ Quiescent VCCBRAM supply current XC7K70T 6 6 6 N/A N/A N/A 6 mA XC7K160T 14 14 14 N/A N/A 8 14 mA XC7K325T 19 19 19 N/A N/A 10 19 mA XC7K355T 31 31 31 N/A N/A 17 31 mA XC7K410T 34 34 34 N/A N/A 19 34 mA XC7K420T 41 41 41 N/A N/A 23 41 mA XC7K480T 41 41 41 N/A N/A 23 41 mA XQ7K325T N/A 19 19 19 19 19 19 mA XQ7K410T N/A 34 34 N/A 34 34 34 mA Notes: 1. Typical values are specified at nominal voltage, 85°C junction temperatures (T j) with single-ended SelectIO resources. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for conditions other than those specified. Table 6: Typical Quiescent Supply Current (Cont’d) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LM -1M -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 8 Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate current drain on these supplies. DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 7: Power-On Current for Kintex-7 Devices Device I CCINTMIN ICCAUXMIN ICCOMIN ICCAUX_IOMIN ICCBRAMMIN Units XC7K70T I CCINTQ + 450 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +4 0 m A XC7K160T I CCINTQ + 550 I CCAUXQ +5 0 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +4 0 m A XC7K325T I CCINTQ + 600 I CCAUXQ +8 0 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +4 0 m A XC7K355T I CCINTQ + 1450 I CCAUXQ +1 0 9 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +8 1 m A XC7K410T I CCINTQ + 1500 I CCAUXQ +1 2 5 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +9 0 m A XC7K420T I CCINTQ + 2200 I CCAUXQ +1 8 0 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +1 0 8 m A XC7K480T I CCINTQ + 2200 I CCAUXQ +1 8 0 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +1 0 8 m A XQ7K325T I CCINTQ + 600 I CCAUXQ +8 0 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +4 0 m A XQ7K410T I CCINTQ + 1500 I CCAUXQ +1 2 5 I CCOQ + 40 mA per bank I CCOAUXIOQ + 40 mA per bank I CCBRAMQ +9 0 m A Table 8: Power Supply Ramp Time Symbol Description Conditions Min Max Units TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms TVCCAUX_IO Ramp time from GND to 90% of VCCAUX_IO 0.2 50 ms TVCCBRAM Ramp time from GND to 90% of VCCBRAM 0.2 50 ms TVCCO2VCCAUX Allowed time per power cycle for VCCO – VCCAUX > 2.625V TJ = 125°C(1) –3 0 0 msTJ = 100°C(1) –5 0 0 TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms TMGTVCCAUX Ramp time from GND to 90% of VMGTVCCAUX 0.2 50 ms Notes: 1. Based on 240,000 power cycles with nominal V CCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V. Table 9: SelectIO DC Input and Output Levels (1)(2) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 9 LVCMOS12 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.400 V CCO –0 . 4 0 0 Note 3 Note 3 LVCMOS15, LVDCI_15 –0.300 35% V CCO 65% VCCO VCCO + 0.300 25% V CCO 75% VCCO Note 4 Note 4 LVCMOS18, LVDCI_18 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.450 V CCO –0 . 4 5 0 Note 5 Note 5 MOBILE_DDR –0.300 20% V CCO 80% VCCO VCCO + 0.300 10% V CCO 90% VCCO 0.1 –0.1 PCI33_3 –0.400 30% V CCO 50% VCCO VCCO + 0.500 10% V CCO 90% VCCO 1.5 –0.5 Notes: 1. Tested according to relevant specifications. 2. 3.3V and 2.5V standards are only supported in HR I/O banks. 3. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks. 4. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks. 5. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks. 6. Supported drive strengths of 4, 8, 12, or 16 mA 7. Supported drive strengths of 4, 8, 12, 16, or 24 mA 8. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide (UG471 Table 9: SelectIO DC Input and Output Levels (1)(2) (Cont’d) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 10 Table 10: Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) VID(2) VOCM(3) VOD(4) V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage (Q – Q). 3. V OCM is the output common mode voltage. 4. V OD is the output differential voltage (Q – Q). 5. V OD for BLVDS will vary significantly depending on topology and loading. 6. LVDS_25 is specified in Table 12. 7. LVDS is specified in Table 13. Table 11: Complementary Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH V, Min V, Typ V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage (Q – Q). 3. V OL is the single-ended low-output voltage. 4. V OH is the single-ended high-output voltage. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 11 LVDS DC Specifications (LVDS_25) The LVDS_25 standard is available in the HR I/O banks. See the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more information. LVDS DC Specifications (LVDS) The LVDS standard is available in the HP I/O banks. See the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more information. Table 12: LVDS_25 DC Specifications Symbol DC Parameter Conditions Min Typ Max Units VCCO Supply Voltage 2.375 2.500 2.625 V VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals – – 1.675 V VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.700 – – V VODIFF Differential Output Voltage: (Q – Q), Q = High (Q –Q ) , Q=H i g h RT = 100 Ω across Q and Q signals 247 350 600 mV VOCM Output Common-Mode Voltage R T = 100 Ω across Q and Q signals 1.000 1.250 1.425 V VIDIFF Differential Input Voltage: (Q – Q), Q = High (Q –Q ) , Q=H i g h 100 350 600 mV VICM Input Common-Mode Voltage 0.300 1.200 1.500 V Notes: 1. Differential inputs for LVDS_25 can be placed in banks with V CCO levels that are different from the required level for outputs. Refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more information. Table 13: LVDS DC Specifications Symbol DC Parameter Conditions Min Typ Max Units VCCO Supply Voltage 1.710 1.800 1.890 V VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals – – 1.675 V VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.825 – – V VODIFF Differential Output Voltage: (Q – Q), Q = High (Q –Q ) , Q=H i g h RT = 100 Ω across Q and Q signals 247 350 600 mV VOCM Output Common-Mode Voltage R T = 100 Ω across Q and Q signals 1.000 1.250 1.425 V VIDIFF Differential Input Voltage: (Q – Q), Q = High (Q –Q ) , Q=H i g h Common-mode input voltage = 1.25V 100 350 600 mV VICM Input Common-Mode Voltage Differential input voltage = ±350 mV 0.300 1.200 1.425 V Notes: 1. Differential inputs for LVDS can be placed in banks with V CCO levels that are different from the required level for outputs. Refer to the 7S e r i e s FPGAs SelectIO Resources User Guide (UG471) for more information. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 12 AC Switching Characteristics All values represented in this data sheet are based on the speed specifications in the Vivado® Design Suite 2015.4 and ISE® software 14.7 as outlined in Table 14. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance Product Specification These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary Product Specification These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Product Specification These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to production before faster speed grades. Testing of AC Switching Characteristics Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Kintex-7 FPGAs. Table 14: Kintex-7 FPGA Speed Specification Version By Device Version In: Typical V CCINT Device ISE 14.7 Vivado 2015.4 ( Table 2) 1.10 1.12 1.0V XC7K70T (1), XC7K160T(1), XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T N/A 1.12 0.95V XC7K160T (1), XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T 1.09 1.09 0.9V XC7K70T, XC7K 160T, XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T 1.05 1.09 1.0V XQ7K325T, XQ7K410T 1.05 1.09 0.9V XQ7K325T, XQ7K410T Notes: 1. GTX data rates greater than 6.6 Gb/s in the FBG484 package in the -3 and -2 speed grades require Vivado Design Suite 2017.1 or later. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 13 Speed Grade Designations Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 15 correlates the current status of each Kintex-7 device on a per speed grade basis. Production Silicon and Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 16 lists the production released Kintex-7 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 15: Kintex-7 Device Speed Grade Designations Device Speed Grade Designations Advance Preliminary Production XC7K70T -3, -2, -2LE(1.0V), -1, and -2LE (0.9V) XC7K160T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K325T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K355T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K410T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K420T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XC7K480T -3, -2, -2LE(1.0V), -2LI (0.95V), -1, and -2LE (0.9V) XQ7K325T -2I, -2LE(1.0V), -1I, -2LE(0 .9V), -2LI (0.95V), -1LM, and -1M XQ7K410T -2I, -2LE(1.0V), -1I, -2LE (0.9V), -2LI (0.95V), and -1M Table 16: Kintex-7 Device Production Software and Speed Specification Release Device Speed Grade Designations 1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M -1LM -2LI -2LE XC7K70T Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06 N/A N/A N/A Vivado tools 2012.4 v1.07 or ISE tools 14.3 v1.06 XC7K160T Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06 N/A N/A Vivado tools 2014.4 v1 .12 Vivado tools 2012.4 v1.07 or ISE tools 14.3 v1.06 XC7K325T Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06 N/A N/A Vivado tools 2014.4 v1 .12 Vivado tools 2012.4 v1.07 or ISE tools 14.3 v1.06 XC7K355T Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06 N/A N/A Vivado tools 2014.4 v1 .12 Vivado tools 2012.4 v1.07 or ISE tools 14.3 v1.06 XC7K410T Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06 N/A N/A Vivado tools 2014.4 v1 .12 Vivado tools 2012.4 v1.07 or ISE tools 14.3 v1.06 XC7K420T Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06 N/A N/A Vivado tools 2014.4 v1 .12 Vivado tools 2012.4 v1.07 or ISE tools 14.3 v1.06 XC7K480T Vivado tools 2012.4 v1.08 or ISE tools 14.2 v1.06 N/A N/A Vivado tools 2014.4 v1 .12 Vivado tools 2012.4 v1.07 or ISE tools 14.3 v1.06 XQ7K325T N/A Vivado t ools 2013.1 v1.04 or ISE tools 14.5 v1.04 Vivado tools 2015.4 v1.09 Vivado tools 2015.4 v1.07 V ivado tools 2013.1 v1.04 or ISE tools 14.5 v1.04 XQ7K410T N/A Vivado t ools 2013.1 v1.04 or ISE tools 14.5 v1.04 N/A Vivado tools 2015.4 v1.0 7 Vivado tools 2013.1 v1.04 or ISE tools 14.5 v1.04 Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 14 Selecting the Correct Speed Grade and Voltage in the Vivado Tools It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting. To select the 1.0V speed specifications in the Vivado tools, select the Kintex-7 or Defense Grade Kintex-7Q sub-family, and then select the part name that is the device name followed by the package name followed by the speed grade. For example, select the xc7k325tffg900-3 part name for the XC7K325T device in the FFG900 package and -3 (1.0V) speed grade or select the xc7k325tffg900-2L part name for the XC7K325T device in the FFG900 package and -2LE (1.0V) speed grade. To select the -2LI (0.95V) speed specifications in the Vivado tools, select the Kintex-7 sub-family and then select the part name that is the device name followed by an i followed by the package name followed by the speed grade. For example, select the xc7k325tiffg900-2L part name for the XC7K325T device in the FFG900 package and -2LI (0.95V) speed grade. The -2LI (0.95V) speed specifications are not supported in the ISE tools. To select the -2LE (0.9V) speed specifications in the Vivado tools, select the Kintex-7 Low Voltage or Defense Grade Kintex-7Q Low Voltage sub-family, and then select the part name that is the device name followed by an l followed by the package name followed by the speed grade. For example, select the xc7k325tlffg900-2L part name for the XC7K325T device in the FFG900 package and -2LE (0.9V) speed grade. A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See Table 16 for the subset of 7 series FPGAs supported in the ISE tools. Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Kintex-7 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 12. In each table, the I/O bank type is either High Performance (HP) or High Range (HR). Table 18 and Table 19 provide the maximum data rates for applicable memory standards using the Kintex-7 FPGAs memory PHY. The final performance of the memory interface is determined through a complete design implemented in the Vivado or ISE Design Suite, following guidelines in the Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586), electrical analysis, and characterization of the system. Table 17: Networking Applications Interface Performances

Description

Units1.0V 0.95V 0.9V -3 -2/-2LE -1/-1M/-1LM -2LI -2LE SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) HR 710 710 625 710 625 Mb/s HP 710 710 625 710 625 Mb/s DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) HR 1250 1250 950 1250 950 Mb/s HP 1600 1400 1250 1400 1250 Mb/s SDR LVDS receiver (SFI-4.1)(1) HR 710 710 625 710 625 Mb/s HP 710 710 625 710 625 Mb/s DDR LVDS receiver (SPI-4.2)(1) HR 1250 1250 950 1250 950 Mb/s HP 1600 1400 1250 1400 1250 Mb/s Notes: 1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 15 Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface Generator (FF and RF Packages)(1)(2) Memory Standard I/O Bank Type VCCAUX_IO Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE 4:1 Memory Controllers DDR3 HP 2.0V 1866 (3) 1866(3) 1600 1066 1600 1333 Mb/s HP 1.8V 1600 1333 1066 800 1333 1066 Mb/s HR N/A 1066 1066 800 800 1066 800 Mb/s DDR3L HP 2.0V 1600 1600 1333 1066 1600 1066 Mb/s HP 1.8V 1333 1066 800 800 1066 800 Mb/s HR N/A 800 800 667 N/A 800 667 Mb/s DDR2 HP 2.0V 800 800 800 667 800 800 Mb/s HP 1.8V 800 800 800 667 800 800 Mb/s HR N/A 800 800 800 533 800 800 Mb/s RLDRAM III HP 2.0V 800 667 667 550 667 533 MHz HP 1.8V 550 500 450 400 500 450 MHz HR N/A N/A 2:1 Memory Controllers DDR3 HP 2.0V 1066 1066 800 667 1066 800 Mb/s HP 1.8V 1066 1066 800 667 1066 800 Mb/s HR N/A 1066 1066 800 667 1066 800 Mb/s DDR3L HP 2.0V 1066 1066 800 667 1066 800 Mb/s HP 1.8V 1066 1066 800 667 1066 800 Mb/s HR N/A 800 800 667 N/A 800 667 Mb/s DDR2 HP 2.0V 800 800 800 667 800 800 Mb/sHP 1.8V 667 HR N/A 533 QDR II+(4) HP 2.0V 550 500 450 300 500 450 MHz HP 1.8V HR N/A 500 450 400 300 450 400 MHz RLDRAM II HP 2.0V 533 500 450 400 500 450 MHzHP 1.8V HR N/A LPDDR2 HP 2.0V 667 667 667 533 667 667 Mb/s HP 1.8V 667 667 667 533 667 667 Mb/s HR N/A 667 667 667 533 667 667 Mb/s Notes: 1. V REF tracking is required. For more information, see the Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586). 2. When using the internal V REF, the maximum data rate is 800 Mb/s (400 MHz). 3. For designs using 1866 Mb/s components, contact Xilinx Technical Support. 4. The maximum QDRII+ performance specifications are for burst-l ength 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations are limited to 333 MHz for all speed grades and I/O bank types. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 16 Table 19: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface Generator (FB Packages)(1)(2) Memory Standard I/O Bank Type VCCAUX_IO(3) Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE 4:1 Memory Controllers DDR3 HP N/A 1333 1066 800 800 1066 800 Mb/s HR N/A 1066 800 800 800 800 800 Mb/s DDR3L HP N/A 1066 800 667 667 800 667 Mb/s HR N/A 800 800 667 N/A 800 667 Mb/s DDR2 HP N/A 800 800 800 667 800 800 Mb/s HR N/A 800 667 667 533 667 667 Mb/s RLDRAM III HP N/A 550 500 450 350 500 450 MHz HR N/A N/A 2:1 Memory Controllers DDR3 HP N/A 1066 1066 800 667 1066 800 Mb/s HR N/A 1066 800 800 667 800 800 Mb/s DDR3L HP N/A 1066 800 667 667 800 667 Mb/s HR N/A 800 800 667 N/A 800 667 Mb/s DDR2 HP N/A 800 800 800 667 800 800 Mb/s HR N/A 800 667 667 533 667 667 Mb/s QDR II+(4) HP N/A 550 500 450 300 500 450 MHz HR N/A 450 400 350 300 400 350 MHz RLDRAM II HP N/A 533 500 450 400 500 450 MHz HR N/A LPDDR2 HP N/A 667 667 667 400 667 667 Mb/s HR N/A 667 667 533 400 667 533 Mb/s Notes: 1. V REF tracking is required. For more information, see the Zynq-7000 AP SoC and 7 Series Devices Memory Interface Solutions User Guide (UG586). 2. When using the internal V REF, the maximum data rate is 800 Mb/s (400 MHz). 3. FB packages do not have separate V CCAUX_IO supply pins to adjust the pre-driver voltage of the HP I/O banks. 4. The maximum QDRII+ performance specifications are for burst-l ength 4 (BL = 4) implementations. Burst length 2 (BL = 2) implementations are limited to 333 MHz for all speed grades and I/O bank types. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 17 IOB Pad Input/Output/3-State Table 20 (high-range IOB (HR)) and Table 21 (high-performance IOB (HP)) summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.

• T IOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.
• T IOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer.
• T IOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HP I/O banks, the internal DCI termination turn-on time is always faster than TIOTP when the DCITERMDISABLE pin is used. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used. Table 20: IOB High Range (HR) Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE RSDS_25 ns DIFF_HSUL_ ns DIFF_HSUL_ DIFF_MOBILE_ DIFF_MOBILE_ Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 18 DIFF_HSTL_I_ ns DIFF_HSTL_II_ DIFF_HSTL_I_ ns DIFF_HSTL_II_ Table 20: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 19 DIFF_SSTL135_ ns DIFF_SSTL18_ DIFF_SSTL18_ Table 20: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 20 DIFF_SSTL135_ DIFF_SSTL18_I_ DIFF_SSTL18_II Table 20: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 21 Table 21: IOB High Performance (HP) Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE DIFF_HSUL_12_ DIFF_HSUL_12_ DIFF_HSUL_12_ HSTL_II_T_DCI_ HSTL_I_DCI_18_ HSTL_II_DCI_18_ HSTL_II DIFF_HSTL_I_ DIFF_HSTL_II_ DIFF_HSTL_I_ DIFF_HSTL_II_ DIFF_HSTL_I_ DIFF_HSTL_II_ DIFF_HSTL_II Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 22 HSTL_I_DCI_ HSTL_II_DCI_ HSTL_II DIFF_HSTL_I_ DIFF_HSTL_II_ DIFF_HSTL_I_ DIFF_HSTL_II_ DIFF_HSTL_I_ DIFF_HSTL_II_ DIFF_HSTL_II Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 23 SSTL18_II_T_ SSTL135_T_ Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 24 DIFF_SSTL18_ DIFF_SSTL18_ DIFF_SSTL18_ DIFF_SSTL18_ DIFF_SSTL18_ DIFF_SSTL15_ DIFF_SSTL15_T_ DIFF_SSTL135_D DIFF_SSTL135_ DIFF_SSTL12_ DIFF_SSTL12_ SSTL18_II_T_ SSTL135_T_ DIFF_SSTL18_ DIFF_SSTL18_ Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 25 Table 22 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HP I/O banks, the internal DCI termination turn-off time is always faster than TIOTPHZ when the DCITERMDISABLE pin is used. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used. DIFF_SSTL18_I_ DIFF_SSTL18_II_ DIFF_SSTL18_II_ DIFF_SSTL15_D DIFF_SSTL15_T_ DIFF_SSTL135_ DIFF_SSTL135_ DIFF_SSTL12_ DIFF_SSTL12_T_ Table 22: IOB 3-state Output Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE TIOIBUFDISABLE_HR IBUF turn-on time from IBUFDISABLE to O output for HR I/O banks TIOIBUFDISABLE_HP IBUF turn-on time from IBUFDISABLE to O output for HP I/O banks Table 21: IOB High Performance (HP) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE -3 -2/ -2LE -1 -1M/ -1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 26 I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 23 shows the test setup parameters used for measuring input delay. Table 23: Input Delay Measurement Methodology Description I/O Standard Attribute V L(1)(2) VH(1)(2) VMEAS (1)(4)(6) VREF (1)(3)(5) LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 – LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 – LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 – LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 – LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 – LVTTL, 3.3V LVTTL 0.1 3.2 1.65 – MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9 – PCI33, 3.3V PCI33_3 0.1 3.2 1.65 – HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 HSTL, Class I & II, 1.5V HSTL_I, HSTL_II V REF –0 . 6 5 V REF +0 . 6 5 V REF 0.75 HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 V REF –0 . 8 V REF +0 . 8 V REF 0.90 HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 SSTL, 1.35V SSTL135, SSTL135_R V REF – 0.575 V REF + 0.575 V REF 0.675 SSTL, 1.5V SSTL15, SSTL15_R V REF –0 . 6 5 V REF +0 . 6 5 V REF 0.75 SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II V REF –0 . 8 V REF +0 . 8 V REF 0.90 DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I, DIFF_HSTL_II DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0 (6) – RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0 (6) – Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 28 5. Compare the results of step 2 and step 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace. Table 24: Output Delay Measurement Methodology Description I/O Standard Attribute RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) LVCMOS, 1.2V LVCMOS12 1M 0 0.6 0 LVCMOS/LVDCI/HSLVDCI, 1.5V LVCMOS 15, LVDCI_15, HSLVDCI_15 1M 0 0.75 0 LVCMOS/LVDCI/HSLVDCI, 1.8V LVCMOS 18, LVDCI_15, HSLVDCI_18 1M 0 0.9 0 LVCMOS, 2.5V LVCMOS25 1M 0 1.25 0 LVCMOS, 3.3V LVCMOS33 1M 0 1.65 0 LVTTL, 3.3V LVTTL 1M 0 1.65 0 PCI33, 3.3V PCI33_3 25 10 1.65 0 HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 V REF 0.6 HSTL, Class I, 1.5V HSTL_I 50 0 V REF 0.75 HSTL, Class II, 1.5V HSTL_II 25 0 V REF 0.75 HSTL, Class I, 1.8V HSTL_I_18 50 0 V REF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 V REF 0.9 HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 V REF 0.6 SSTL12, 1.2V SSTL12 50 0 V REF 0.6 SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 V REF 0.675 SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 V REF 0.75 SSTL (Stub Series Terminated Logic), Class I & Class II, 1.8V SSTL18_I, SSTL18_II 50 0 V REF 0.9 DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 V REF 0.9 DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 V REF 0.6 DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 V REF 0.75 DIFF_HSTL, Class I & II, 1.8V DIFF _HSTL_I_18, DIFF_HSTL_II_18 50 0 V REF 0.9 DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 V REF 0.6 DIFF_SSTL12, 1.2V DIFF_SSTL12 50 0 V REF 0.6 DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 V REF 0.675 DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL1 5, DIFF_SSTL15_R 50 0 V REF 0.75 DIFF_SSTL18, Class I & II, 1.8V DI FF_SSTL18_I, DIFF_SSTL18_II 50 0 V REF 0.9 LVDS (Low-Voltage Differential Signaling), 1.8V LVDS 100 0 0 (2) 0 LVDS, 2.5V LVDS_25 100 0 0 (2) 0 BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0 (2) 0 Mini LVDS, 2.5V MINI_LVDS_25 100 0 0 (2) 0 PPDS_25 PPDS_25 100 0 0 (2) 0 RSDS_25 RSDS_25 100 0 0 (2) 0 TMDS_33 TMDS_33 50 0 0 (2) 3.3 Notes: 1. C REF is the capacitance of the probe, nominally 0 pF. 2. The value given is the differential output voltage. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 29 Input/Output Logic Switching Characteristics Table 25: ILOGIC Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup/Hold TICE1CK/ TICKCE1 CE1 pin Setup/Hold with respect to CLK T TIDOCKE2/ TIOCKDE2 D pin Setup/Hold with respect to CLK without Delay (HP I/O banks only) T IDOCKDE2/ TIOCKDDE2 DDLY pin Setup/Hold with respect to CLK (using IDELAY) (HP I/O banks only) T IDOCKE3/ TIOCKDE3 D pin Setup/Hold with respect to CLK without Delay (HR I/O banks only) T IDOCKDE3/ TIOCKDDE3 DDLY pin Setup/Hold with respect to CLK (using IDELAY) (HR I/O banks only) Combinatorial T IDIE2 D pin to O pin propagation delay, no Delay (HP I/O banks only) TIDIDE2 DDLY pin to O pin propagation delay (using IDELAY) (HP I/O banks only) TIDIE3 D pin to O pin propagation delay, no Delay (HR I/O banks only) TIDIDE3 DDLY pin to O pin propagation delay (using IDELAY) (HR I/O banks only) Sequential Delays TIDLOE2 D pin to Q1 pin using flip-flop as a latch without Delay (HP I/O banks only) TIDLODE2 DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY) (HP I/O banks only) TIDLOE3 D pin to Q1 pin using flip-flop as a latch without Delay (HR I/O banks only) TIDLODE3 DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY) (HR I/O banks only) TRQ_ILOGICE2 SR pin to OQ/TQ out (HP I/O banks only) TGSRQ_ILOGICE2 Global Set/Reset to Q outputs (HP I/O banks only) TRQ_ILOGICE3 SR pin to OQ/TQ out (HR I/O banks only) TGSRQ_ILOGICE3 Global Set/Reset to Q outputs (HR I/O banks only) Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 30 Set/Reset TRPW_ILOGICE2 Minimum Pulse Width, SR inputs (HP I/O banks only) Min TRPW_ILOGICE3 Minimum Pulse Width, SR inputs (HR I/O banks only) Min Table 26: OLOGIC Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup/Hold TODCK/TOCKD D1/D2 pins Setup/Hold with respect to CLK TOOCECK/ TOCKOCE OCE pin Setup/Hold with respect to CLK T OSRCK/TOCKSR SR pin Setup/Hold with respect to CLK TOTCK/TOCKT T1/T2 pins Setup/Hold with respect to CLK TOTCECK/ TOCKTCE TCE pin Setup/Hold with respect to CLK Combinatorial Sequential Delays TRQ_OLOGICE2 SR pin to OQ/TQ out (HP I/O banks only) TGSRQ_OLOGICE2 Global Set/Reset to Q outputs (HP I/O banks only) TRQ_OLOGICE3 SR pin to OQ/TQ out (HR I/O banks only) TGSRQ_OLOGICE3 Global Set/Reset to Q outputs (HR I/O banks only) Set/Reset TRPW_OLOGICE2 Minimum Pulse Width, SR inputs (HP I/O banks only) Min TRPW_OLOGICE3 Minimum Pulse Width, SR inputs (HR I/O banks only) Min Table 25: ILOGIC Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 31 Input Serializer/Deserializer Switching Characteristics Table 27: ISERDES Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to CLKDIV T ISCCK_CE/ TISCKC_CE(2) CE pin Setup/Hold with respect to CLK (for CE1) TISCCK_CE2/ TISCKC_CE2(2) CE pin Setup/Hold with respect to CLKDIV (for CE2) Setup/Hold for Data Lines TISDCK_D/ TISCKD_D D pin Setup/Hold with respect to CLK T ISDCK_DDLY/ TISCKD_DDLY DDLY pin Setup/Hold with respect to CLK (using IDELAY) (1) TISDCK_D_DDR/ TISCKD_D_DDR D pin Setup/Hold with respect to CLK at DDR mode T ISDCK_DDLY_DDR/ TISCKD_DDLY_DDR D pin Setup/Hold with respect to CLK at DDR mode (using IDELAY)(1) Sequential Delays Propagation Delays Notes: 1. Recorded at 0 tap value. 2. T ISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 32 Output Serializer/Deserializer Switching Characteristics Table 28: OSERDES Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup/Hold TOSDCK_D/ TOSCKD_D D input Setup/Hold with respect to CLKDIV T OSDCK_T/ TOSCKD_T(1) T input Setup/Hold with respect to CLK TOSDCK_T2/ TOSCKD_T2(1) T input Setup/Hold with respect to CLKDIV TOSCCK_OCE/ TOSCKC_OCE OCE input Setup/Hold with respect to CLK T OSCCK_S SR (Reset) input Setup with respect to CLKDIV TOSCCK_TCE/ TOSCKC_TCE TCE input Setup/Hold with respect to CLK Sequential Delays T Combinatorial T Notes: 1. T OSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 33 Input/Output Delay Switching Characteristics Table 29: Input/Output Delay Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE IDELAYCTRL FIDELAYCTRL_REF Attribute REFCLK frequency = 200.00(1) Attribute REFCLK frequency = 300.00(1) 300.00 300.00 N/A N/A 300.00 N/A MHz Attribute REFCLK frequency = 400.00(1) 400.00 400.00 N/A N/A 400.00 N/A MHz IDELAYCTRL_REF _PRECISION REFCLK precision ±10 ±10 ±10 ±10 ±10 ±10 MHz IDELAY/ODELAY TIDELAYRESOLUTION IDELAY/ODELAY chain delay resolution 1 / ( 3 2x2xFREF)µ s TIDELAYPAT_JIT and TODELAYPAT_JIT Pattern dependent period jitter in delay chain for clock pattern.(2) 000000 p s per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(3) per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(4) per tap TIDELAY_CLK_MAX/ TODELAY_CLK_MAX Maximum frequency of CLK input to IDELAY/ODELAY T IDCCK_CE / TIDCKC_CE CE pin Setup/Hold with respect to C for IDELAY T ODCCK_CE / TODCKC_CE CE pin Setup/Hold with respect to C for ODELAY T IDCCK_INC/ TIDCKC_INC INC pin Setup/Hold with respect to C for IDELAY T ODCCK_INC/ TODCKC_INC INC pin Setup/Hold with respect to C for ODELAY T IDCCK_RST/ TIDCKC_RST RST pin Setup/Hold with respect to C for IDELAY TODCCK_RST/ TODCKC_RST RST pin Setup/Hold with respect to C for ODELAY TIDDO_IDATAIN Propagation delay through IDELAY Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ps TODDO_ODATAIN Propagation delay through ODELAY Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ps Notes: 1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps. 2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. 3. When HIGH_PERFORMANCE mode is set to TRUE. 4. When HIGH_PERFORMANCE mode is set to FALSE. 5. Delay depends on IDELAY/ODELAY tap setting. See the timing report for actual values. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 34 Table 30: IO_FIFO Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE IO_FIFO Clock to Out Delays Setup/Hold TCCK_D/ TCKC_D TIFFCCK_WREN / TIFFCKC_WREN TOFFCCK_RDEN/ TOFFCKC_RDEN Minimum Pulse Width Maximum Frequency F Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 35 CLB Switching Characteristics Table 31: CLB Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Combinatorial Delays Sequential Delays Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TAS/TAH AN –D N input to CLK on A – D flip-flops TDICK/TCKDI AX –D X input to CLK on A – D flip-flops AX –D X input through MUXs and/or carry logic to CLK on A – D flip-flops TCECK_CLB/ TCKCE_CLB Set/Reset TRQ Delay from SR input to AQ – DQ flip-flops TCEO Delay from CE input to AQ – DQ flip-flops FTOG Toggle frequency (for export control) 1818 1818 1818 1818 1818 1286 MHz Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 36 CLB Distributed RAM Switching Characteristics (SLICEM Only) CLB Shift Register Switching Characteristics (SLICEM Only) Table 32: CLB Distributed RAM Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Sequential Delays Setup and Hold Times Before/After Clock CLK TDS_LRAM/ TDH_LRAM TAS_LRAM/ TAH_LRAM Address An inputs through MUXs and/or carry logic to clock TWS_LRAM/ TWH_LRAM TCECK_LRAM/ TCKCE_LRAM Clock CLK Notes: 1. T SHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path. Table 33: CLB Shift Register Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Sequential Delays TREG_M31 Clock to DMUX output via M31 output Setup and Hold Times Before/After Clock CLK TWS_SHFREG/ TWH_SHFREG TCECK_SHFREG/ TCKCE_SHFREG TDS_SHFREG/ TDH_SHFREG Clock CLK Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 37 Block RAM and FIFO Switching Characteristics Table 34: Block RAM and FIFO Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Block RAM and FIFO Clock-to-Out Delays TRCKO_DO and TRCKO_DO_REG(1) Clock CLK to DOUT output (without output register)(2)(3) Clock CLK to DOUT output (with output register)(4)(5) TRCKO_DO_ECC and TRCKO_DO_ECC_REG Clock CLK to DOUT output with ECC (without output register)(2)(3) Clock CLK to DOUT output with ECC (with output register)(4)(5) TRCKO_DO_CASCOUT and TRCKO_DO_CASCOUT_REG Clock CLK to DOUT output with Cascade (without output register)(2) Clock CLK to DOUT output with Cascade (with output register)(4) TRCKO_FLAGS Clock CLK to FIFO flags outputs(6) TRCKO_POINTERS Clock CLK to FIFO pointers outputs(7) TRCKO_PARITY_ECC Clock CLK to ECCPARITY in ECC encode only mode TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG Clock CLK to BITERR (without output register) Clock CLK to BITERR (with output register) TRCKO_RDADDR_ECC and TRCKO_RDADDR_ECC_REG Clock CLK to RDADDR output with ECC (without output register) Clock CLK to RDADDR output with ECC (with output register) Setup and Hold Times Before/After Clock CLK T RCCK_ADDRA/ TRCKC_ADDRA ADDR inputs(8) 0.38/ 0.27 0.42/ 0.28 0.48/ 0.31 0.48/ 0.38 0.42/ 0.28 0.65/ 0.38 ns, Min TRDCK_DI_WF_NC/ TRCKD_DI_WF_NC Data input setup/hold time when block RAM is configured in WRITE_FIRST or NO_CHANGE mode (9) 0.49/ 0.51 0.55/ 0.53 0.63/ 0.57 0.63/ 0.57 0.55/ 0.53 0.78/ 0.64 ns, Min TRDCK_DI_RF/ TRCKD_DI_RF Data input setup/hold time when block RAM is configured in READ_FIRST mode (9) 0.17/ 0.25 0.19/ 0.29 0.21/ 0.35 0.21/ 0.35 0.19/ 0.29 0.25/ 0.32 ns, Min TRDCK_DI_ECC/ TRCKD_DI_ECC DIN inputs with block RAM ECC in standard mode (9) 0.42/ 0.37 0.47/ 0.39 0.53/ 0.43 0.53/ 0.58 0.47/ 0.39 0.66/ 0.46 ns, Min TRDCK_DI_ECCW/ TRCKD_DI_ECCW DIN inputs with block RAM ECC encode only (9) 0.79/ 0.37 0.87/ 0.39 0.99/ 0.43 0.99/ 0.58 0.87/ 0.39 1.17/ 0.41 ns, Min TRDCK_DI_ECC_FIFO/ TRCKD_DI_ECC_FIFO DIN inputs with FIFO ECC in standard mode (9) 0.89/ 0.47 0.98/ 0.50 1.12/ 0.54 1.12/ 0.69 0.98/ 0.50 1.32/ 0.65 ns, Min Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 38 TRCCK_INJECTBITERR/ TRCKC_INJECTBITERR Inject single/double bit error in ECC mode 0.49/ 0.30 0.55/ 0.31 0.63/ 0.34 0.63/ 0.43 0.55/ 0.31 0.78/ 0.41 ns, Min T RCCK_EN/TRCKC_EN Block RAM Enable (EN) input 0.30/ 0.17 0.33/ 0.18 0.38/ 0.20 0.38/ 0.32 0.33/ 0.18 0.48/ 0.22 ns, Min TRCCK_REGCE/ TRCKC_REGCE CE input of output register 0.21/ 0.13 0.25/ 0.13 0.31/ 0.14 0.31/ 0.19 0.25/ 0.13 0.34/ 0.16 ns, Min TRCCK_RSTREG/ TRCKC_RSTREG Synchronous RSTREG input 0.25/ 0.06 0.27/ 0.06 0.29/ 0.06 0.29/ 0.14 0.27/ 0.06 0.35/ 0.06 ns, Min TRCCK_RSTRAM/ TRCKC_RSTRAM Synchronous RSTRAM input 0.27/ 0.35 0.29/ 0.37 0.31/ 0.39 0.31/ 0.39 0.29/ 0.37 0.34/ 0.40 ns, Min TRCCK_WEA/ TRCKC_WEA Write Enable (WE) input (Block RAM only) 0.38/ 0.15 0.41/ 0.16 0.46/ 0.17 0.46/ 0.29 0.41/ 0.16 0.54/ 0.19 ns, Min TRCCK_WREN/ TRCKC_WREN WREN FIFO inputs 0.39/ 0.25 0.39/ 0.30 0.40/ 0.37 0.40/ 0.49 0.39/ 0.30 0.65/ 0.37 ns, Min TRCCK_RDEN/ TRCKC_RDEN RDEN FIFO inputs 0.36/ 0.26 0.36/ 0.30 0.37/ 0.37 0.37/ 0.49 0.36/ 0.30 0.60/ 0.38 ns, Min Reset Delays TRCO_FLAGS Reset RST to FIFO flags/pointers(10) TRREC_RST/ TRREM_RST FIFO reset recovery and removal timing(11) 1.59/ –0.68 1.76/ –0.68 2.01/ –0.68 2.01/ –0.68 1.76/ –0.68 2.07/ –0.60 ns, Max Maximum Frequency FMAX_BRAM_WF_NC Block RAM (Write first and No change modes) When not in SDP RF mode FMAX_BRAM_RF _PERFORMANCE Block RAM (Read first, Performance mode) When in SDP RF mode but no address overlap between port A and port B FMAX_BRAM_RF_ DELAYED_WRITE Block RAM (Read first, Delayed_write mode) When in SDP RF mode and there is possibility of overlap between port A and port B addresses F MAX_CAS_WF_NC Block RAM Cascade (Write first, No change mode) When cascade but not in RF mode FMAX_CAS_RF _PERFORMANCE Block RAM Cascade (Read first, Performance mode) When in cascade with RF mode and no possibility of address overlap/one port is disabled Table 34: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 39 FMAX_CAS_RF_ DELAYED_WRITE When in cascade RF mode and there is a possibility of address overlap between port A and port B F FMAX_ECC Block RAM and FIFO in ECC configuration Notes: 1. The timing report shows all of these parameters as T RCKO_DO. 2. T RCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. 3. These parameters also apply to synchronous FIFO with DO_REG = 0. 4. T RCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. 5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. 6. T RCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. 7. T RCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. 8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 9. These parameters include both A and B inputs as well as the parity inputs of A and B. 10. T RCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock e dges of the slowest clock (WRCLK or RDCLK). Table 34: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 40 DSP48E1 Switching Characteristics Table 35: DSP48E1 Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK 0.24/ 0.12 0.27/ 0.14 0.31/ 0.16 0.33/ 0.18 0.27/ 0.14 0.38/ 0.12 ns TDSPDCK_B_BREG/ TDSPCKD_B_BREG B input to B register CLK 0.28/ 0.13 0.32/ 0.14 0.39/ 0.15 0.41/ 0.18 0.32/ 0.14 0.51/ 0.16 ns TDSPDCK_C_CREG/ TDSPCKD_C_CREG C input to C register CLK 0.15/ 0.15 0.17/ 0.17 0.20/ 0.20 0.20/ 0.22 0.17/ 0.17 0.31/ 0.21 ns TDSPDCK_D_DREG/ TDSPCKD_D_DREG D input to D register CLK 0.21/ 0.19 0.27/ 0.22 0.35/ 0.26 0.35/ 0.27 0.27/ 0.22 0.46/ 0.20 ns TDSPDCK_ACIN_AREG/ TDSPCKD_ACIN_AREG ACIN input to A register CLK 0.21/ 0.12 0.24/ 0.14 0.27/ 0.16 0.30/ 0.16 0.24/ 0.14 0.31/ 0.12 ns TDSPDCK_BCIN_BREG/ TDSPCKD_BCIN_BREG BCIN input to B register CLK 0.22/ 0.13 0.25/ 0.14 0.30/ 0.15 0.32/ 0.15 0.25/ 0.14 0.34/ 0.16 ns Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{A, B}_MREG_MULT/ {A, B} input to M register CLK using multiplier 2.04/ –0.01 2.34/ –0.01 2.79/ –0.01 2.79/ –0.01 2.34/ –0.01 3.66/ –0.06 ns T DSPDCK_{A, D}_ADREG/ TDSPCKD_{A, D}_ADREG {A, D} input to AD register CLK 1.09/ –0.02 1.25/ –0.02 1.49/ –0.02 1.49/ –0.02 1.25/ –0.02 1.94/ –0.23 ns Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{A, B}_PREG_MULT/ TDSPCKD_{A, B} _PREG_MULT {A, B,} input to P register CLK using multiplier 3.41/ –0.24 3.90/ –0.24 4.64/ –0.24 4.64/ –0.24 3.90/ –0.24 5.89/ –0.41 ns TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT D input to P register CLK using multiplier 3.33/ –0.62 3.81/ –0.62 4.53/ –0.62 4.53/ –0.62 3.81/ –0.62 5.70/ –1.42 ns T DSPDCK_{A, B} _PREG/ TDSPCKD_{A, B} _PREG A or B input to P register CLK not using multiplier 1.47/ –0.24 1.68/ –0.24 2.00/ –0.24 2.00/ –0.24 1.68/ –0.24 2.37/ –0.41 ns TDSPDCK_C_PREG/ TDSPCKD_C_PREG C input to P register CLK not using multiplier 1.30/ –0.22 1.49/ –0.22 1.78/ –0.22 1.78/ –0.22 1.49/ –0.22 2.11/ –0.36 ns T DSPDCK_PCIN_PREG/ TDSPCKD_PCIN_PREG PCIN input to P register CLK 1.12/ –0.13 1.28/ –0.13 1.52/ –0.13 1.52/ –0.13 1.28/ –0.13 1.81/ –0.21 ns Setup and Hold Times of the CE Pins TDSPDCK_{CEA;CEB}_{AREG;BREG}/ {CEA; CEB} input to {A; B} register CLK 0.30/ 0.05 0.36/ 0.06 0.44/ 0.09 0.44/ 0.09 0.36/ 0.06 0.55/ 0.09 ns TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG CEC input to C register CLK 0.24/ 0.08 0.29/ 0.09 0.36/ 0.11 0.36/ 0.11 0.29/ 0.09 0.43/ 0.11 ns TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG CED input to D register CLK 0.31/ –0.02 0.36/ –0.02 0.44/ –0.02 0.44/ 0.02 0.36/ –0.02 0.58/ 0.12 ns TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG CEM input to M register CLK 0.26/ 0.15 0.29/ 0.17 0.33/ 0.20 0.33/ 0.20 0.29/ 0.17 0.39/ 0.25 ns TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG CEP input to P register CLK 0.31/ 0.01 0.36/ 0.01 0.45/ 0.01 0.45/ 0.01 0.36/ 0.01 0.54/ 0.00 ns Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 41 Setup and Hold Times of the RST Pins TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG} {RSTA, RSTB} input to {A, B} register CLK 0.34/ 0.10 0.39/ 0.11 0.47/ 0.13 0.47/ 0.14 0.39/ 0.11 0.53/ 0.34 ns TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG RSTC input to C register CLK 0.06/ 0.22 0.07/ 0.24 0.08/ 0.26 0.08/ 0.26 0.07/ 0.24 0.08/ 0.31 ns TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG RSTD input to D register CLK 0.37/ 0.06 0.42/ 0.06 0.50/ 0.07 0.50/ 0.07 0.42/ 0.06 0.57/ 0.07 ns TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG RSTM input to M register CLK 0.18/ 0.18 0.20/ 0.21 0.23/ 0.24 0.23/ 0.24 0.20/ 0.21 0.24/ 0.29 ns TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG RSTP input to P register CLK 0.24/ 0.01 0.26/ 0.01 0.30/ 0.01 0.30/ 0.11 0.26/ 0.01 0.37/ 0.00 ns Combinatorial Delays from Input Pins to Output Pins TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output using multiplier TDSPDO_D_P_MULT D input to P output using multiplier TDSPDO_A_P A input to P output not using multiplier Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT, BCOUT} output TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to CARRYCASCOUT output using multiplier TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT output using multiplier TDSPDO_{A, B}_CARRYCASCOUT {A, B} input to CARRYCASCOUT output not using multiplier TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT output Combinatorial Delays from Cascading Input Pins to All Output Pins TDSPDO_ACIN_P_MULT ACIN input to P output using multiplier TDSPDO_ACIN_P ACIN input to P output not using multiplier TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to CARRYCASCOUT output using multiplier T DSPDO_ACIN_CARRYCASCOUT ACIN input to CARRYCASCOUT output not using multiplier TDSPDO_PCIN_CARRYCASCOUT PCIN input to CARRYCASCOUT output Table 35: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 42 Clock to Outs from Output Register Clock to Output Pins TDSPCKO_CARRYCASCOUT_PREG CLK PREG to CARRYCASCOUT output Clock to Outs from Pipeline Register Clock to Output Pins TDSPCKO_CARRYCASCOUT_MREG CLK MREG to CARRYCASCOUT output TDSPCKO_P_ADREG_MULT CLK ADREG to P output using multiplier TDSPCKO_CARRYCASCOUT_ ADREG_MULT CLK ADREG to CARRYCASCOUT output using multiplier Clock to Outs from Input Register Clock to Output Pins TDSPCKO_P_AREG_MULT CLK AREG to P output using multiplier TDSPCKO_P_BREG CLK BREG to P output not using multiplier TDSPCKO_P_CREG CLK CREG to P output not using multiplier TDSPCKO_P_DREG_MULT CLK DREG to P output using multiplier Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUT; BCOUT} _{AREG; BREG} CLK (ACOUT, BCOUT) to {A,B} register output TDSPCKO_CARRYCASCOUT_ {AREG, BREG}_MULT CLK (AREG, BREG) to CARRYCASCOUT output using multiplier TDSPCKO_CARRYCASCOUT_ BREG CLK BREG to CARRYCASCOUT output not using multiplier TDSPCKO_CARRYCASCOUT _ DREG_MULT CLK DREG to CARRYCASCOUT output using multiplier TDSPCKO_CARRYCASCOUT_ CREG CLK CREG to CARRYCASCOUT output Maximum Frequency FMAX_MULT_NOMREG Two register multiply without MREG FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect FMAX_PREADD_MULT_ NOADREG_PATDET Without ADREG with pattern detect Table 35: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 43 Clock Buffers and Networks FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG) FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect Table 36: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE TBCCCK_CE/ TBCCKC_CE(1) TBCCCK_S/ TBCCKC_S(1) Maximum Frequency Notes: 1. T BCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold time s are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. 2. T BGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. Table 37: Input/Output Clock Switching Characteristics (BUFIO) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Maximum Frequency Table 38: Regional Clock Buffer Switching Characteristics (BUFR) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE TBRCKO_O Clock to out delay from I to O TBRCKO_O_BYP Clock to out delay from I to O with Divide Bypass attribute set Table 35: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 44 Maximum Frequency Notes: 1. The maximum input frequency to the BUFR and BUFMR is the BUFIO F MAX frequency except for the BUFMR in the -2LE at 0.9V, which has a maximum input frequency of 667 MHz. Table 39: Horizontal Clock Buffer Switching Characteristics (BUFH) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE TBHCCK_CE/ TBHCKC_CE Maximum Frequency Table 40: Duty Cycle Distortion and Clock-Tree Skew Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE TDCD_CLK Global Clock Tree Duty Cycle Distortion(1) TCKSKEW Global Clock Tree Skew(2) XC7K70T 0.29 0.40 0.40 N/A N/A 0.47 ns T DCD_BUFIO I/O clock tree duty cycle distortion TBUFIOSKEW I/O clock tree skew across one clock region TDCD_BUFR Regional clock tree duty cycle distortion Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. The T CKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer tools to evaluate clock skew specific to your application. Table 38: Regional Clock Buffer Switching Characteristics (BUFR) (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 45 MMCM Switching Characteristics Table 41: MMCM Specification Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE MMCM_FINMAX Maximum Input Clock Frequency MMCM_FINMIN Minimum Input Clock Frequency MMCM_FINJITTER Maximum Input Clock Period Jitter < 20% of clock input period or 1 ns Max MMCM_FINDUTY Allowable Input Duty Cycle: 10–49 MHz Allowable Input Duty Cycle: 50–199 MHz Allowable Input Duty Cycle: 200–399 MHz Allowable Input Duty Cycle: 400–499 MHz Allowable Input Duty Cycle: >500 MHz MMCM_FMIN_PSCLK Minimum Dynamic Phase Shift Clock Frequency MMCM_FMAX_PSCLK Maximum Dynamic Phase Shift Clock Frequency MMCM_FVCOMIN Minimum MMCM VCO Frequency MMCM_FVCOMAX Maximum MMCM VCO Frequency MMCM_FBANDWIDTH Low MMCM Bandwidth at Typical(1) High MMCM Bandwidth at Typical(1) MMCM_TSTATPHAOFFSET Static Phase Offset of the MMCM Outputs(2) MMCM_TOUTJITTER MMCM Output Jitter Note 3 MMCM_TOUTDUTY MMCM Output Clock Duty Cycle Precision(4) MMCM_FOUTMAX MMCM Maximum Output Frequency MMCM_FOUTMIN MMCM Minimum Output Frequency(5)(6) MMCM_TEXTFDVAR External Clock Feedback Variation < 20% of clock input period or 1 ns Max MMCM_FPFDMAX Maximum Frequency at the Phase Frequency Detector MMCM_FPFDMIN Minimum Frequency at the Phase Frequency Detector Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 46 MMCM_TFBDELAY Maximum Delay in the Feedback Path 3 ns Max or one CLKIN cycle MMCM Switching Characteristics Setup and Hold TMMCMDCK_PSEN/ TMMCMCKD_PSEN Setup and Hold of Phase Shift Enable T MMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC Setup and Hold of Phase Shift Increment/Decrement T MMCMCKO_PSDONE Phase Shift Clock-to-Out of PSDONE Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK TMMCMDCK_DADDR/ TMMCMCKD_DADDR TMMCMDCK_DI/ TMMCMCKD_DI TMMCMDCK_DEN/ TMMCMCKD_DEN TMMCMDCK_DWE/ TMMCMCKD_DWE Notes: 1. The MMCM does not filter typical spread-spectrum input clocks bec ause they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any MMCM outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. See www.xilinx.com/products/intellectual-property/clocking_wizard.htm. 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. 6. When CLKOUT4_CASCADE = TRUE, MMCM_F OUTMIN is 0.036 MHz. Table 41: MMCM Specification (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 47 PLL Switching Characteristics Table 42: PLL Specification Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE PLL_FINJITTER Maximum Input Clock Period Jitter < 20% of clock input period or 1 ns Max PLL_FINDUTY Allowable Input Duty Cycle: 19–49 MHz Allowable Input Duty Cycle: 50–199 MHz Allowable Input Duty Cycle: 200–399 MHz Allowable Input Duty Cycle: 400–499 MHz Allowable Input Duty Cycle: >500 MHz PLL_TSTATPHAOFFSET Static Phase Offset of the PLL Outputs(2) PLL_TOUTJITTER PLL Output Jitter Note 3 PLL_TOUTDUTY PLL Output Clock Duty Cycle Precision(4) PLL_TLOCKMAX PLL Maximum Lock Time 100 100 100 100 100 100 µs PLL_FOUTMIN PLL Minimum Output Frequency(5) PLL_TEXTFDVAR External Clock Feedback Variation < 20% of clock input period or 1 ns Max PLL_FPFDMAX Maximum Frequency at the Phase Frequency Detector PLL_FPFDMIN Minimum Frequency at the Phase Frequency Detector PLL_TFBDELAY Maximum Delay in the Feedback Path 3 ns Max or one CLKIN cycle Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK TPLLCCK_DADDR/ TPLLCKC_DADDR TPLLCCK_DI/ TPLLCKC_DI TPLLCCK_DEN/ TPLLCKC_DEN Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 48 TPLLCCK_DWE/ TPLLCKC_DWE Notes: 1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any PLL outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. See www.xilinx.com/products/intellectual-property/clocking_wizard.htm 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. Table 42: PLL Specification (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 49 Device Pin-to-Pin Output Parameter Guidelines Table 43: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOF Clock-capable clock input and OUTFF at pins/banks closest to the BUFGs without MMCM/PLL (near clock region) XC7K70T 4.98 5.49 6.17 N/A N/A 7.04 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475). Table 44: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOFFAR Clock-capable clock input and OUTFF at pins/banks farthest from the BUFGs without MMCM/PLL (far clock region) XC7K70T 5.29 5.83 6.55 N/A N/A 7.47 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Refer to the Die Level Bank Numbering Overview section of the 7 Series FPGA Packaging and Pinout Specification (UG475). Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 50 Table 45: Clock-Capable Clock Input to Output Delay With MMCM Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM XC7K70T 0.95 0.95 0.95 N/A N/A 1.74 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. MMCM output jitter is already included in the timing calculation. Table 46: Clock-Capable Clock Input to Output Delay With PLL Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. TICKOFPLLCC Clock-capable clock input and OUTFF with PLL XC7K70T 0.84 0.84 0.84 N/A N/A 1.45 ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is already included in the timing calculation. Table 47: Pin-to-Pin, Clock-to-Out using BUFIO Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 51 Device Pin-to-Pin Input Parameter Guidelines Table 48: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks Symbol Descrip tion Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) TPSFD/TPHFD Full Delay (Legacy Delay or Default Delay) Global Clock Input and IFF(2) without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch. Table 49: Clock-Capable Clock Input Setup and Hold With MMCM Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) TPSMMCMCC/ TPHMMCMCC No Delay clock- capable clock input and IFF (2) with MMCM Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle di stortion incurred using various standards. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 52 Table 50: Clock-Capable Clock Input Setup and Hold With PLL Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1) TPSPLLCC/ TPHPLLCC No Delay clock-capable clock input and IFF (2) with PLL Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. Table 51: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard. TPSCS/TPHCS Setup/Hold of I/O clock for HR I/O banks Setup/Hold of I/O clock for HP I/O banks Table 52: Sample Window Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1LM -2LI -2LE TSAMP_BUFIO Sampling Error at Receiver Pins using BUFIO(2) Notes: 1. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, tempera ture, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. 2. This parameter indicates the total sampling error of the Kintex-7 FPGAs DDR input registers, measured across voltage, tempera ture, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 53 Additional Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for Kintex-7 FPGA clock transmitter and receiver data-valid windows. Table 53: Package Skew Symbol Description Devi ce Package Value Units FBG676 135 ps XC7K160T FBG484 118 ps FBG676 136 ps FFG676 161 ps XC7K325T FBG676 146 ps FFG676 154 ps FBG900 163 ps FFG900 161 ps XC7K355T FFG901 149 ps XC7K410T FBG676 165 ps FFG676 168 ps FBG900 151 ps FFG900 146 ps XC7K420T FFG901 149 ps FFG1156 145 ps XC7K480T FFG901 149 ps FFG1156 145 ps XQ7K325T RF676 154 ps RF900 161 ps XQ7K410T RF676 168 ps RF900 146 ps Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. 2. Package delay information is available for these device/package combinations. This information can be used to deskew the pack age. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 55 Table 55 summarizes the DC specifications of the clock input of the GTX transceiver. Consult the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) for further details. GTX Transceiver Switching Characteristics Consult the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) for further information. Table 55: GTX Transceiver Clock DC Input Level Specification Symbol DC Parameter Min Typ Max Units VIDIFF Differential peak-to-peak input voltage 250 – 2000 mV RIN Differential input resistance – 100 – Ω CEXT Required external AC coupling capacitor – 100 – nF Table 56: GTX Transceiver Performance Symbol Description Output Divider Speed Grade(1) Units -3 (1.0V) -2 (1.0V) -2LE (1.0V) -2LI (0.95V) -1 (1.0V)(2) -1M (1.0V)(2) -1LM (1.0V)(2) -2LE (0.9V)(3) Package Type FF FBG484 FBG676 FBG900 FF RF FBG484 FBG676 FBG900 FF RF FB FF RF FB FGTXMAX(4) Maximum GTX transceiver data rate FGTXMIN(4) Minimum GTX transceiver data rate FGTXCRANGE CPLL line rate range 1 3.2–6.6 Gb/s 2 1.6–3.3 Gb/s 40 . 8 – 1 . 6 5 G b / s 8 0.5–0.825 Gb/s

16 N/A Gb/s

F GTXQRANGE1 QPLL line rate range 1 1 5.93– 8.0 5.93– 8.0 5.93– 6.6 5.93– 8.0 5.93– 6.6 5.93– 8.0 5.93– 6.6 5.93–6.6 Gb/s

16 N/A N/A N/A N/A Gb/s

F GTXQRANGE2 QPLL line rate range 2(7) 1 9.8– 12.5 9.8– 10.3125 N/A 9.8– 10.3125 N/A N/A N/A Gb/s 4 2.45–3.125 2.45–2.578125 N/A N/A Gb/s 8 1.225–1.5625 1.225–1.2890625 N/A N/A Gb/s 16 0.6125–0.78125 0.6125– 0.64453125 N/A N/A Gb/s F GCPLLRANGE GTX transceiver CPLL frequency range FGQPLLRANGE1 GTX transceiver QPLL frequency range 1 Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 56 FGQPLLRANGE2 GTX transceiver QPLL frequency range 2 9.8–12.5 9.8–10.3125 N/A N/A GHz Notes: 1. Voltages specified for speed grades are V CCINT. 2. The -1 speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s. 3. The -2LE (0.9V) speed grade requires a 4-byte internal data width for operation above 3.8 Gb/s. 4. Data rates between 8.0 Gb/s and 9.8 Gb/s are not available. 5. For line rates greater than 10.3125 Gb/s, V MGTAVCC is 1.05V nominal (see Table 2). 6. The FBG484 package supports data rates greater than 6.6 Gb/s in the -2 and -3 speed grades (requires Vivado Design Suite 2017.1 or later). 7. For QPLL line rate range 2, the maximum line rate with the divider N set to 66 is 10.3125 Gb/s. Table 57: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1/-1M/-1LM -2LI -2LE Table 58: GTX Transceiver Reference Clock Switching Characteristics Symbol Description Conditions All Speed Grades Units Min Typ Max FGCLK Reference clock frequency range -3 speed grade 60 – 700 MHz All other speed grades 60 – 670 MHz TRCLK Reference clock rise time 20% – 80% – 200 – ps TFCLK Reference clock fall time 80% – 20% – 200 – ps TDCREF Reference clock duty cycle Tr ansceiver PLL only 40 50 60 % X-Ref Target - Figure 5 Figure 5: Reference Clock Timing Parameters Table 56: GTX Transceiver Performance (Cont’d) Symbol Description Output Divider Speed Grade(1) Units -3 (1.0V) -2 (1.0V) -2LE (1.0V) -2LI (0.95V) -1 (1.0V)(2) -1M (1.0V)(2) -1LM (1.0V)(2) -2LE (0.9V)(3) Package Type FF FBG484 FBG676 FBG900 FF RF FBG484 FBG676 FBG900 FF RF FB FF RF FB ds182_03_042712 80% 20% T FCLK T RCLK Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 57 Table 59: GTX Transceiver PLL /Lock Time Adaptation Symbol Description Conditions All Speed Grades Units Min Typ Max TLOCK Initial PLL lock – – 1 ms TDLOCK Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE). After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. – 50,000 37 x10 6 UI Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled. – 50,000 2.3 x10 6 UI Table 60: GTX Transceiver User Clock Switching Characteristics(1)(2) Symbol Description Conditions Speed Grade Units1.0V 0.95V 0.9V FTXIN TXUSRCLK maximum frequency FRXIN RXUSRCLK maximum frequency FTXIN2 TXUSRCLK2 maximum frequency FRXIN2 RXUSRCLK2 maximum frequency Notes: 1. Clocking must be implemented as described in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476). 2. These frequencies are not supported for all possible transceiver configurations. 4. For speed grade -1, a 16-bit data path can only be used for speeds less than 5.0 Gb/s. 5. For speed grade -2LE (0.9V), a 16-bit data path can only be used for speeds less than 3.8 Gb/s. Table 61: GTX Transceiver Transmitter Switching Characteristics Symbol Description Cond ition Min Typ Max Units FGTXTX Serial data rate range 0.500 – F GTXMAX Gb/s TRTX TX Rise time 20%–80% – 40 – ps TFTX TX Fall time 80%–20% – 40 – ps TLLSKEW TX lane-to-lane skew(1) – – 500 ps TJ12.5 Total Jitter(2)(4)

12.5 Gb/s

– – 0.28 UI DJ12.5 Deterministic Jitter(2)(4) – – 0.17 UI TJ11.18 Total Jitter(2)(4)

11.18 Gb/s

– – 0.28 UI DJ11.18 Deterministic Jitter(2)(4) – – 0.17 UI Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 58 TJ10.3125 Total Jitter(2)(4)

10.3125 Gb/s

– – 0.28 UI DJ10.3125 Deterministic Jitter(2)(4) – – 0.17 UI TJ9.953 Total Jitter(2)(4)

9.953 Gb/s

– – 0.28 UI DJ9.953 Deterministic Jitter(2)(4) – – 0.17 UI TJ9.8 Total Jitter(2)(4)

9.8 Gb/s

– – 0.28 UI DJ9.8 Deterministic Jitter(2)(4) – – 0.17 UI TJ8.0 Total Jitter(2)(4)

8.0 Gb/s

– – 0.30 UI DJ8.0 Deterministic Jitter(2)(4) – – 0.15 UI TJ6.6_QPLL Total Jitter(2)(4)

6.6 Gb/s

– – 0.28 UI DJ6.6_QPLL Deterministic Jitter(2)(4) – – 0.17 UI TJ6.6_CPLL Total Jitter(3)(4) – – 0.30 UI DJ6.6_CPLL Deterministic Jitter(3)(4) – – 0.15 UI TJ5.0 Total Jitter(3)(4)

5.0 Gb/s

– – 0.30 UI DJ5.0 Deterministic Jitter(3)(4) – – 0.15 UI TJ4.25 Total Jitter(3)(4)

4.25 Gb/s

– – 0.30 UI DJ4.25 Deterministic Jitter(3)(4) – – 0.15 UI TJ3.75 Total Jitter(3)(4)

3.75 Gb/s

– – 0.30 UI DJ3.75 Deterministic Jitter(3)(4) – – 0.15 UI TJ3.2 Total Jitter(3)(4) DJ3.2 Deterministic Jitter(3)(4) –– 0 . 1 U I TJ3.2L Total Jitter(3)(4) DJ3.2L Deterministic Jitter(3)(4) – – 0.16 UI TJ2.5 Total Jitter(3)(4) DJ2.5 Deterministic Jitter(3)(4) – – 0.08 UI TJ1.25 Total Jitter(3)(4) DJ1.25 Deterministic Jitter(3)(4) – – 0.06 UI TJ500 Total Jitter(3)(4)

500 Mb/s

–– 0 . 1 U I DJ500 Deterministic Jitter(3)(4) – – 0.03 UI Notes: 1. Using same REFCLK input with TX phase alignment enabled for up to 12 consecutive transmitters (three fully populated GTX Quad s). 2. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 3. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. 4. All jitter values are based on a bit-error ratio of 1e -12. 5. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. 6. CPLL frequency at 1.6 GHz and TXOUT_DIV = 1. 7. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. 8. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4. Table 61: GTX Transceiver Transmitter Switching Characteristics (Cont’d) Symbol Description Cond ition Min Typ Max Units Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 59 Table 62: GTX Transceiver Receiver Switching Characteristics Symbol Description Min Typ Max Units FGTXRX Serial data rate 0.500 – F GTXMAX Gb/s TRXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data – 10 – ns RXOOBVDPP OOB detect threshold peak-to-peak 60 – 150 mV RXSST Receiver spread-spectrum tracking(1) Modulated @ 33 KHz –5000 – 0 ppm RXRL Run length (CID) – – 512 UI RXPPMTOL Data/REFCLK PPM offset tolerance Bit rates ≤ 6.6 Gb/s –1250 – 1250 ppm Bit rates > 6.6 Gb/s and ≤ 8.0 Gb/s –700 – 700 ppm Bit rates > 8.0 Gb/s –200 – 200 ppm SJ Jitter Tolerance(2) JT_SJ12.5 Sinusoidal Jitter (QPLL)(3) 12.5 Gb/s 0.3 – – UI JT_SJ11.18 Sinusoidal Jitter (QPLL)(3) 11.18 Gb/s 0.3 – – UI JT_SJ10.32 Sinusoidal Jitter (QPLL)(3) 10.32 Gb/s 0.3 – – UI JT_SJ9.95 Sinusoidal Jitter (QPLL)(3) 9.95 Gb/s 0.3 – – UI JT_SJ9.8 Sinusoidal Jitter (QPLL)(3) 9.8 Gb/s 0.3 – – UI JT_SJ8.0 Sinusoidal Jitter (QPLL)(3) 8.0 Gb/s 0.44 – – UI JT_SJ6.6_QPLL Sinusoidal Jitter (QPLL)(3) 6.6 Gb/s 0.48 – – UI JT_SJ6.6_CPLL Sinusoidal Jitter (CPLL)(3) 6.6 Gb/s 0.44 – – UI JT_SJ5.0 Sinusoidal Jitter (CPLL)(3) 5.0 Gb/s 0.44 – – UI JT_SJ4.25 Sinusoidal Jitter (CPLL)(3) 4.25 Gb/s 0.44 – – UI JT_SJ3.75 Sinusoidal Jitter (CPLL)(3) 3.75 Gb/s 0.44 – – UI JT_SJ3.2 Sinusoidal Jitter (CPLL)(3) 3.2 Gb/s(4) 0.45 – – UI JT_SJ3.2L Sinusoidal Jitter (CPLL)(3) 3.2 Gb/s(5) 0.45 – – UI JT_SJ2.5 Sinusoidal Jitter (CPLL)(3) 2.5 Gb/s(6) 0.5 – – UI JT_SJ1.25 Sinusoidal Jitter (CPLL)(3) 1.25 Gb/s(7) 0.5 – – UI JT_SJ500 Sinusoidal Jitter (CPLL)(3) 500 Mb/s 0.4 – – UI SJ Jitter Tolerance with Stressed Eye(2) JT_TJSE3.2 Total Jitter with Stressed Eye(8) 3.2 Gb/s 0.70 – – UI JT_TJSE6.6 6.6 Gb/s 0.70 – – UI JT_SJSE3.2 Sinusoidal Jitter with Stressed Eye(8) 3.2 Gb/s 0.1 – – UI JT_SJSE6.6 6.6 Gb/s 0.1 – – UI Notes: 1. Using RXOUT_DIV = 1, 2, and 4. 2. All jitter values are based on a bit error ratio of 1e –12. 3. The frequency of the injected sinusoidal jitter is 10 MHz. 4. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. 5. CPLL frequency at 1.6 GHz and RXOUT_DIV = 1. 6. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. 7. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. 8. Composite jitter with RX in LPM or DFE mode. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 60 GTX Transceiver Protocol Jitter Characteristics For Table 63 through Table 68, the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) contains recommended settings for optimal usage of protocol specific characteristics. Table 63: Gigabit Ethernet Protocol Characteristics Description Line Rate (Mb/s) Min Max Units Gigabit Ethernet Transmitter Jitter Generation Total transmitter jitter (T_TJ) 1250 – 0.24 UI Gigabit Ethernet Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 1250 0.749 – UI Table 64: XAUI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units XAUI Transmitter Jitter Generation Total transmitter jitter (T_TJ) 3125 – 0.35 UI XAUI Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 3125 0.65 – UI Table 65: PCI Express Protocol Characteristics(1) Standard Description Line Rate (Mb/s) Min Max Units PCI Express Transmitter Jitter Generation PCI Express Gen 1 Total transmitter jitter 2500 – 0.25 UI PCI Express Gen 2 Total transmitter jitter 5000 – 0.25 UI PCI Express Gen 3 Total transmitter jitter uncorrelated 8000 – 31.25 ps Deterministic transmitter jitter uncorrelated – 12 ps PCI Express Receiver High Frequency Jitter Tolerance PCI Express Gen 1 Total receiver jitter tolerance 2500 0.65 – UI PCI Express Gen 2(2) Receiver inherent timing error 5000 0.40 – UI Receiver inherent deterministic timing error 0.30 – UI PCI Express Gen 3 Receiver sinusoidal jitter tolerance 0.03 MHz–1.0 MHz 8000 1.00 – UI

1.0 MHz–10 MHz Note 3 –U I

10 MHz–100 MHz 0.10 – UI Notes: 1. Tested per card electromechanical (CEM) methodology. 2. Using common REFCLK. 3. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 61 Table 66: CEI-6G and CEI-11G Protocol Characteristics Description Line Rate (M b/s) Interface Min Max Units CEI-6G Transmitter Jitter Generation Total transmitter jitter(1) 4976–6375 CEI-6G-SR – 0.3 UI CEI-6G-LR – 0.3 UI CEI-6G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(1) 4976–6375 CEI-6G-SR 0.6 – UI CEI-6G-LR 0.95 – UI CEI-11G Transmitter Jitter Generation Total transmitter jitter(2) 9950–11100 CEI-11G-SR – 0.3 UI CEI-11G-LR/MR – 0.3 UI CEI-11G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(2) 9950–11100 CEI-11G-SR 0.65 – UI CEI-11G-MR 0.65 – UI CEI-11G-LR 0.825 – UI Notes: 1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock. 2. Tested at line rate of 9950 Mb/s using 155.46875 MHz reference clock and 11100 Mb/s using 173.4375 MHz reference clock. Table 67: SFP+ Protocol Characteristics Description Line Rate (Mb/s) Min Max Units SFP+ Transmitter Jitter Generation Total transmitter jitter 9830.40(1) –0 . 2 8 U I 9953.00 10312.50 10518.75 11100.00 SFP+ Receiver Frequency Jitter Tolerance Total receiver jitter tolerance 9830.40(1) 0.7 – UI 9953.00 10312.50 10518.75 11100.00 Notes: 1. Line rated used for CPRI over SFP+ applications. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 62 Integrated Interface Block for PCI Express Designs Switching Characteristics More information and documentation on solutions for PCI Express designs can be found at: www.xilinx.com/products/technology/pci-express.html Table 68: CPRI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units CPRI Transmitter Jitter Generation Total transmitter jitter 614.4 – 0.35 UI 1228.8 – 0.35 UI 2457.6 – 0.35 UI 3072.0 – 0.35 UI 4915.2 – 0.3 UI 6144.0 – 0.3 UI 9830.4 – Note 1 UI CPRI Receiver Frequency Jitter Tolerance Total receiver jitter tolerance 614.4 0.65 – UI 1228.8 0.65 – UI 2457.6 0.65 – UI 3072.0 0.65 – UI 4915.2 0.95 – UI 6144.0 0.95 – UI

9830.4 Note 1 –U I

Notes: 1. Tested per SFP+ specification, see Table 67. Table 69: Maximum Performance for PCI Express Designs(1) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1/-1M/-1LM -2LI -2LE Notes: 1. Refer to the 7 Series FPGAs Integrated Block for PCI Express Product Guide (PG054) for specific supported core configurations. Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 63 XADC Specifications Table 70: XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units VCCADC = 1.8V ± 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, Tj = –40°C to 100°C, Typical values at Tj=+40°C ADC Accuracy(1) Resolution 12 – – Bits Integral Nonlinearity(2) INL – – ±3 LSBs Differential Nonlinearity DNL No missing codes, guaranteed monotonic – – ±1 LSBs Offset Error Offset calibration enabled – – ±6 LSBs Gain Error Gain calibration disabled – – ±0.5 % Offset Matching Offset calibration enabled – – 4 LSBs Gain Matching Gain calibration disabled – – 0.3 % Sample Rate –– 1 M S / s Signal to Noise Ratio (2) SNR F SAMPLE = 500KS/s, FIN = 20KHz 60 – – dB RMS Code Noise External 1.25V reference – – 2 LSBs On-chip reference – 3 – LSBs Total Harmonic Distortion(2) THD F SAMPLE = 500KS/s, FIN = 20KHz – 70 – dB ADC Accuracy at Extended Temperatures Resolution T j = –55°C to 125°C 10 – – Bits Integral Nonlinearity(2) INL T j = –55°C to 125°C – – ±1 LSB (at 10 bits)Differential Nonlinearity DNL No mi ssing codes, guaranteed monotonic, Tj = –55°C to 125°C ––± 1 Analog Inputs(3) ADC Input Ranges Unipolar operation 0 – 1 V Bipolar operation –0.5 – +0.5 V Unipolar common mode range (FS input) 0 – +0.5 V Bipolar common mode range (FS input) +0.5 – +0.6 V Maximum External Channel Input Ranges Adjacent channels set within these ranges should not corrupt measurements on adjacent channels –0.1 – V CCADC V Auxiliary Channel Full Resolution Bandwidth FRBW 250 – – KHz On-Chip Sensors Temperature Sensor Error Tj = –40°C to 100°C – – ±4 °C Supply Sensor Error Measurement range of V CCAUX 1.8V ±5% Tj = –40°C to +100°C ––± 1 % Measurement range of VCCAUX 1.8V ±5% Tj = –55°C to +125°C ––± 2 % Conversion Rate(4) Conversion Time - Continuous t CONV Number of ADCCLK cycles 26 – 32 Cycles Conversion Time - Event t CONV Number of CLK cycles – – 21 Cycles DRP Clock Frequency DCLK DRP clock frequency 8 – 250 MHz ADC Clock Frequency ADCCLK Derived from DCLK 1 – 26 MHz Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 64 Configuration Switching Characteristics DCLK Duty Cycle 40 – 60 % XADC Reference(5) External Reference V REFP Externally supplied reference voltage 1.20 1.25 1.30 V On-Chip Reference Ground V REFP pin to AGND, Tj = –40°C to 100°C 1.2375 1.25 1.2625 V Notes: 1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled. 2. Only specified for bitstream option XADCEnhancedLinearity = ON. 3. For a detailed description, see the ADC chapter in the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480). 4. For a detailed description, see the Timing chapter in the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480). 5. Any variation in the reference voltage from the nominal V REFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. On-chip reference variation is ±1%. Table 71: Configuration Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1/-1M/-1LM -2LI -2LE Power-up Timing Characteristics TPL(1) Program latency 5 5 5 5 5 ms, Max TPOR(1) Power-on reset (50 ms ramp rate time) 10/50 10/50 10/50 10/50 10/50 ms, Min/Max Power-on reset (1 ms ramp rate time) 10/35 10/35 10/35 10/35 10/35 ms, Min/Max TPROGRAM Program pulse width 250 250 250 250 250 ns, Min CCLK Output (Master Mode) TICCK Master CCLK output delay 150 150 150 150 150 ns, Min TMCCKL Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max TMCCKH Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/ 60 40/60 %, Min/Max Master CCLK frequency for AES encrypted x16 FMCCK_START Master CCLK frequency at start of configuration FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK CCLK Input (Slave Modes) EMCCLK Input (Master Mode) Table 70: XADC Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 65 Internal Configuration Access Port Master/Slave Serial Mode Programming Switching TDCCK/ TCCKD SelectMAP Mode Programming Switching TSMDCCK/ TSMCCKD TSMCSCCK/ TSMCCKCS TSMWCCK/ TSMCCKW TSMCKCSO CSO_B clock to out (330Ω pull-up resistor required) Boundary-Scan Port Timing Specifications TTAPTCK/ TTCKTAP BPI Flash Master Mode Programming Switching TBPICCO(2) A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B clock to out TBPIDCC/ TBPICCD SPI Flash Master Mode Programming Switching TSPIDCC/ TSPICCD STARTUPE2 Ports TUSRCCLKO STARTUPE2 USRCCLKO input to CCLK output FCFGMCLKTOL STARTUPE2 CFGMCLK output frequency tolerance Table 71: Configuration Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1/-1M/-1LM -2LI -2LE Send Feedback

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 66 eFUSE Programming Conditions Table 72 lists the programming conditions specifically for eFUSE. For more information, see the 7 Series FPGA Configuration User Guide (UG470).

Revision History

The following table shows the revision history for this document: Device DNA Access Port Notes: 1. To support longer delays in configuration, use the design solutions described in the 7 Series FPGA Configuration User Guide (UG470). 2. Only during configuration, the last edge is determi ned by a weak pull-up/pull-down resistor in the I/O. Table 72: eFUSE Programming Conditions(1) Symbol Description Min Typ Max Units IFS VCCAUX supply current – – 115 mA t j Temperature range 15 – 125 °C Notes: 1. The FPGA must not be configured during eFUSE programming. Date Version Description 03/01/2011 1.0 Initial Xilinx release. 04/01/2011 1.1 Added the XC7K355T, XC7K420T, and XC7K480T devices throughout data sheet. Added the extended temperature range discussion to page 1. Updated VCCAUX_IO in Table 2. Edits to clarify Power-On/Off Power Supply Sequencing power sequencing discussion. Added ICCAUX_IO and ICCBRAM to Table 6 and Table 7. Updated MMCM_FINDUTY and added FINJITTER, TOUTJITTER, TEXTFDVAR, and Note 3 to Table 41. Removed the SBG324 package from Table 53. Updated the Notice of Disclaimer. 10/04/2011 1.2 Replaced -1L with -2L thr oughout this data sheet. Updated Min/Max values and removed Note 5 from Table 2. Clarified Power-On/Off Power Supply Sequencing power sequencing discussion including adding TVCCO2VCCAUX to Table 8. Updated VICM in Table 12 and Table 13. Added Note 1 to table 12. Updated Table 72 including adding Note 1. Added Absolute Maximum Ratings for GTX Transceivers. Table 21. Removed the I/O Standard Adjustment Measurement Methodology section. Use IBIS for Table 31. Added TRDCK_DI_WF_NC/TRCKD_DI_WF_NC and TRDCK_DI_RF/TRCKD_DI_RF to Table 34. with the SSTL15 standard. Updated units in Table 52.

removed DIFF_SSTL135, DIFF_SSTL18_I, DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. applicable. Updated specifications in Table 71. Updated Note 1 in Table 40. GTX Transceiver Protocol Jitter Characteristics in Table 63 through Table 68. 05/23/2012 1.5 Reorganized entire data sheet including adding Table 47 and Table 51. Table 7. Updated Power-On/Off Power Supply Sequencing, page 7 with regards to GTX transceivers. and -2L (0.9V) speed specifications throughout the document. Table 71 to Table 41 and Table 42. Note 12. Updated parameters in Table 3. Added Table 4 and Table 5. Table 9. Updated many of the specifications in Table 10 and Table 11. in the -2, -2L(1.0V), and -1 speed designations. Added notes and specifications to Table 18 and Table 19. Removed many of the combinatorial delay specifications and TCINCK/TCKCIN from Table 31. Table 60. In Table 62, updated SJ Jitter Tolerance with Stressed Eye section, page 59 and Note 8. ranges. Updated Table 67 including adding Note 1. Updated Table 68 including adding Note 1. In Table 70 updated Note 1 and added Note 4. In Table 71, updated TPOR and FEMCCK. XC7K325T and XC7K410T in the -3 speed designation. production release of the XC7K420T in the -2, -2L(1.0V), and -1 speed designations. -1 speed grade (FF package) FGTXMAX value from 6.6 Gb/s to 8.0 Gb/s.

XC7K160T, XC7K355T, XC7K420T, and XC7K480T. Removed Note 4 from Table 70. XC7K160T, XC7K420T, and XC7K480T. Updated Note 1 in Table 53. XC7K70T and XC7K355T. Added Internal Configuration Access Port section to Table 71. with old Note 5 and then added new Note 5. Also in Table 1, updated IDCIN and IDCOUT sections. Table 5. Replaced XPower with Xilinx Power Estimator (XPE) in sentence before Table 7. Updated VIL Hold Time listing indicates no hold time or a negative hold time from Table 32, Table 33, and Table 48. and Note 4 in Table 70. Added TUSRCCLKO to Table 71. reference to 7 Series FPGAs Overview and Defense-Grade 7 Series FPGAs Overview in Introduction. type to Table 56. Added FDNACK to Table 71. and added Note 6 to Table 2. Added Note 2 to Table 4. Added Note 2 and updated Note 3 in Table 5. Accuracy at Extended Temperatures” section in Table 70. Table 21. Added Note 1 to Table 69. STARTUPE2 Ports and added FCFGMCLK and FCFGMCLKTOL. peak” to labels in Figure 3 and Figure 4.

brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. www.xilinx.com/legal.htm#tos. Table 2. Updated the AC Switching Characteristics based upon Vivado 2014.4. In Table 14, updated specification from Table 70. at -2LI (0.95V) speed grade.

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS182 (v2.16) May 8, 2017 www.xilinx.com Product Specification 70 AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTI VE SAFETY STANDARD (“SAFETY DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. Send Feedback