XC7A100T

XC7A100T-1FG484I AMD | Alldatasheet

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DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 1 © 2011– 2017 Xilinx, Inc. XILINX, the Xilinx logo, Artix, Virtex, Kintex, Zynq, Spartan, ISE, Vivado and other designated brand s included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Introduction Artix®-7 FPGAs are available in -3, -2, -1, -1LI, and -2L speed grades, with -3 having the highest performance. The Artix-7 FPGAs predominantly operate at a 1.0V core voltage. The -1LI and -2L devices are screened for lower maximum static power and can operate at lower core voltages for lower dynamic power than the -1 and -2 devices, respectively. The -1LI devices operate only at V CCINT =V CCBRAM = 0.95V and have the same speed specifications as the -1 speed grade. The -2L devices can operate at either of two V CCINT voltages, 0.9V and 1.0V and are screened for lower maximum static power. When operated at VCCINT = 1.0V, the speed specification of a -2L device is the same as the -2 speed grade. When operated at V CCINT = 0.9V, the -2L static and dynamic power is reduced. Artix-7 FPGA DC and AC characteristics are specified in commercial, extended, industrial, expanded (-1Q), and military (-1M) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1M speed grade military device are the same as for a -1C speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. For example, -1M is only available in the defense-grade Artix-7Q family and -1Q is only available in XA Artix-7 FPGAs. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Available device and package combinations can be found in:

• 7 Series FPGAs Overview (DS180)
• Defense-Grade 7 Series FPGAs Overview (DS185)
• XA Artix-7 FPGAs Overview (DS197) This Artix-7 FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/ documentation. DC Characteristics Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 Product Specification Table 1: Absolute Maximum Ratings(1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage –0.5 1.1 V VCCAUX Auxiliary supply voltage –0.5 2.0 V VCCBRAM Supply voltage for the block RAM memories –0.5 1.1 V VCCO Output drivers supply voltage for HR I/O banks –0.5 3.6 V VREF Input reference voltage –0.5 2.0 V VIN(2)(3)(4) I/O input voltage –0.4 V CCO +0 . 5 5 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(5) –0.4 2.625 V VCCBATT Key memory battery backup supply –0.5 2.0 V GTP Transceiver VMGTAVCC Analog supply voltage for the GTP transmitter and receiver circuits –0.5 1.1 V VMGTAVTT Analog supply voltage for the GTP transmitter and receiver termination circuits –0.5 1.32 V VMGTREFCLK Reference clock absolute input voltage –0.5 1.32 V VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 2 IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating – 14 mA IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT – 12 mA IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND – 6.5 mA IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating – 14 mA IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT – 12 mA XADC VCCADC XADC supply relative to GNDADC –0.5 2.0 V VREFP XADC reference input relative to GNDADC –0.5 2.0 V Temperature TSTG Storage temperature (ambient) –65 150 °C TSOL Maximum soldering temperature for Pb/Sn component bodies(6) –+ 2 2 0 ° C Maximum soldering temperature for Pb-free component bodies(6) –+ 2 6 0 ° C Tj Maximum junction temperature(6) –+ 1 2 5 ° C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. The lower absolute voltage specification always applies. 3. For I/O operation, refer to 7 Series FPGAs SelectIO Resources User Guide (UG471). 4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4. 5. See Table 9 for TMDS_33 specifications. 6. For soldering guidelines and thermal considerations, see 7 Series FPGA Packaging and Pinout Specification (UG475). Table 2: Recommended Operating Conditions(1)(2) Symbol Description Min Typ Max Units FPGA Logic VCCINT(3) For -3, -2, -2LE (1.0V), -1, -1Q, -1M devices: internal supply voltage 0.95 1.00 1.05 V For -1LI (0.95V) devices: internal supply voltage 0.92 0.95 0.98 V For -2LE (0.9V) devices: internal supply voltage 0.87 0.90 0.93 V VCCAUX Auxiliary supply voltage 1.71 1.80 1.89 V VCCBRAM(3) For -3, -2, -2LE (1.0V), -2LE (0.9V), -1, -1Q, -1M devices: block RAM supply voltage 0.95 1.00 1.05 V For -1LI (0.95V) devices: block RAM supply voltage 0.92 0.95 0.98 V VCCO(4)(5) Supply voltage for HR I/O banks 1.14 – 3.465 V VIN(6) I/O input voltage –0.20 – V CCO +0 . 2 0 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(7) –0.20 – 2.625 V IIN(8) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. –– 1 0m A VCCBATT(9) Battery voltage 1.0 – 1.89 V GTP Transceiver VMGTAVCC(10) Analog supply voltage for the GTP transmitter and receiver circuits 0.97 1.0 1.03 V VMGTAVTT(10) Analog supply voltage for the GTP transmitter and receiver termination circuits 1.17 1.2 1.23 V XADC VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 3 VREFP Externally supplied reference voltage 1.20 1.25 1.30 V Temperature Tj Junction temperature operating range for commercial (C) temperature devices 0 – 85 °C Junction temperature operating range for extended (E) temperature devices 0 – 100 °C Junction temperature operating range for industrial (I) temperature devices –40 – 100 °C Junction temperature operating range for expanded (Q) temperature devices –40 – 125 °C Junction temperature operating range for military (M) temperature devices –55 – 125 °C Notes: 1. All voltages are relative to ground. 2. For the design of the power distribution system consult 7 Series FPGAs PCB Design and Pin Planning Guide (UG483). 3. If V CCINT and VCCBRAM are operating at the same voltage, VCCINT and VCCBRAM should be connected to the same supply. 4. Configuration data is retained even if V CCO drops to 0V. 6. The lower absolute voltage specification always applies. 7. See Table 9 for TMDS_33 specifications. 8. A total of 200 mA per bank should not be exceeded. 9. V CCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. 10. Each voltage listed requires the filter circuit described in 7 Series FPGAs GTP Transceiver User Guide (UG482). Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ (1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 – – V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 – – V IREF VREF leakage current per pin – – 15 µA IL Input or output leakage current per pin (sample-tested) – – 15 µA CIN(2) Die input capacitance at the pad – – 8 pF IRPU Pad pull-up (when selected) @ VIN =0 V , VCCO =3 . 3 V 9 0 – 3 3 0 µ A Pad pull-up (when selected) @ VIN =0 V , VCCO =2 . 5 V 6 8 – 2 5 0 µ A Pad pull-up (when selected) @ VIN =0 V , VCCO =1 . 8 V 3 4 – 2 2 0 µ A Pad pull-up (when selected) @ VIN =0 V , VCCO =1 . 5 V 2 3 – 1 5 0 µ A Pad pull-up (when selected) @ VIN =0 V , VCCO =1 . 2 V 1 2 – 1 2 0 µ A IRPD Pad pull-down (when selected) @ VIN =3 . 3 V 6 8 – 3 3 0 µ A ICCADC Analog supply current, analog circuits in powered up state – – 25 mA IBATT(3) Battery supply current – – 150 nA RIN_TERM(4) Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40) 28 40 55 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50) 35 50 65 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60) 44 60 83 Ω Table 2: Recommended Operating Conditions(1)(2) (Cont’d) Symbol Description Min Typ Max Units Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 4 n Temperature diode ideality factor – 1.010 – – r Temperature diode series resistance – 2 – Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. This measurement represents the die capacitance at the pad, not including the package. 3. Maximum value specified for worst case process at 25°C. 4. Termination resistance to a V CCO/2 level. Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for HR I/O Banks(1)(2) AC Voltage Overshoot % of UI @–55°C to 125°C AC Voltage Undershoot % of UI @–55°C to 125°C VCCO + 0.55 100 –0.40 100 –0.45 61.7 –0.50 25.8 –0.55 11.0 V CCO + 0.60 46.6 –0.60 4.77 VCCO + 0.65 21.2 –0.65 2.10 VCCO + 0.70 9.75 –0.70 0.94 VCCO + 0.75 4.55 –0.75 0.43 VCCO + 0.80 2.15 –0.80 0.20 VCCO + 0.85 1.02 –0.85 0.09 VCCO + 0.90 0.49 –0.90 0.04 VCCO + 0.95 0.24 –0.95 0.02 Notes: 1. A total of 200 mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above V CCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d) Symbol Description Min Typ (1) Max Units Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 5 Table 5: Typical Quiescent Supply Current Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2 -2LE -1 -1LI -2LE ICCINTQ Quiescent VCCINT supply current XC7A12T 48 48 48 48 43 38 mA XC7A15T 95 95 95 95 58 66 mA XC7A25T 48 48 48 48 43 38 mA XC7A35T 95 95 95 95 58 66 mA XC7A50T 95 95 95 95 58 66 mA XC7A75T 155 155 155 155 96 108 mA XC7A100T 155 155 155 155 96 108 mA XC7A200T 328 328 328 328 203 232 mA XA7A15T N/A 95 N/A 95 N/A N/A mA XA7A35T N/A 95 N/A 95 N/A N/A mA XA7A50T N/A 95 N/A 95 N/A N/A mA XA7A75T N/A 155 N/A 155 N/A N/A mA XA7A100T N/A 155 N/A 155 N/A N/A mA XQ7A50T N/A 95 N/A 95 58 N/A mA XQ7A100T N/A 155 N/A 155 96 N/A mA XQ7A200T N/A 328 N/A 328 203 N/A mA I CCOQ Quiescent VCCO supply current XC7A12T 1 1 1 1 1 1 mA X C 7 A 1 5 T 111111 m A X C 7 A 2 5 T 111111 m A X C 7 A 3 5 T 111111 m A X C 7 A 5 0 T 111111 m A X C 7 A 7 5 T 444444 m A XC7A100T 4 4 4 4 4 4 mA XC7A200T 5 5 5 5 5 5 mA XA7A15T N/A 1 N/A 1 N/A N/A mA XA7A35T N/A 1 N/A 1 N/A N/A mA XA7A50T N/A 1 N/A 1 N/A N/A mA XA7A75T N/A 4 N/A 4 N/A N/A mA XA7A100T N/A 4 N/A 4 N/A N/A mA XQ7A50T N/A 1 N/A 1 1 N/A mA XQ7A100T N/A 4 N/A 4 4 N/A mA XQ7A200T N/A 5 N/A 5 5 N/A mA Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 6 ICCAUXQ Quiescent VCCAUX supply current XC7A12T 13 13 13 13 13 13 mA XC7A15T 22 22 22 22 19 22 mA XC7A25T 13 13 13 13 13 13 mA XC7A35T 22 22 22 22 19 22 mA XC7A50T 22 22 22 22 19 22 mA XC7A75T 36 36 36 36 32 36 mA XC7A100T 36 36 36 36 32 36 mA XC7A200T 73 73 73 73 65 73 mA XA7A15T N/A 22 N/A 22 N/A N/A mA XA7A35T N/A 22 N/A 22 N/A N/A mA XA7A50T N/A 22 N/A 22 N/A N/A mA XA7A75T N/A 36 N/A 36 N/A N/A mA XA7A100T N/A 36 N/A 36 N/A N/A mA XQ7A50T N/A 22 N/A 22 19 N/A mA XQ7A100T N/A 36 N/A 36 32 N/A mA XQ7A200T N/A 73 N/A 73 65 N/A mA I CCBRAMQ Quiescent VCCBRAM supply current XC7A12T 1 1 1 1 1 1 mA X C 7 A 1 5 T 222212 m A X C 7 A 2 5 T 111111 m A X C 7 A 3 5 T 222212 m A X C 7 A 5 0 T 222212 m A X C 7 A 7 5 T 444424 m A XC7A100T 4 4 4 4 2 4 mA XC7A200T 11 11 11 11 6 11 mA XA7A15T N/A 2 N/A 2 N/A N/A mA XA7A35T N/A 2 N/A 2 N/A N/A mA XA7A50T N/A 2 N/A 2 N/A N/A mA XA7A75T N/A 4 N/A 4 N/A N/A mA XA7A100T N/A 4 N/A 4 N/A N/A mA XQ7A50T N/A 2 N/A 2 1 N/A mA XQ7A100T N/A 4 N/A 4 2 N/A mA XQ7A200T N/A 11 N/A 11 6 N/A mA Notes: 1. Typical values are specified at nominal voltage, 85°C junction temperature (T j) with single-ended SelectIO resources. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to estimate static power consumption for conditions other than those specified. Table 5: Typical Quiescent Supply Current (Cont’d) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2 -2LE -1 -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 7 Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX and VCCO have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0:

• The voltage difference between V CCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels.
• T h e T VCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps. The recommended power-on sequence to achieve minimum current draw for the GTP transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power- up and power-down.
• W h e n V MGTAVTT is powered before VMGTAVCC and VMGTAVTT –V MGTAVCC > 150 mV and VMGTAVCC <0 . 7 V , t h e VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down.
• W h e n V MGTAVTT is powered before VCCINT and VMGTAVTT –V CCINT > 150 mV and VCCINT <0 . 7 V , t h e VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down. There is no recommended sequence for supplies not shown. Table 6 shows the minimum current, in addition to I CCQ, that is required by Artix-7 devices for proper power-on and configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies. Table 6: Power-On Current for Artix-7 Devices Device I CCINTMIN ICCAUXMIN ICCOMIN ICCBRAMMIN Units XC7A12T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XC7A15T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XC7A25T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XC7A35T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XC7A50T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XC7A75T I CCINTQ +1 7 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XC7A100T I CCINTQ +1 7 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XC7A200T I CCINTQ +3 4 0 I CCAUXQ +5 0 I CCOQ + 40 mA per bank I CCBRAMQ +8 0 m A XA7A15T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XA7A35T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XA7A50T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XA7A75T I CCINTQ +1 7 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XA7A100T I CCINTQ +1 7 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XQ7A50T I CCINTQ +1 2 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XQ7A100T I CCINTQ +1 7 0 I CCAUXQ +4 0 I CCOQ + 40 mA per bank I CCBRAMQ +6 0 m A XQ7A200T I CCINTQ +3 4 0 I CCAUXQ +5 0 I CCOQ + 40 mA per bank I CCBRAMQ +8 0 m A Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 8 DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 7: Power Supply Ramp Time Symbol Description Conditions Min Max Units TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms TVCCBRAM Ramp time from GND to 90% of VCCBRAM 0.2 50 ms TVCCO2VCCAUX Allowed time per power cycle for VCCO – VCCAUX > 2.625V TJ = 125°C(1) –3 0 0 msTJ = 100°C(1) –5 0 0 TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms Notes: 1. Based on 240,000 power cycles with nominal V CCO of 3.3V or 36,500 power cycles with worst case VCCO of 3.465V. Table 8: SelectIO DC Input and Output Levels(1)(2) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min LVCMOS12 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.400 V CCO –0 . 4 0 0 Note 3 Note 3 LVCMOS15 –0.300 35% V CCO 65% VCCO VCCO + 0.300 25% V CCO 75% VCCO Note 4 Note 4 LVCMOS18 –0.300 35% V CCO 65% VCCO VCCO + 0.300 0.450 V CCO –0 . 4 5 0 Note 5 Note 5 MOBILE_DDR –0.300 20% V CCO 80% VCCO VCCO + 0.300 10% V CCO 90% VCCO 0.10 –0.10 PCI33_3 –0.400 30% V CCO 50% VCCO VCCO + 0.500 10% V CCO 90% VCCO 1.50 –0.50 Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 9 Notes: 1. Tested according to relevant specifications. 2. 3.3V and 2.5V standards are only supported in HR I/O banks. 3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks. 4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks. 5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks. 6. For detailed interface specific DC voltage levels, see 7 Series FPGAs SelectIO Resources User Guide (UG471 Table 9: Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) VID(2) VOCM(3) VOD(4) V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max V, Min V, Typ V, Max Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage (Q – Q). 3. V OCM is the output common mode voltage. 4. V OD is the output differential voltage (Q – Q). 5. V OD for BLVDS will vary significantly depending on topology and loading. Table 10: Complementary Differential SelectIO DC Input and Output Levels I/O Standard VICM(1) VID(2) VOL(3) VOH(4) IOL IOH V, Min V,Typ V, Max V,Min V, Max V, Max V, Min mA, Max mA, Min Notes: 1. V ICM is the input common mode voltage. 2. V ID is the input differential voltage (Q – Q). 3. V OL is the single-ended low-output voltage. 4. V OH is the single-ended high-output voltage. Table 8: SelectIO DC Input and Output Levels(1)(2) (Cont’d) I/O Standard VIL VIH VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA, Max mA, Min Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 10 LVDS DC Specifications (LVDS_25) Table 11: LVDS_25 DC Specifications(1) Symbol DC Parameter Conditions Min Typ Max Units VCCO Supply Voltage 2.375 2.500 2.625 V VOH Output High Voltage for Q and Q RT = 100 Ω across Q and Q signals – – 1.675 V VOL Output Low Voltage for Q and Q RT = 100 Ω across Q and Q signals 0.700 – – V VODIFF Differential Output Voltage: (Q – Q), Q = High (Q –Q ) , Q=H i g h RT = 100 Ω across Q and Q signals 247 350 600 mV VOCM Output Common-Mode Voltage R T = 100 Ω across Q and Q signals 1.000 1.250 1.425 V VIDIFF Differential Input Voltage: (Q – Q), Q = High (Q –Q ) , Q=H i g h 100 350 600 mV VICM Input Common-Mode Voltage 0.300 1.200 1.500 V Notes: 1. Differential inputs for LVDS_25 can be placed in banks with V CCO levels that are different from the required level for outputs. Consult the 7 Series FPGAs SelectIO Resources User Guide (UG471) for more information. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 11 AC Switching Characteristics All values represented in this data sheet are based on the speed specifications from the ISE® Design Suite 14.7 and Vivado® Design Suite 2016.3 as outlined in Table 12. Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance Product Specification These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur. Preliminary Product Specification These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production Product Specification These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. Testing of AC Switching Characteristics Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Artix-7 FPGAs. Table 12: Artix-7 FPGA Speed Specification Version By Device Version In: Typical V CCINT Device ISE 14.7 Vivado 2016.4 ( Table 2) N/A 1.16 1.0V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T N/A 1.16 0.95V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T, XC7A100T, XC7A200T N/A 1.11 0.9V XC7A12T, XC7A15T, XC7A25T, XC7A35T, XC7A50T, XC7A75T 1.10 1.16 1.0V XC7A100T, XC7A200T 1.07 1.11 0.9V XC7A100T, XC7A200T N/A 1.11 1.0V XA7A15T, XA7A35T, XA7A50T, XA7A75T 1.07 1.11 1.0V XA7A100T 1.06 1.11 1.0V XQ7A100T, XQ7A200T N/A 1.11 1.0V XQ7A50T Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 12 Speed Grade Designations Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Artix-7 device on a per speed grade basis. Production Silicon and Software Status In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 14 lists the production released Artix-7 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 13: Artix-7 Device Speed Grade Designations Device Speed Grade Designations Advance Prelimin ary Production XC7A12T -3, -2, -1, -1LI (0.95V), and -2LE (0.9V) XC7A15T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V) XC7A25T -3, -2, -1, -1LI (0.95V), and -2LE (0.9V) XC7A35T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V) XC7A50T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V) XC7A75T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V) XC7A100T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V) XC7A200T -3, -2, -2LE (1.0V), -1, -1LI (0.95V), and -2LE (0.9V) XA7A15T -2I, -1I, and -1Q XA7A35T -2I, -1I, and -1Q XA7A50T -2I, -1I, and -1Q XA7A75T -2I, -1I, and -1Q XA7A100T -2I, -1I, and -1Q XQ7A50T -2I, -1I, -1LI (0.95V), and -1M XQ7A100T -2I, -1I, -1LI (0.95V), and -1M XQ7A200T -2I, -1I, -1LI (0.95V), and -1MTable 14: Artix-7 Device Production Software and Speed Specification Release Device Speed Grade 1.0V 0.95V 0.9V -3 -2 -2LE -1 -1Q -1M -1LI -2LE XC7A12T N/A N/A XC7A15T Vivado tools 2014.4 v1.14 N/A N/A Vivado tools 2014.4 v1.14 Vivado tools 2014.4 v1.10 XC7A25T N/A N/A XC7A35T Vivado tools 2013.4 v1.11 N/A N/A Vivado tools 2014.4 v1.14 Vivado tools 2013.4 v1.08 XC7A50T Vivado tools 2013.4 v1.11 N/A N/A Vivado tools 2014.4 v1.14 Vivado tools 2013.4 v1.08 XC7A75T Vivado tools 2013.3 v1.10 N/A N/A Vivado tools 2014.4 v1.14 Vivado tools 2013.3 v1.07 Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 13 Selecting the Correct Speed Grade and Voltage in the Vivado Tools It is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting. To select the 1.0V speed specifications in the Vivado tools, select the Artix-7, XA Artix-7, or Defense Grade Artix-7Q sub-family, and then select the part name that is the device name followed by the package name followed by the speed grade. For example, select the xc7a100tfgg676-3 part name for the XC7A100T device in the FGG676 package and -3 (1.0V) speed grade or select the xc7a100tfgg676-2L part name for the XC7A100T device in the FGG676 package and -2LE (1.0V) speed grade. To select the -1LI (0.95V) speed specifications in the Vivado tools, select the Artix-7 sub-family and then select the part name that is the device name followed by an “i” followed by the package name followed by the speed grade. For example, select the xc7a100tifgg676-1L part name for the XC7A100T device in the FGG676 package and -1LI (0.95V) speed grade. The -1LI (0.95V) speed specifications are not supported in the ISE tools. To select the -2LE (0.9V) speed specifications in the Vivado tools, select the Artix-7 Low Voltage sub-family and then select the part name that is the device name followed by an “l” followed by the package name followed by the speed grade. For example, select the xc7a100tlfgg676-2L part name for the XC7A100T device in the FGG676 package and -2LE (0.9V) speed grade. A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See Table 14 for the subset of 7 series FPGAs supported in the ISE tools. XC7A100T ISE tools 14.4 or Vivado tools 2012.4 with the 14.4/2012.4 device pack v1.07 N/A N/A Vivado tools 2014.4 v1.14 ISE tools 14.5 or Vivado tools 2013.1 v1.05XC7A200T ISE tools 14.4 or Vivado tools 2012.4 with the 14.4/2012.4 device pack v1.07 N/A N/A Vivado tools 2014.4 v1.14 XA7A15T N/A Vivado tools 2014.4 v1.14 N/A Vivado tools 2014.4 v1.14 N/A N/A N/A XA7A35T N/A Vivado tools 2014.1 v1.09 N/A Vivado tools 2014.1 v1.09 N/A N/A N/A XA7A50T N/A Vivado tools 2014.1 v1.09 N/A Vivado tools 2014.1 v1.09 N/A N/A N/A XA7A75T N/A Vivado tools 2014.1 v1.09 N/A Vivado tools 2014.1 v1.09 N/A N/A N/A XA7A100T N/A ISE tools 14.5 or Vivado tools 2013.1 v1.05 N/A ISE tools 14.5 or Vivado tools 2013.1 v1.05 ISE tools 14.6 or Vivado tools 2013.2 v1.06 N/A N/A N/A XQ7A50T N/A Vivado tools 2014.2 v1.08 N/A Vivado tools 2014.2 v1.08 N/A Vivado tools 2014.2 v1.08 Vivado tools 2015.4 v1.11 N/A XQ7A100T N/A ISE tools 14.5 or Vivado tools 2013.1 v1.04 N/A ISE tools 14.5 or Vivado tools 2013.1 v1.04 N/A ISE tools 14.6 or Vivado tools 2013.2 v1.05 Vivado tools 2015.4 v1.11 N/A XQ7A200T N/A ISE tools 14.5 or Vivado tools 2013.1 v1.04 N/A ISE tools 14.5 or Vivado tools 2013.1 v1.04 N/A ISE tools 14.6 or Vivado tools 2013.2 v1.05 Vivado tools 2015.4 v1.11 N/A Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status. Table 14: Artix-7 Device Production Software and Speed Specification Release (Cont’d) Device Speed Grade 1.0V 0.95V 0.9V -3 -2 -2LE -1 -1Q -1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 14 Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Artix-7 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 11. Table 15: Networking Applications Interface Performances

Description

Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8) 680 680 600 600 600 Mb/s DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) 1250 1250 950 950 950 Mb/s SDR LVDS receiver (SFI-4.1)(1) 680 680 600 600 600 Mb/s DDR LVDS receiver (SPI-4.2)(1) 1250 1250 950 950 950 Mb/s Notes: 1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance. Table 16: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface Generator(1)(2) Memory Standard Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE 4:1 Memory Controllers DDR3 1066 800 800 667 800 800 Mb/s DDR3L 800 800 667 N/A 667 667 Mb/s DDR2 800 800 667 533 667 667 Mb/s 2:1 Memory Controllers DDR3 800 700 620 620 620 620 Mb/s DDR3L 800 700 620 N/A 620 620 Mb/s DDR2 800 700 620 533 620 620 Mb/s LPDDR2 667 667 533 400 533 533 Mb/s Notes: 1. V REF tracking is required. For more information, see 7 Series FPGAs Memory Interface Solutions User Guide (UG586). 2. When using the internal V REF, the maximum data rate is 800 Mb/s (400 MHz). Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 15 IOB Pad Input/Output/3-State Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.

• T IOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer.
• T IOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer.
• T IOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM termination turn-on time is always faster than TIOTP when the INTERMDISABLE pin is used. Table 17: IOB High Range (HR) Switching Characteristics I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE RSDS_25 (point DIFF_HSUL_ DIFF_HSUL_ MOBILE_ MOBILE_ DIFF_MOBILE_ DIFF_MOBILE_ Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 16 DIFF_HSTL_ DIFF_HSTL_ DIFF_HSTL_ DIFF_HSTL_ DIFF_HSTL_ DIFF_HSTL_ Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 17 DIFF_SSTL135_ DIFF_SSTL15_ DIFF_SSTL18 DIFF_SSTL18 Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 18 Table 18 specifies the values of TIOTPHZ and TIOIBUFDISABLE. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). TIOIBUFDISABLE is described as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always faster than TIOTPHZ when the INTERMDISABLE pin is used. I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 19 shows the test setup parameters used for measuring input delay. DIFF_SSTL135 DIFF_SSTL18_I DIFF_SSTL18_II Table 18: IOB 3-state Output Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE TIOIBUFDISABLE IBUF turn-on time from IBUFDISABLE to O output Table 19: Input Delay Measurement Methodology Description I/O Standard Attribute V L(1) VH(1) VMEAS (3)(5) VREF (2)(4) LVCMOS, 1.2V LVCMOS12 0.1 1.1 0.6 – LVCMOS, 1.5V LVCMOS15 0.1 1.4 0.75 – LVCMOS, 1.8V LVCMOS18 0.1 1.7 0.9 – LVCMOS, 2.5V LVCMOS25 0.1 2.4 1.25 – LVCMOS, 3.3V LVCMOS33 0.1 3.2 1.65 – LVTTL, 3.3V LVTTL 0.1 3.2 1.65 – MOBILE_DDR, 1.8V MOBILE_DDR 0.1 1.7 0.9 – PCI33, 3.3V PCI33_3 0.1 3.2 1.65 – HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 Table 17: IOB High Range (HR) Switching Characteristics (Cont’d) I/O Standard TIOPI TIOOP TIOTP Units Speed Grade Speed Grade Speed Grade -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE -3 -2/ -2LE -1 -1Q/ -1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 19 HSTL, Class I & II, 1.5V HSTL_I, HSTL_II V REF –0 . 6 5 V REF +0 . 6 5 V REF 0.75 HSTL, Class I & II, 1.8V HSTL_I_18, HSTL_II_18 V REF –0 . 8 V REF +0 . 8 V REF 0.90 HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 SSTL (Stub Terminated Transceiver Logic), 1.2V SSTL12 V REF –0 . 5 V REF +0 . 5 V REF 0.60 SSTL, 1.35V SSTL135, SSTL135_R V REF – 0.575 V REF + 0.575 V REF 0.675 SSTL, 1.5V SSTL15, SSTL15_R V REF –0 . 6 5 V REF +0 . 6 5 V REF 0.75 SSTL, Class I & II, 1.8V SSTL18_I, SSTL18_II V REF –0 . 8 V REF +0 . 8 V REF 0.90 DIFF_HSTL, Class I & II,1.5V DIFF_HSTL_I, DIFF_HSTL_II DIFF_HSTL, Class I & II, 1.8V DIFF_HSTL_I_18, DIFF_HSTL_II_18 DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL15, DIFF_SSTL15_R DIFF_SSTL18_I/DIFF_SSTL18_II, 1.8V DIFF_SSTL18_I, DIFF_SSTL18_II PPDS_25 PPDS_25 1.25 – 0.125 1.25 + 0.125 0 (5) – RSDS_25 RSDS_25 1.25 – 0.125 1.25 + 0.125 0 (5) – TMDS_33 TMDS_33 3 – 0.125 3 + 0.125 0 (5) – Notes: 1. Input waveform switches between V Land VH. 2. Measurements are made at typical, minimum, and maximum V REF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 3. Input voltage level from which measurement starts. 4. This is an input voltage reference that bears no relation to the V REF / VMEAS parameters found in IBIS models and/or noted in Figure 1. 5. The value given is the differential input voltage. Table 19: Input Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute V L(1) VH(1) VMEAS (3)(5) VREF (2)(4) Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 21 HSTL (High-Speed Transceiver Logic), Class I, 1.2V HSTL_I_12 50 0 V REF 0.6 HSTL, Class I, 1.5V HSTL_I 50 0 V REF 0.75 HSTL, Class II, 1.5V HSTL_II 25 0 V REF 0.75 HSTL, Class I, 1.8V HSTL_I_18 50 0 V REF 0.9 HSTL, Class II, 1.8V HSTL_II_18 25 0 V REF 0.9 HSUL (High-Speed Unterminated Logic), 1.2V HSUL_12 50 0 V REF 0.6 SSTL12, 1.2V SSTL12 50 0 V REF 0.6 SSTL135/SSTL135_R, 1.35V SSTL135, SSTL135_R 50 0 V REF 0.675 SSTL15/SSTL15_R, 1.5V SSTL15, SSTL15_R 50 0 V REF 0.75 SSTL (Stub Series Terminated Logic), Class I & Class II, 1.8V SSTL18_I, SSTL18_II 50 0 V REF 0.9 DIFF_MOBILE_DDR, 1.8V DIFF_MOBILE_DDR 50 0 V REF 0.9 DIFF_HSTL, Class I, 1.2V DIFF_HSTL_I_12 50 0 V REF 0.6 DIFF_HSTL, Class I & II, 1.5V DIFF_HSTL_I, DIFF_HSTL_II 50 0 V REF 0.75 DIFF_HSTL, Class I & II, 1.8V DIFF _HSTL_I_18, DIFF_HSTL_II_18 50 0 V REF 0.9 DIFF_HSUL_12, 1.2V DIFF_HSUL_12 50 0 V REF 0.6 DIFF_SSTL135/DIFF_SSTL135_R, 1.35V DIFF_SSTL135, DIFF_SSTL135_R 50 0 V REF 0.675 DIFF_SSTL15/DIFF_SSTL15_R, 1.5V DIFF_SSTL1 5, DIFF_SSTL15_R 50 0 V REF 0.75 DIFF_SSTL18, Class I & II, 1.8V DI FF_SSTL18_I, DIFF_SSTL18_II 50 0 V REF 0.9 LVDS, 2.5V LVDS_25 100 0 0 (2) 0 BLVDS (Bus LVDS), 2.5V BLVDS_25 100 0 0 (2) 0 Mini LVDS, 2.5V MINI_LVDS_25 100 0 0 (2) 0 PPDS_25 PPDS_25 100 0 0 (2) 0 RSDS_25 RSDS_25 100 0 0 (2) 0 TMDS_33 TMDS_33 50 0 0 (2) 3.3 Notes: 1. C REF is the capacitance of the probe, nominally 0 pF. 2. The value given is the differential output voltage. Table 20: Output Delay Measurement Methodology (Cont’d) Description I/O Standard Attribute RREF (Ω) CREF(1) (pF) VMEAS (V) VREF (V) Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 22 Input/Output Logic Switching Characteristics Table 21: ILOGIC Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Setup/Hold TICE1CK/ TICKCE1 CE1 pin setup/hold with respect to CLK T ISRCK/ TICKSR SR pin setup/hold with respect to CLK T IDOCK/ TIOCKD D pin setup/hold with respect to CLK without Delay T IDOCKD/ TIOCKDD DDLY pin setup/hold with respect to CLK (using IDELAY) Combinatorial T IDI D pin to O pin propagation delay, no Delay TIDID DDLY pin to O pin propagation delay (using IDELAY) Sequential Delays TIDLO D pin to Q1 pin using flip-flop as a latch without Delay TIDLOD DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY) TRQ_ ILOGIC TGSRQ_ ILOGIC Set/Reset TRPW_ ILOGIC Table 22: OLOGIC Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Setup/Hold TODCK/ TOCKD D1/D2 pins setup/hold with respect to CLK T OOCECK/ TOCKOCE OCE pin setup/hold with respect to CLK T OSRCK/ TOCKSR SR pin setup/hold with respect to CLK T OTCK/ TOCKT T1/T2 pins setup/hold with respect to CLK T OTCECK/ TOCKTCE TCE pin setup/hold with respect to CLK Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 23 Input Serializer/Deserializer Switching Characteristics Combinatorial Sequential Delays T Set/Reset T Min Table 23: ISERDES Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin setup/hold with respect to CLKDIV T ISCCK_CE / TISCKC_CE(2) CE pin setup/hold with respect to CLK (for CE1) TISCCK_CE2 / TISCKC_CE2(2) CE pin setup/hold with respect to CLKDIV (for CE2) Setup/Hold for Data Lines TISDCK_D / TISCKD_D D pin setup/hold with respect to CLK T ISDCK_DDLY / TISCKD_DDLY DDLY pin setup/hold with respect to CLK (using IDELAY) (1) TISDCK_D_DDR / TISCKD_D_DDR D pin setup/hold with respect to CLK at DDR mode T ISDCK_DDLY_DDR/ TISCKD_DDLY_DDR D pin setup/hold with respect to CLK at DDR mode (using IDELAY) (1) Sequential Delays Propagation Delays Notes: 1. Recorded at 0 tap value. 2. T ISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE/TISCKC_CE in the timing report. Table 22: OLOGIC Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 24 Output Serializer/Deserializer Switching Characteristics Table 24: OSERDES Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Setup/Hold TOSDCK_D/ TOSCKD_D D input setup/hold with respect to CLKDIV T OSDCK_T/ TOSCKD_T(1) T input setup/hold with respect to CLK TOSDCK_T2/ TOSCKD_T2(1) T input setup/hold with respect to CLKDIV TOSCCK_OCE/ TOSCKC_OCE OCE input setup/hold with respect to CLK T OSCCK_S SR (reset) input setup with respect to CLKDIV TOSCCK_TCE/ TOSCKC_TCE TCE input setup/hold with respect to CLK Sequential Delays T Combinatorial T Notes: 1. T OSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the timing report. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 25 Input/Output Delay Switching Characteristics Table 25: Input/Output Delay Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE IDELAYCTRL FIDELAYCTRL_REF Attribute REFCLK frequency = 200.00(1) Attribute REFCLK frequency = 300.00(1) Attribute REFCLK frequency = 400.00(1) 400.00 400.00 N/A N/A N/A N/A MHz IDELAYCTRL_REF_ PRECISION REFCLK precision ±10 ±10 ±10 ±10 ±10 ±10 MHz IDELAY TIDELAYRESOLUTION IDELAY chain delay resolution 1/(32 x 2 x F REF)µ s TIDELAYPAT_JIT Pattern dependent period jitter in delay chain for clock pattern.(2) 000000 p s per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(3) per tap Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)(4) per tap TIDELAY_CLK_MAX Maximum frequency of CLK input to IDELAY TIDCCK_CE / TIDCKC_CE CE pin setup/hold with respect to C for IDELAY T IDCCK_INC/ TIDCKC_INC INC pin setup/hold with respect to C for IDELAY T IDCCK_RST/ TIDCKC_RST RST pin setup/hold with respect to C for IDELAY T IDDO_IDATAIN Propagation delay through IDELAY Note 5 Note 5 Note 5 Note 5 Note 5 Note 5 ps Notes: 1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps. 2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE. 3. When HIGH_PERFORMANCE mode is set to TRUE. 4. When HIGH_PERFORMANCE mode is set to FALSE. 5. Delay depends on IDELAY tap setting. See the timing report for actual values. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 26 Table 26: IO_FIFO Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE IO_FIFO Clock to Out Delays Setup/Hold TIFFCCK_WREN/ TIFFCKC_WREN TOFFCCK_RDEN/ TOFFCKC_RDEN Minimum Pulse Width Maximum Frequency Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 27 CLB Switching Characteristics Table 27: CLB Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Combinatorial Delays TILO_2 An – Dn LUT address to AMUX/CMUX Sequential Delays Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TAS/TAH AN – DN input to CLK on A – D flip-flops TDICK/ TCKDI AX –D X input to CLK on A – D flip-flops AX –D X input through MUXs and/or carry logic to CLK on A – D flip-flops TCECK_CLB/ TCKCE_CLB TSRCK/ TCKSR Set/Reset TRQ Delay from SR input to AQ – DQ flip-flops TCEO Delay from CE input to AQ – DQ flip-flops FTOG Toggle frequency (for export control) 1412 1286 1098 1098 1098 1098 MHz Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 28 CLB Distributed RAM Switching Characteristics (SLICEM Only) CLB Shift Register Switching Characteristics (SLICEM Only) Table 28: CLB Distributed RAM Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Sequential Delays Setup and Hold Times Before/After Clock CLK TDS_LRAM/ TDH_LRAM TAS_LRAM/ TAH_LRAM Address An inputs through MUXs and/or carry logic to clock TWS_LRAM/ TWH_LRAM TCECK_LRAM/ TCKCE_LRAM Clock CLK Notes: 1. T SHCKO also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path. Table 29: CLB Shift Register Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Sequential Delays TREG_M31 Clock to DMUX output via M31 output Setup and Hold Times Before/After Clock CLK TWS_SHFREG/ TWH_SHFREG TCECK_SHFREG/ TCKCE_SHFREG TDS_SHFREG/ TDH_SHFREG Clock CLK Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 29 Block RAM and FIFO Switching Characteristics Table 30: Block RAM and FIFO Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Block RAM and FIFO Clock-to-Out Delays TRCKO_DO and TRCKO_DO_REG(1) Clock CLK to DOUT output (without output register)(2)(3) Clock CLK to DOUT output (with output register)(4)(5) TRCKO_DO_ECC and TRCKO_DO_ECC_REG Clock CLK to DOUT output with ECC (without output register)(2)(3) Clock CLK to DOUT output with ECC (with output register)(4)(5) TRCKO_DO_CASCOUT and TRCKO_DO_CASCOUT_REG Clock CLK to DOUT output with cascade (without output register)(2) Clock CLK to DOUT output with cascade (with output register)(4) TRCKO_FLAGS Clock CLK to FIFO flags outputs(6) TRCKO_POINTERS Clock CLK to FIFO pointers outputs(7) TRCKO_PARITY_ECC Clock CLK to ECCPARITY in ECC encode only mode TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG Clock CLK to BITERR (without output register) Clock CLK to BITERR (with output register) TRCKO_RDADDR_ECC and TRCKO_RDADDR_ECC_REG Clock CLK to RDADDR output with ECC (without output register) Clock CLK to RDADDR output with ECC (with output register) Setup and Hold Times Before/After Clock CLK T RCCK_ADDRA/ TRCKC_ADDRA TRDCK_DI_WF_NC/ TRCKD_DI_WF_NC Data input setup/hold time when block RAM is configured in WRITE_FIRST or NO_CHANGE mode (9) TRDCK_DI_RF/ TRCKD_DI_RF Data input setup/hold time when block RAM is configured in READ_FIRST mode (9) Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 30 TRDCK_DI_ECC/ TRCKD_DI_ECC DIN inputs with block RAM ECC in standard mode (9) TRDCK_DI_ECCW/ TRCKD_DI_ECCW DIN inputs with block RAM ECC encode only (9) TRDCK_DI_ECC_FIFO/ TRCKD_DI_ECC_FIFO DIN inputs with FIFO ECC in standard mode (9) TRCCK_INJECTBITERR/ TRCKC_INJECTBITERR Inject single/double bit error in ECC mode T RCCK_EN/TRCKC_EN Block RAM enable (EN) input TRCCK_REGCE/ TRCKC_REGCE TRCCK_RSTREG/ TRCKC_RSTREG Synchronous RSTREG input T RCCK_RSTRAM/ TRCKC_RSTRAM Synchronous RSTRAM input T RCCK_WEA/ TRCKC_WEA Write enable (WE) input (block RAM only) T RCCK_WREN/ TRCKC_WREN TRCCK_RDEN/ TRCKC_RDEN Reset Delays TRCO_FLAGS Reset RST to FIFO flags/pointers(10) TRREC_RST/ TRREM_RST FIFO reset recovery and removal timing (11) Maximum Frequency FMAX_BRAM_WF_NC Block RAM (write first and no change modes) when not in SDP RF mode FMAX_BRAM_RF_ PERFORMANCE Block RAM (read first, performance mode) when in SDP RF mode but no address overlap between port A and port B F MAX_BRAM_RF_ DELAYED_WRITE Block RAM (read first, delayed write mode) when in SDP RF mode and there is possibility of overlap between port A and port B addresses Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 31 FMAX_CAS_WF_NC Block RAM cascade (write first, no change mode) when cascade but not in RF mode F MAX_CAS_RF_ PERFORMANCE Block RAM cascade (read first, performance mode) when in cascade with RF mode and no possibility of address overlap/one port is disabled F MAX_CAS_RF_ DELAYED_WRITE When in cascade RF mode and there is a possibility of address overlap between port A and port B F MAX_FIFO FIFO in all modes without ECC FMAX_ECC Block RAM and FIFO in ECC configuration Notes: 1. The timing report shows all of these parameters as T RCKO_DO. 2. T RCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters. 3. These parameters also apply to synchronous FIFO with DO_REG = 0. 4. T RCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters. 5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1. 6. T RCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR. 7. T RCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT. 8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 9. These parameters include both A and B inputs as well as the parity inputs of A and B. 10. T RCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT. 11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock e dges of the slowest clock (WRCLK or RDCLK). Table 30: Block RAM and FIFO Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 32 DSP48E1 Switching Characteristics Table 31: DSP48E1 Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_AREG/ TDSPCKD_A_AREG A input to A register CLK 0.26/ 0.12 0.30/ 0.13 0.37/ 0.14 0.37/ 0.28 0.37/ 0.14 0.45/ 0.14 ns TDSPDCK_B_BREG/ TDSPCKD_B_BREG B input to B register CLK 0.33/ 0.15 0.38/ 0.16 0.45/ 0.18 0.45/ 0.25 0.45/ 0.18 0.60/ 0.19 ns TDSPDCK_C_CREG/ TDSPCKD_C_CREG C input to C register CLK 0.17/ 0.17 0.20/ 0.19 0.24/ 0.21 0.24/ 0.26 0.24/ 0.21 0.34/ 0.29 ns TDSPDCK_D_DREG/ TDSPCKD_D_DREG D input to D register CLK 0.25/ 0.25 0.32/ 0.27 0.42/ 0.27 0.42/ 0.42 0.42/ 0.27 0.54/ 0.23 ns TDSPDCK_ACIN_AREG/ TDSPCKD_ACIN_AREG ACIN input to A register CLK 0.23/ 0.12 0.27/ 0.13 0.32/ 0.14 0.32/ 0.17 0.32/ 0.14 0.36/ 0.14 ns TDSPDCK_BCIN_BREG/ TDSPCKD_BCIN_BREG BCIN input to B register CLK 0.25/ 0.15 0.29/ 0.16 0.36/ 0.18 0.36/ 0.18 0.36/ 0.18 0.41/ 0.19 ns Setup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{A, B}_MREG_MULT/ {A, B} input to M register CLK using multiplier 2.40/ –0.01 2.76/ –0.01 3.29/ –0.01 3.29/ –0.01 3.29/ –0.01 4.31/ –0.07 ns T DSPDCK_{A, D}_ADREG/ TDSPCKD_{A, D}_ADREG {A, D} input to AD register CLK 1.29/ –0.02 1.48/ –0.02 1.76/ –0.02 1.76/ –0.02 1.76/ –0.02 2.29/ –0.27 ns Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{A, B}_PREG_MULT/ TDSPCKD_{A, B} _PREG_MULT {A, B} input to P register CLK using multiplier 4.02/ –0.28 4.60/ –0.28 5.48/ –0.28 5.48/ –0.28 5.48/ –0.28 6.95/ –0.48 ns TDSPDCK_D_PREG_MULT/ TDSPCKD_D_PREG_MULT D input to P register CLK using multiplier 3.93/ –0.73 4.50/ –0.73 5.35/ –0.73 5.35/ –0.73 5.35/ –0.73 6.73/ –1.68 ns TDSPDCK_{A, B} _PREG/ TDSPCKD_{A, B} _PREG A or B input to P register CLK not using multiplier 1.73/ –0.28 1.98/ –0.28 2.35/ –0.28 2.35/ –0.28 2.35/ –0.28 2.80/ –0.48 ns TDSPDCK_C_PREG/ TDSPCKD_C_PREG C input to P register CLK not using multiplier 1.54/ –0.26 1.76/ –0.26 2.10/ –0.26 2.10/ –0.26 2.10/ –0.26 2.54/ –0.45 ns TDSPDCK_PCIN_PREG/ TDSPCKD_PCIN_PREG PCIN input to P register CLK 1.32/ –0.15 1.51/ –0.15 1.80/ –0.15 1.80/ –0.15 1.80/ –0.15 2.13/ –0.25 ns Setup and Hold Times of the CE Pins TDSPDCK_{CEA;CEB}_{AREG;BREG}/ {CEA; CEB} input to {A; B} register CLK 0.35/ 0.06 0.42/ 0.08 0.52/ 0.11 0.52/ 0.11 0.52/ 0.11 0.64/ 0.11 ns TDSPDCK_CEC_CREG/ TDSPCKD_CEC_CREG CEC input to C register CLK 0.28/ 0.10 0.34/ 0.11 0.42/ 0.13 0.42/ 0.13 0.42/ 0.13 0.49/ 0.16 ns TDSPDCK_CED_DREG/ TDSPCKD_CED_DREG CED input to D register CLK 0.36/ –0.03 0.43/ –0.03 0.52/ –0.03 0.52/ –0.03 0.52/ –0.03 0.68/ 0.14 ns TDSPDCK_CEM_MREG/ TDSPCKD_CEM_MREG CEM input to M register CLK 0.17/ 0.18 0.21/ 0.20 0.27/ 0.23 0.27/ 0.23 0.27/ 0.23 0.45/ 0.29 ns TDSPDCK_CEP_PREG/ TDSPCKD_CEP_PREG CEP input to P register CLK 0.36/ 0.01 0.43/ 0.01 0.53/ 0.01 0.53/ 0.01 0.53/ 0.01 0.63/ 0.00 ns Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 33 Setup and Hold Times of the RST Pins TDSPDCK_{RSTA; RSTB}_{AREG; BREG}/ TDSPCKD_{RSTA; RSTB}_{AREG; BREG} {RSTA, RSTB} input to {A, B} register CLK 0.41/ 0.11 0.46/ 0.13 0.55/ 0.15 0.55/ 0.24 0.55/ 0.15 0.63/ 0.40 ns TDSPDCK_RSTC_CREG/ TDSPCKD_RSTC_CREG RSTC input to C register CLK 0.07/ 0.10 0.08/ 0.11 0.09/ 0.12 0.09/ 0.25 0.09/ 0.12 0.13/ 0.11 ns TDSPDCK_RSTD_DREG/ TDSPCKD_RSTD_DREG RSTD input to D register CLK 0.44/ 0.07 0.50/ 0.08 0.59/ 0.09 0.59/ 0.09 0.59/ 0.09 0.67/ 0.08 ns TDSPDCK_RSTM_MREG/ TDSPCKD_RSTM_MREG RSTM input to M register CLK 0.21/ 0.22 0.23/ 0.24 0.27/ 0.28 0.27/ 0.28 0.27/ 0.28 0.28/ 0.35 ns TDSPDCK_RSTP_PREG/ TDSPCKD_RSTP_PREG RSTP input to P register CLK 0.27/ 0.01 0.30/ 0.01 0.35/ 0.01 0.35/ 0.03 0.35/ 0.01 0.43/ 0.00 ns Combinatorial Delays from Input Pins to Output Pins TDSPDO_A_CARRYOUT_MULT A input to CARRYOUT output using multiplier TDSPDO_D_P_MULT D input to P output using multiplier TDSPDO_B_P B input to P output not using multiplier Combinatorial Delays from Input Pins to Cascading Output Pins TDSPDO_{A; B}_{ACOUT; BCOUT} {A, B} input to {ACOUT, BCOUT} output TDSPDO_{A, B}_CARRYCASCOUT_MULT {A, B} input to CARRYCASCOUT output using multiplier TDSPDO_D_CARRYCASCOUT_MULT D input to CARRYCASCOUT output using multiplier TDSPDO_{A, B}_CARRYCASCOUT {A, B} input to CARRYCASCOUT output not using multiplier TDSPDO_C_CARRYCASCOUT C input to CARRYCASCOUT output Combinatorial Delays from Cascading Input Pins to All Output Pins TDSPDO_ACIN_P_MULT ACIN input to P output using multiplier TDSPDO_ACIN_P ACIN input to P output not using multiplier TDSPDO_ACIN_CARRYCASCOUT_MULT ACIN input to CARRYCASCOUT output using multiplier T DSPDO_ACIN_CARRYCASCOUT ACIN input to CARRYCASCOUT output not using multiplier TDSPDO_PCIN_CARRYCASCOUT PCIN input to CARRYCASCOUT output Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 34 Clock to Outs from Output Register Clock to Output Pins TDSPCKO_CARRYCASCOUT_PREG CLK PREG to CARRYCASCOUT output Clock to Outs from Pipeline Register Clock to Output Pins TDSPCKO_CARRYCASCOUT_MREG CLK MREG to CARRYCASCOUT output TDSPCKO_P_ADREG_MULT CLK ADREG to P output using multiplier TDSPCKO_CARRYCASCOUT_ADREG_ MULT CLK ADREG to CARRYCASCOUT output using multiplier Clock to Outs from Input Register Clock to Output Pins TDSPCKO_P_AREG_MULT CLK AREG to P output using multiplier TDSPCKO_P_BREG CLK BREG to P output not using multiplier TDSPCKO_P_CREG CLK CREG to P output not using multiplier TDSPCKO_P_DREG_MULT CLK DREG to P output using multiplier Clock to Outs from Input Register Clock to Cascading Output Pins TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG} CLK (ACOUT, BCOUT) to {A,B} register output TDSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT CLK (AREG, BREG) to CARRYCASCOUT output using multiplier TDSPCKO_CARRYCASCOUT_ BREG CLK BREG to CARRYCASCOUT output not using multiplier TDSPCKO_CARRYCASCOUT_ DREG_MULT CLK DREG to CARRYCASCOUT output using multiplier TDSPCKO_CARRYCASCOUT_ CREG CLK CREG to CARRYCASCOUT output Maximum Frequency FMAX_MULT_NOMREG Two register multiply without MREG FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect FMAX_PREADD_MULT_NOADREG_ PATDET Without ADREG with pattern detect Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 35 Clock Buffers and Networks FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG) FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect Table 32: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE TBCCCK_CE/ TBCCKC_CE(1) TBCCCK_S/ TBCCKC_S(1) Maximum Frequency Notes: 1. T BCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold time s are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. 2. T BGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values. Table 33: Input/Output Clock Switching Characteristics (BUFIO) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Maximum Frequency Table 34: Regional Clock Buffer Switching Characteristics (BUFR) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE TBRCKO_O_BYP Clock to out delay from I to O with Divide Bypass attribute set Table 31: DSP48E1 Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 36 Maximum Frequency Notes: 1. The maximum input frequency to the BUFR and BUFMR is the BUFIO F MAX frequency. Table 35: Horizontal Clock Buffer Switching Characteristics (BUFH) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE TBHCCK_CE/ TBHCKC_CE Maximum Frequency Table 36: Duty Cycle Distortion and Clock-Tree Skew Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE TDCD_CLK Global clock tree duty-cycle distortion(1) XA7A15T N/A 0.26 0.26 0.26 N/A N/A ns XA7A35T N/A 0.26 0.26 0.26 N/A N/A ns XA7A50T N/A 0.26 0.26 0.26 N/A N/A ns XA7A75T N/A 0.33 0.36 0.36 N/A N/A ns XA7A100T N/A 0.33 0.36 0.36 N/A N/A ns XQ7A50T N/A 0.26 0.26 0.26 0.26 N/A ns XQ7A100T N/A 0.33 0.36 0.36 0.36 N/A ns XQ7A200T N/A 0.48 0.54 0.54 0.54 N/A ns T TBUFIOSKEW I/O clock tree skew across one clock region Table 34: Regional Clock Buffer Switching Characteristics (BUFR) (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 37 MMCM Switching Characteristics TDCD_BUFR Regional clock tree duty cycle distortion Notes: 1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. The T CKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer tools to evaluate clock skew specific to your application. Table 37: MMCM Specification Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE MMCM_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max MMCM_FINDUTY Allowable input duty cycle: 10—49 MHz 25 25 25 25 25 % Allowable input duty cycle: 50—199 MHz 30 30 30 30 30 % Allowable input duty cycle: 200—399 MHz 35 35 35 35 35 % Allowable input duty cycle: 400—499 MHz 40 40 40 40 40 % Allowable input duty cycle: > 500 MHz 45 45 45 45 45 % MMCM_FMIN_PSCLK Minimum dynamic phase-shift clock frequency MMCM_FMAX_PSCLK Maximum dynamic phase-shift clock frequency MMCM_TSTATPHAOFFSET Static phase offset of the MMCM outputs(2) MMCM_TOUTJITTER MMCM output jitter Note 3 MMCM_TOUTDUTY MMCM output clock duty-cycle precision(4) MMCM_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max Table 36: Duty Cycle Distortion and Clock-Tree Skew (Cont’d) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1Q/-1M -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 38 MMCM_FPFDMAX Maximum frequency at the phase frequency detector MMCM_FPFDMIN Minimum frequency at the phase frequency detector MMCM_TFBDELAY Maximum delay in the feedback path 3 ns Max or one CLKIN cycle MMCM Switching Characteristics Setup and Hold TMMCMDCK_PSEN/ TMMCMCKD_PSEN TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC Setup and hold of phase-shift increment/decrement T Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK TMMCMDCK_DADDR/ TMMCMCKD_DADDR TMMCMDCK_DI/ TMMCMCKD_DI TMMCMDCK_DEN/ TMMCMCKD_DEN TMMCMDCK_DWE/ TMMCMCKD_DWE Notes: 1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any MMCM outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm. 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. 6. When CLKOUT4_CASCADE = TRUE, MMCM_F OUTMIN is 0.036 MHz. Table 37: MMCM Specification (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 39 PLL Switching Characteristics Table 38: PLL Specification Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE PLL_FINJITTER Maximum input clock period jitter < 20% of clock input period or 1 ns Max PLL_FINDUTY Allowable input duty cycle: 19—49 MHz 25 25 25 25 25 % Allowable input duty cycle: 50—199 MHz 30 30 30 30 30 % Allowable input duty cycle: 200—399 MHz 35 35 35 35 35 % Allowable input duty cycle: 400—499 MHz 40 40 40 40 40 % Allowable input duty cycle: >500 MHz 45 45 45 45 45 % PLL_F PLL_TOUTJITTER PLL output jitter Note 3 PLL_TEXTFDVAR External clock feedback variation < 20% of clock input period or 1 ns Max PLL_FPFDMAX Maximum frequency at the phase frequency detector PLL_FPFDMIN Minimum frequency at the phase frequency detector PLL_TFBDELAY Maximum delay in the feedback path 3 ns Max or one CLKIN cycle Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK TPLLDCK_DADDR/ TPLLCKD_DADDR TPLLDCK_DI/ TPLLCKD_DI TPLLDCK_DEN/ TPLLCKD_DEN TPLLDCK_DWE/ TPLLCKD_DWE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 40 Device Pin-to-Pin Output Parameter Guidelines Notes: 1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies. 2. The static offset is measured between any PLL outputs with identical phase. 3. Values for this parameter are available in the Clocking Wizard. See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm 4. Includes global clock buffer. 5. Calculated as F VCO/128 assuming output duty cycle is 50%. Table 39: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)(1) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOF Clock-capable clock input and OUTFF at pins/banks closest to the BUFGs without MMCM/PLL (near clock region)(2) XA7A15T N/A 5.70 6.61 6.61 N/A N/A ns XA7A35T N/A 5.70 6.61 6.61 N/A N/A ns XA7A50T N/A 5.70 6.61 6.61 N/A N/A ns XA7A75T N/A 5.74 6.72 6.72 N/A N/A ns XA7A100T N/A 5.74 6.72 6.72 N/A N/A ns XQ7A50T N/A 5.70 6.61 6.61 6.61 N/A ns XQ7A100T N/A 5.74 6.72 6.72 6.72 N/A ns XQ7A200T N/A 6.11 7.16 7.16 7.16 N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Refer to the Die Level Bank Numbering Overview section of 7 Series FPGA Packaging and Pinout Specification (UG475). Table 38: PLL Specification (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 41 Table 40: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)(1) Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL. TICKOFFAR Clock-capable clock input and OUTFF at pins/banks farthest from the BUFGs without MMCM/PLL (far clock region)(2) XA7A15T N/A 5.70 6.61 6.61 N/A N/A ns XA7A35T N/A 5.70 6.61 6.61 N/A N/A ns XA7A50T N/A 5.70 6.61 6.61 N/A N/A ns XA7A75T N/A 6.01 7.02 7.02 N/A N/A ns XA7A100T N/A 6.01 7.02 7.02 N/A N/A ns XQ7A50T N/A 5.70 6.61 6.61 6.61 N/A ns XQ7A100T N/A 6.01 7.02 7.02 7.02 N/A ns XQ7A200T N/A 6.89 8.05 8.05 8.05 N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. Refer to the Die Level Bank Numbering Overview section of 7 Series FPGA Packaging and Pinout Specification (UG475). Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 42 Table 41: Clock-Capable Clock Input to Output Delay With MMCM Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM. TICKOFMMCMCC Clock-capable clock input and OUTFF with MMCM XA7A15T N/A 1.00 1.00 1.00 N/A N/A ns XA7A35T N/A 1.00 1.00 1.00 N/A N/A ns XA7A50T N/A 1.00 1.00 1.00 N/A N/A ns XA7A75T N/A 1.00 1.00 1.00 N/A N/A ns XA7A100T N/A 1.00 1.00 1.00 N/A N/A ns XQ7A50T N/A 1.00 1.00 1.00 1.00 N/A ns XQ7A100T N/A 1.00 1.00 1.00 1.00 N/A ns XQ7A200T N/A 1.02 1.04 1.04 1.04 N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. MMCM output jitter is already included in the timing calculation. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 43 Table 42: Clock-Capable Clock Input to Output Delay With PLL Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL. TICKOFPLLCC Clock-capable clock input and OUTFF with PLL XA7A15T N/A 0.82 0.82 0.82 N/A N/A ns XA7A35T N/A 0.82 0.82 0.82 N/A N/A ns XA7A50T N/A 0.82 0.82 0.82 N/A N/A ns XA7A75T N/A 0.82 0.82 0.82 N/A N/A ns XA7A100T N/A 0.82 0.82 0.82 N/A N/A ns XQ7A50T N/A 0.82 0.82 0.82 0.82 N/A ns XQ7A100T N/A 0.82 0.82 0.82 0.82 N/A ns XQ7A200T N/A 0.81 0.81 0.81 0.81 N/A ns Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is already included in the timing calculation. Table 43: Pin-to-Pin, Clock-to-Out using BUFIO Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 44 Device Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted. Table 44: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) TPSFD/ TPHFD Full delay (legacy delay or default delay) global clock input and IFF (2) without MMCM/PLL with ZHOLD_DELAY on HR I/O banks Notes: 1. Setup and hold times are measured over worst case conditions (p rocess, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input flip-flop or latch. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 45 Table 45: Clock-Capable Clock Input Setup and Hold With MMCM Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1) TPSMMCMCC/ TPHMMCMCC No delay clock- capable clock input and IFF (2) with MMCM Notes: 1. Setup and hold times are measured over worst case conditions (pro cess, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input flip-flop or latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 46 Table 46: Clock-Capable Clock Input Setup and Hold With PLL Symbol Description Device Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1) TPSPLLCC/ TPHPLLCC No delay clock-capable clock input and IFF (2) with PLL Notes: 1. Setup and hold times are measured over worst case conditions (pro cess, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input flip-flop or latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. Table 47: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard. Table 48: Sample Window Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 47 Additional Package Parameter Guidelines The parameters in this section provide the necessary values for calculating timing budgets for Artix-7 FPGA clock transmitter and receiver data-valid windows. TSAMP_BUFIO Sampling error at receiver pins using BUFIO(2) Notes: 1. This parameter indicates the total sampling error of the Arti x-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include: - CLK0 MMCM jitter - MMCM accuracy (phase offset) - MMCM phase shift resolution These measurements do not include package or clock tree skew. 2. This parameter indicates the total sampling error of the Arti x-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew. Table 49: Package Skew Symbol Description Device Package Value Units CSG325 ps XC7A15T CPG236 48 ps CSG324 104 ps CSG325 142 ps FTG256 98 ps FGG484 97 ps XC7A25T CPG236 ps CSG325 ps XC7A35T CPG236 48 ps CSG324 104 ps CSG325 142 ps FTG256 98 ps FGG484 97 ps XC7A50T CPG236 48 ps CSG324 104 ps CSG325 142 ps FTG256 98 ps FGG484 97 ps XC7A75T CSG324 113 ps FTG256 120 ps FGG484 144 ps FGG676 153 ps Table 48: Sample Window (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1M/-1Q -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 48 GTP Transceiver Specifications GTP Transceiver DC Input and Output Levels Table 50 summarizes the DC output specifications of the GTP transceivers in Artix-7 FPGAs. Consult 7 Series FPGAs GTP Transceiver User Guide (UG482) for further details. FTG256 120 ps FGG484 144 ps FGG676 153 ps XC7A200T SBG484 111 ps FBG484 109 ps FBG676 121 ps FFG1156 151 ps XA7A15T CPG236 48 ps CSG324 104 ps CSG325 142 ps XA7A35T CPG236 48 ps CSG324 104 ps CSG325 142 ps XA7A50T CPG236 48 ps CSG324 104 ps CSG325 142 ps XA7A75T CSG324 113 ps FGG484 144 ps XA7A100T CSG324 113 ps FGG484 144 ps XQ7A50T CS325 142 ps FG484 97 ps XQ7A100T CS324 113 ps FG484 144 ps XQ7A200T RS484 111 ps RB484 109 ps RB676 121 ps Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die pad to ball. 2. Package delay information is available for these device/package combinations. This information can be used to deskew the pack age. Table 50: GTP Transceiver DC Specifications Symbol DC Parameter Conditions Min Typ Max Units DVPPOUT Differential peak-to-peak output voltage(1) Transmitter output swing is set to maximum setting 1000 – – mV V CMOUTDC DC common mode output voltage Equation based V MGTAVTT –D VPPOUT/4 mV ROUT Differential output resistance – 100 – Ω Table 49: Package Skew (Cont’d) Symbol Description Device Package Value Units Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 50 GTP Transceiver Switching Characteristics Consult 7 Series FPGAs GTP Transceiver User Guide (UG482) for further information. Table 52: GTP Transceiver Performance Symbol Description Output Divider Speed Grade Units -2LE (1.0V) -1 (1.0V) -1LI (0.95V) -1Q (1.0V) -1M (1.0V) -2LE (0.9V) Package Type FF FB SB FG FT CS CP FF FB SB RB RS FG FT CS CP FF FB SB RB RS FG FT CS CP FF FB SB FG FT CS CP FGTPRANGE PLL line rate range F GTPPLLRANGE GTP transceiver PLL frequency range Table 53: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE FGTPDRPCLK GTPDRPCLK maximum frequency 175 175 156 156 125 MHz Table 54: GTP Transceiver Reference Clock Switching Characteristics Symbol Description Conditions All Speed Grades Units Min Typ Max FGCLK Reference clock frequency range 60 – 660 MHz TRCLK Reference clock rise time 20% – 80% – 200 – ps TFCLK Reference clock fall time 80% – 20% – 200 – ps TDCREF Reference clock duty cycle Tr ansceiver PLL only 40 – 60 % X-Ref Target - Figure 5 Figure 5: Reference Clock Timing Parameters ds181_03_062811 80% 20% T FCLK T RCLK Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 51 Table 55: GTP Transceiver PLL/Lock Time Adaptation Symbol Description Conditions All Speed Grades Units Min Typ Max TLOCK Initial PLL lock – – 1 ms TDLOCK Clock recovery phase acquisition and adaptation time. After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input. – 50,000 2.3 x10 6 UI Table 56: GTP Transceiver User Clock Switching Characteristics(1) Symbol Description Conditions Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE Notes: 1. Clocking must be implemented as described in 7 Series FPGAs GTP Transceiver User Guide (UG482). Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 52 Table 57: GTP Transceiver Transmitter Switching Characteristics Symbol Description Cond ition Min Typ Max Units FGTPTX Serial data rate range 0.500 – F GTPMAX Gb/s TRTX TX rise time 20%–80% – 50 – ps TFTX TX fall time 80%–20% – 50 – ps TLLSKEW TX lane-to-lane skew(1) – – 500 ps TJ6.6 Total Jitter(2)(3)

6.6 Gb/s

– – 0.30 UI DJ6.6 Deterministic Jitter(2)(3) – – 0.15 UI TJ5.0 Total Jitter(2)(3)

5.0 Gb/s

– – 0.30 UI DJ5.0 Deterministic Jitter(2)(3) – – 0.15 UI TJ4.25 Total Jitter(2)(3)

4.25 Gb/s

– – 0.30 UI DJ4.25 Deterministic Jitter(2)(3) – – 0.15 UI TJ3.75 Total Jitter(2)(3)

3.75 Gb/s

– – 0.30 UI DJ3.75 Deterministic Jitter(2)(3) – – 0.15 UI TJ3.2 Total Jitter(2)(3) DJ3.2 Deterministic Jitter(2)(3) –– 0 . 1 U I TJ3.2L Total Jitter(2)(3) DJ3.2L Deterministic Jitter(2)(3) – – 0.16 UI TJ2.5 Total Jitter(2)(3) DJ2.5 Deterministic Jitter(2)(3) – – 0.08 UI TJ1.25 Total Jitter(2)(3) DJ1.25 Deterministic Jitter(2)(3) – – 0.06 UI TJ500 Total Jitter(2)(3)

500 Mb/s

–– 0 . 1 U I DJ500 Deterministic Jitter(2)(3) – – 0.03 UI Notes: 1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTP Quad ). 2. Using PLL[0/1]_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinat ions. 3. All jitter values are based on a bit-error ratio of 1e -12. 4. PLL frequency at 3.2 GHz and TXOUT_DIV = 2. 5. PLL frequency at 1.6 GHz and TXOUT_DIV = 1. 6. PLL frequency at 2.5 GHz and TXOUT_DIV = 2. 7. PLL frequency at 2.5 GHz and TXOUT_DIV = 4. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 53 Table 58: GTP Transceiver Receiver Switching Characteristics Symbol Description Min Typ Max Units FGTPRX Serial data rate RX oversampler not enabled 0.500 – F GTPMAX Gb/s TRXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data – 10 – ns RXOOBVDPP OOB detect threshold peak-to-peak 60 – 150 mV RXSST Receiver spread-spectrum tracking(1) Modulated @ 33 kHz –5000 – 5000 ppm RXRL Run length (CID) – – 512 UI RXPPMTOL Data/REFCLK PPM offset tolerance –1250 – 1250 ppm SJ Jitter Tolerance(2) JT_SJ6.6 Sinusoidal Jitter(3) 6.6 Gb/s 0.44 – – UI JT_SJ5.0 Sinusoidal Jitter(3) 5.0 Gb/s 0.44 – – UI JT_SJ4.25 Sinusoidal Jitter(3) 4.25 Gb/s 0.44 – – UI JT_SJ3.75 Sinusoidal Jitter(3) 3.75 Gb/s 0.44 – – UI JT_SJ3.2 Sinusoidal Jitter(3) 3.2 Gb/s(4) 0.45 – – UI JT_SJ3.2L Sinusoidal Jitter(3) 3.2 Gb/s(5) 0.45 – – UI JT_SJ2.5 Sinusoidal Jitter(3) 2.5 Gb/s(6) 0.5 – – UI JT_SJ1.25 Sinusoidal Jitter(3) 1.25 Gb/s(7) 0.5 – – UI JT_SJ500 Sinusoidal Jitter(3) 500 Mb/s 0.4 – – UI SJ Jitter Tolerance with Stressed Eye(2) JT_TJSE3.2 Total Jitter with Stressed Eye(8) 3.2 Gb/s 0.70 – – UI JT_TJSE6.6 6.6 Gb/s 0.70 – – UI JT_SJSE3.2 Sinusoidal Jitter with Stressed Eye(8) 3.2 Gb/s 0.1 – – UI JT_SJSE6.6 6.6 Gb/s 0.1 – – UI Notes: 1. Using RXOUT_DIV = 1, 2, and 4. 2. All jitter values are based on a bit error ratio of 1e –12. 3. The frequency of the injected sinusoidal jitter is 10 MHz. 4. PLL frequency at 3.2 GHz and RXOUT_DIV = 2. 5. PLL frequency at 1.6 GHz and RXOUT_DIV = 1. 6. PLL frequency at 2.5 GHz and RXOUT_DIV = 2. 7. PLL frequency at 2.5 GHz and RXOUT_DIV = 4. 8. Composite jitter. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 54 GTP Transceiver Protocol Jitter Characteristics For Table 59 through Table 63, the 7 Series FPGAs GTP Transceiver User Guide (UG482) contains recommended settings for optimal usage of protocol specific characteristics. Table 59: Gigabit Ethernet Protocol Characteristics Description Line Rate (Mb/s) Min Max Units Gigabit Ethernet Transmitter Jitter Generation Total transmitter jitter (T_TJ) 1250 – 0.24 UI Gigabit Ethernet Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 1250 0.749 – UI Table 60: XAUI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units XAUI Transmitter Jitter Generation Total transmitter jitter (T_TJ) 3125 – 0.35 UI XAUI Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance 3125 0.65 – UI Table 61: PCI Express Protocol Characteristics(1) Standard Description Line Rate (Mb/s) Min Max Units PCI Express Transmitter Jitter Generation PCI Express Gen 1 Total transmitter jitter 2500 – 0.25 UI PCI Express Gen 2 Total transmitter jitter 5000 – 0.25 UI PCI Express Receiver High Frequency Jitter Tolerance PCI Express Gen 1 Total receiver jitter tolerance 2500 0.65 – UI PCI Express Gen 2(2) Receiver inherent timing error 5000 0.40 – UI Receiver inherent deterministic timing error 0.30 – UI Notes: 1. Tested per card electromechanical (CEM) methodology. 2. Using common REFCLK. Table 62: CEI-6G Protocol Characteristics Description Line Rate (M b/s) Interface Min Max Units CEI-6G Transmitter Jitter Generation Total transmitter jitter(1) 4976–6375 CEI-6G-SR – 0.3 UI CEI-6G Receiver High Frequency Jitter Tolerance Total receiver jitter tolerance(1) 4976–6375 CEI-6G-SR 0.6 – UI Notes: 1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 55 Integrated Interface Block for PCI Express Designs Switching Characteristics More information and documentation on solutions for PCI Express designs can be found at: www.xilinx.com/products/technology/pci-express.html Table 63: CPRI Protocol Characteristics Description Line Rate (Mb/s) Min Max Units CPRI Transmitter Jitter Generation Total transmitter jitter 614.4 – 0.35 UI 1228.8 – 0.35 UI 2457.6 – 0.35 UI 3072.0 – 0.35 UI 4915.2 – 0.3 UI 6144.0 – 0.3 UI CPRI Receiver Frequency Jitter Tolerance Total receiver jitter tolerance 614.4 0.65 – UI 1228.8 0.65 – UI 2457.6 0.65 – UI 3072.0 0.65 – UI 4915.2 (1) 0.60 – UI Notes: 1. Tested to CEI-6G-SR. Table 64: Maximum Performance for PCI Express Designs Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE Notes: 1. Refer to PG054, 7 Series FPGAs Integrated Block for PCI Express Product Guide for specific supported core configurations. Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 56 XADC Specifications Table 65: XADC Specifications Parameter Symbol Comments/Conditions Min Typ Max Units VCCADC = 1.8V ± 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, –55°C ≤ Tj ≤ 125°C, Typical values at Tj=+40°C ADC Accuracy(1) Resolution 12 – – Bits Integral Nonlinearity(2) INL –40°C ≤ Tj ≤ 100°C – – ±2 LSBs Differential Nonlinearity DNL No missing codes, guaranteed monotonic – – ±1 LSBs Offset Error Unipolar –40°C ≤ Tj ≤ 100°C – – ±8 LSBs Bipolar –55°C ≤ Tj ≤ 125°C – – ±4 LSBs Gain Error –– ± 0 . 5 % Offset Matching – – 4 LSBs Gain Matching –– 0 . 3 % Sample Rate –– 1 M S / s Signal to Noise Ratio(2) SNR F SAMPLE = 500KS/s, FIN =2 0k H z 6 0 – – d B RMS Code Noise External 1.25V reference – – 2 LSBs On-chip reference – 3 – LSBs Total Harmonic Distortion(2) THD F SAMPLE = 500KS/s, FIN =2 0k H z 7 0 – – d B Analog Inputs(3) ADC Input Ranges Unipolar operation 0 – 1 V Bipolar operation –0.5 – +0.5 V Unipolar common mode range (FS input) 0 – +0.5 V Bipolar common mode range (FS input) +0.5 – +0.6 V Maximum External Channel Input Ranges Adjacent analog channels set within these ranges should not corrupt measurements on adjacent channels –0.1 – V CCADC V Auxiliary Channel Full Resolution Bandwidth FRBW 250 – – kHz On-Chip Sensors Temperature Sensor Error –40°C ≤ Tj ≤ 100°C – – ±4 °C Supply Sensor Error –40°C ≤ Tj ≤ 100°C – – ±1 % Conversion Rate(4) Conversion Time - Continuous t CONV Number of ADCCLK cycles 26 – 32 Cycles Conversion Time - Event t CONV Number of CLK cycles – – 21 Cycles DRP Clock Frequency DCLK DRP clock frequency 8 – 250 MHz ADC Clock Frequency ADCCLK Derived from DCLK 1 – 26 MHz DCLK Duty Cycle 40 – 60 % Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 57 Configuration Switching Characteristics XADC Reference(5) External Reference V REFP Externally supplied reference voltage 1.20 1.25 1.30 V On-Chip Reference Ground V REFP pin to AGND, –40°C ≤ Tj ≤ 100°C 1.2375 1.25 1.2625 V Ground VREFP pin to AGND, 1.225 1.25 1.275 V Notes: 1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature is enabled. 2. Only specified for bitstream option XADCEnhancedLinearity = ON. 3. See the ADC chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480) for a detailed description. 4. See the Timing chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480) for a detailed description. 5. Any variation in the reference voltage from the nominal V REFP = 1.25V and VREFN = 0V will result in a deviation from the ideal transfer function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric type applications allowing reference to vary by ±4% is permitted. Table 66: Configuration Switching Characteristics Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE Power-up Timing Characteristics TPOR(1) Power-on reset (50 ms ramp rate time) 10/50 10/50 10/50 10/50 10/50 ms, Min/Max Power-on reset (1 ms ramp rate time) 10/35 10/35 10/35 10/35 10/35 ms, Min/Max CCLK Output (Master Mode) TMCCKL Master CCLK clock Low time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max TMCCKH Master CCLK clock High time duty cycle 40/60 40/60 40/60 40/60 40/60 %, Min/Max FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK CCLK Input (Slave Modes) EMCCLK Input (Master Mode) Table 65: XADC Specifications (Cont’d) Parameter Symbol Comments/Conditions Min Typ Max Units Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 58 Internal Configuration Access Port FICAPCK Internal configuration access port (ICAPE2) clock frequency Master/Slave Serial Mode Programming Switching TDCCK/ TCCKD SelectMAP Mode Programming Switching TSMDCCK/ TSMCCKD TSMCSCCK/ TSMCCKCS TSMWCCK/ TSMCCKW TSMCKCSO CSO_B clock to out (330 Ω pull-up resistor required) Boundary-Scan Port Timing Specifications TTAPTCK/ TTCKTAP BPI Flash Master Mode Programming Switching TBPICCO(2) A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B clock to out TBPIDCC/ TBPICCD SPI Flash Master Mode Programming Switching TSPIDCC/ TSPICCD STARTUPE2 Ports Min/Max FCFGMCLKTOL STARTUPE2 CFGMCLK output frequency tolerance Table 66: Configuration Switching Characteristics (Cont’d) Symbol Description Speed Grade Units1.0V 0.95V 0.9V -3 -2/-2LE -1 -1LI -2LE Send Feedback

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 59 eFUSE Programming Conditions Table 67 lists the programming conditions specifically for eFUSE. For more information, see 7 Series FPGA Configuration User Guide (UG470).

Revision History

The following table shows the revision history for this document: Device DNA Access Port Notes: 1. To support longer delays in configuration, use the design solutions described in 7 Series FPGA Configuration User Guide (UG470). 2. Only during configuration, the last edge is determi ned by a weak pull-up/pull-down resistor in the I/O. Table 67: eFUSE Programming Conditions(1) Symbol Description Min Typ Max Units IFS VCCAUX supply current – – 115 mA Tj Temperature range 15 – 125 °C Notes: 1. The FPGA must not be configured during eFUSE programming. Date Version Description 09/26/2011 1.0 Initial Xilinx release. 11/07/2011 1.1 Revised the V OCM specification in Table 11. Updated the AC Switching Characteristics based upon the ISE 13.3 software v1.02 speed specification throughout document including Table 13 and Table 14. Added MMCM_TFBDELAY while adding MMCM_ to the symbol names of a few specifications in Table 37 and PLL to the symbol names in Table 38. In Table 39 through Table 46, updated the pin-to- pin description with the SSTL15 standard. Updated units in Table 46. 02/13/2012 1.2 Updated the Artix-7 fam ily of devices listed throughout the entire data sheet. Updated the AC Switching Characteristics based upon the ISE 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00 for the -2L speed grade. Updated summary description on page 1. In Table 2, revised VCCO for the 3.3V HR I/O banks and updated Tj. Updated the notes in Table 5. Added MGTAVCC and MGTAVTT power supply ramp times to Table 7. Rearranged Table 8, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12, SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I, DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table 9 and Table 10. Revised the specifications in Table 11. Revised VIN in Table 50. Updated the eFUSE Programming Conditions section and removed the endurance table. Added the table. Revised FTXIN and FRXIN in Table 56. Revised ICCADC and updated Note 1 in Table 65. Revised DDR LVDS transmitter data width in Table 15. Removed notes from Table 27 as they are no longer applicable. Updated specifications in Table 66. Updated Note 1 in Table 36.

06/01/2012 1.3 Reorganized entire data sheet including adding Table 43 and Table 47. including SSTL135 and SSTL135_R. Removed VOX column and added DIFF_HSUL_12 to Table 10. Updated VOL in Table 11. Updated Table 15 and removed notes 2 and 3. Updated Table 16. (1.0V), -1, and v1.01 for the -2L (0.9V) speed specifications throughout the document. Table 66 to Table 37 and Table 38. Table 10. Removed the XC7A350T device from data sheet. Table 65, updated Note 1. In Table 66, updated TPOR. for -3, -2, -2L (1.0V), -1 speed specifications. Revised IDCIN and IDCOUT and added Note 5 in Table 1. Added Note 2 to Table 2. Updated Table 5. Added minimum current specifications to Table 6. Removed SSTL12 and HSTL_I_12 from Table 8. Table 16. Updated Note 1 in Table 34. Revised Table 36. Updated Note 1 and Note 2 in Table 49. revised Note 4 through Note 7. In Table 63, revised and added Note 1. added the Internal Configuration Access Port section. -3, -2, -2L (1.0V), and -1 speed specifications, and v1.05 for the -2L (0.9V) speed specifications. Production changes to Table 13 and Table 14 for -2L (0.9V) speed specifications. 5 and then added new Note 5. Revised VIN description, removed Note 10, and added Note 7 in Table 2. Table 1 and Table 4. Added Note 1 to Table 11. Removed Note 1 from Table 14. Updated Table 16 title. package to Table 50 and Table 52. Reference sections and notes. Added TUSRCCLKO and FDNACK to Table 66.

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 61 01/07/2014 1.9 In Table 13, promoted all XC7A75T speed grades from Advance to Production and all XQ7A50T speed grades from Preliminary to Advance. In Table 14, inserted “Vivado tools 2013.3” for the production XC7A75T speed grades. 01/23/2014 1.10 Updated the AC Switching Characteristics based upon ISE 14.7 and Vivado 2013.4. Updated Note 5 in Table 2. Removed pad pull-down @ VIN =1 . 8 V f o r IRPD in Table 3. Added Note 2 to Table 4. Removed XQ7A50T fromTable 12, Table 13, and Table 14. In Table 13, changed speed grades for XA Artix-7 FPGAs and defense-grade Artix-7Q family from -2 to -2I and -1 to -1I, and moved all speed grades of XA7A100T, and -1I and -2I speed grades of XQ7A100T from Preliminary to Production. In Table 14, updated production software for XA7A100T and XQ7A100T. Added HSUL_12_F, DIFF_HSUL_12_F, MOBILE_DDR_S, MOBILE_DDR_F, DIFF_MOBILE_DDR_S, and DIFF_MOBILE_DDR_F to Table 17. Removed introductory text in Device Pin-to-Pin Output Parameter Guidelines. 03/04/2014 1.11 Updated Note 2 in Table 4. In Table 13, moved XQ7A100T -1M speed grade from Preliminary to Production. In Table 14, added production software for XQ7A100T -1M speed grade. 03/28/2014 1.12 In Table 5, added ICCINTQ, ICCOQ, ICCAUXQ, and ICCBRAMQ values for XC7A35T, XC7A50T, XA7A35T, XA7A50T, and XQ7A50T devices. In Table 6, added power-on current values for XC7A35T, XC7A50T, XA7A35T, XA7A50T, and XQ7A50T devices. In Table 12, added row for XC7A35T, XC7A50T, and XC7A75T devices. In Table 13, moved all speed grades of XC7A35T and XC7A50T devices from Advance to Production, and added XQ7A50T. In Table 14, added XQ7A50T and production software for XC7A35T and XC7A50T -3, -2, -2L (1.0V), -1, and -2L (0.9V) speed grades. For FIDELAYCTRL_REF in Table 25, updated REFCLK frequency of 300 MHz, added REFCLK frequency of 400 MHz, and updated Note 1. In Table 36, added TCKSKEW data for XC7A35T and XC7A50T devices. In Table 39, updated TICKOF data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 40, updated TICKOFFAR data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 41, added TICKOFMMCMCC data for -2L (0.9V) speed grade of XC7A35T and XC7A50T devices. In Table 42, added TICKOFPLLCC data for -2L (0.9V) speed grade of XC7A35T and XC7A50T devices. In Table 44, updated TPSFD/TPHFD data for -2/-2L, -1, and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 45, updated TPSMMCMCC/TPHMMCMCC data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 46, updated TPSPLLCC/TPHPLLCC data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 49, added package skew values for XC7A35T, XC7A50T, XA7A35T, XA7A50T, and XQ7A50T devices. 05/13/2014 1.13 In AC Switching Characteristics, updated to Vivado 2014.1. In Table 12, updated Vivado 2014.1 version numbers and consolidated rows. In Table 13, moved all XA7A75T speed grades from Advance to Preliminary and all XQ7A200T speed grades from Preliminary to Production. In Table 14, added production software for XQ7A200T -2, -1, and -1M speed grades. Added timing data for XA7A35T, XA7A50T, XA7A75T, and XQ7A50T devices to Table 39, Table 40, Table 41, Table 42, Table 44, Table 45, and Table 46. 07/01/2014 1.14 Updated Note 2 in Table 4 per the customer notice XCN14014 : 7 Series FPGA and Zynq-7000 AP SoC I/O Undershoot Voltage Data Sheet Update. In Power-On/Off Power Supply Sequencing, added sentence about there being no recommended sequence for supplies not shown. In AC Switching Characteristics, updated to Vivado 2014.2. In Table 12, added row for XQ7A50T. In Table 13, moved all XQ7A50T speed grades from Advance to Production. In Table 14, added production software for XQ7A50T -2, -1, and -1M speed grades. In Table 36, added TCKSKEW values for XA7A35T, XA7A50T, and XQ7A50T. Updated description of TICKOF in Table 39 and added Note 2. Updated description of TICKOFFAR in Table 40 and added Note 2. In Table 50, moved DVPPOUT value of 1000 mV from Max to Min column, updated VIN DC parameter description, and added Note 2. Added “peak-to-peak” to labels in Figure 3 and Figure 4. Added note after Figure 4. Added Note 1 to Table 64. In Table 66, replaced USRCCLK Output with STARTUPE2 Ports and added FCFGMCLK and FCFGMCLKTOL. 09/23/2014 1.15 Removed 3.3V as descriptor of HR I/O banks throughout. Updated Note 3 in Table 5. In Table 13, moved all XA7A35T and XA7A50T speed grades from Advance to Production, and all XA7A75T speed grades from Preliminary to Production. In Table 14, added production software for XA7A35T, XA7A50T, and XA7A75T -2, -1, and -1Q speed grades, and removed Note 2. Added I/O Standard Adjustment Measurement Methodology. 10/09/2014 1.16 Added XC7A15T and XA7A15T devices. Added -1LI speed grade throughout. Updated Introduction. Added -1LI (0.95V) to description of VCCINT and VCCBRAM in Table 2. Updated Note 1 and added Note 2 to Table 14. Date Version Description Send Feedback

brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos. Table 2. Updated the AC Switching Characteristics based upon Vivado 2014.4. In Table 12, updated in the Vivado Tools. In Table 16, moved LPDDR2 row to end of 2:1 Memory Controllers section. Updated speed grade heading row in Table 52. Table 19 and Table 20. Removed minimum sample rate specification from Table 65. Table 49. Removed Pb-free G suffix from packages in Table 50 and Table 52. 2016.4. In Table 13, added -2LE (0.9V) speed grade to Advance column for XC7A12T and XC7A25T. and Substrates in Lead-free (FFG/FBG/SBG) Packages.

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS181 (v1.22) April 13, 2017 www.xilinx.com Product Specification 63 AUTOMOTIVE APPLICATIONS DISCLAIMER AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTI VE SAFETY STANDARD (“SAFETY DESIGN”). CUSTOMER SHALL, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY. Send Feedback