WM72016-6 CYPRESS | Alldatasheet
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16Kbit Secure F-RAM Memory with Gen-2 RFID Access & Serial Port Direct Memory Access This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-86227 Rev. ** Revised February 25, 2013
DESCRIPTION
The WM72016-6 is a RFID transponder IC with nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory, or F-RAM, is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 20 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike EEPROM‟s, the WM72016-6 write operations are zero power – there is no power or speed premium paid for executing writes into the WM72016-6 as compared to read power and speed. Operation of the memory is fully symmetric: it has an equivalent read and write range. The WM72016-6‟s RFID interface is compatible with the EPC Class -1 Generation -2 UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.2.0 Specification for RFID Air Interface. The WM72016-6 is a two chip configurat ion offered in various forms: standard IC package or wafers. All specifications discussed here in are applicable to the combined chipset operation. Figure 1. System Block Diagram
FEATURES
16 Kbit Ferroelectric Nonvolatile RAM
Organized as 1024 x 16 bits Very High Read/Write Endurance (> 1014) 20-Year Data Retention Gamma Stability Demonstrated to > 30 kGy Symmetric Read/Write Operation Advanced High-Reliability Ferroelectric Process Interface and Security Features EPC Class 1 Gen2 ( ISO18000-6C) RFID Compatible Interface (revision 1.2.0) 192-Bit Memory: 96 -Bit Electronic Product Code™ (EPC), 32 -Bit Access Password, 32 -Bit KILL Password, 64-Bit TID Memory (Factory Programmed and Locked) Inventory, Read, Write and Erase features Kill Command Block Permalock Command Access Command UHF carrier frequencies from 860 MHz to 960 MHz ISM band, ASK demodulation Tag-to-reader link frequencies up to 640Kbps Reader-to-tag asymptotical transmission rates up to 160Kbps Supports FM0 and MMS data encoding formats Serial Port Interface Custom Features Stored Address Pointer to Improve Data Write Speed Stored Address Pointer Lock Block Write Command Variable USER memory block size support Interrupt Generation Ultra Low Power Operation Memory Read/Write Sensitivity: < -6 dBm (typ.) Industry Standard Configurations Industrial Temperature -40 C to +85 C Bumped Wafers 8-pin UDFN WM72016-6 RFID Tag with F-RAM RFID Reader (Class-1 Gen-2)
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 2 of 33 PIN CONFIGURATION (UDFN PACKAGE) Top View Ser_clk Ser_dat1 Ser_dat0 Ser_CS ANT- ANT+ Vddr Vddraw 3.0 mm × 3.0 mm body, 0.65 mm pad pitch PIN DESCRIPTION Pin Name Pin Number Type Description ANT+, ANT- 7, 8 Input RFID Antenna. Connect to external RFID antenna terminal s. Connect ANT - to ex ternal RFID antenna terminal, a lso acts as ground. Ser_clk 1 Input Serial interface clock Ser_dat1, Ser_dat0 2, 3 I/O Serial interface bi-directional data Ser_CS 4 I/O Serial interface bi-directional chip select/interrupt Vddraw 5 PWR Power supply input pin. DC supply (2.1V to 3.0V) Vddr 6 PWR Power supply output pin. This supply is int ernally generated via the RF field . The Vddr and Vddraw pins are tied together for most applications. Contact the factory for other applications such as battery assisted systems.
unique applications of an RFID solution. and symmetrical characteristics. RAM memory, and power management unit. The external antenna is connected directly to the RFID antenna. processes commands to enable access in and out of F-RAM memory. Figure 2. Block Diagram
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 4 of 33 MEMORY MAP WM72016-6‟s memory is partitioned according to the logical and physical mapping shown in the table below. Table 1: Memory Map DSPI Address Gen-2 Memory Bank Gen-2 Address Word Pointer (EBV8) Description 0x000 RESERVED 0x000 0x00 Kill Password[31:16] 0x001 RESERVED 0x001 0x01 Kill Password[15:0] 0x002 RESERVED 0x002 0x02 Access Password[31:16] 0x003 RESERVED 0x003 0x03 Access Password[15:0] 0x004 EPC 0x000 0x00 CRC 0x005 EPC 0x001 0x01 PC 0x006 EPC 0x002 0x02 EPC - Word 0 (MSW) 0x007 EPC 0x003 0x03 EPC - Word 1 0x008 EPC 0x004 0x04 EPC - Word 2 0x009 EPC 0x005 0x05 EPC - Word 3 0x00A EPC 0x006 0x06 EPC - Word 4 0x00B EPC 0x007 0x07 EPC - Word 5 (LSW) 0x00C EPC 0x008 0x08 EPC - read memory 0x00D EPC 0x009 0x09 EPC - read memory 0x00E SERVICE 0x00A 0x0A RESERVED 0x00F SERVICE 0x00B 0x0B RESERVED 0x010 TID 0x000 0x00 TID - Word 0: xE201 0x011 TID 0x001 0x01 TID - Word 1: x6216 0x012 TID 0x002 0x02 TID - Word 2: Serial #1 0x013 TID 0x003 0x03 TID - Word 3: Serial #2 0x014 USER 0x000 0x00 RESERVED 0x015 USER 0x001 0x01 RFU 0x016 USER 0x002 0x02 Control/Status Register 0x017 USER 0x003 0x03 Working Stored Address Register 0x018 USER 0x004 0x04 0x019 USER 0x005 0x05 0x01A USER 0x006 0x06 USER Memory - Start 0x01B USER 0x007 0x07 0x0FE USER 0x0EA 0x816A 0x0FF USER 0x0EB 0x816B 0x100 USER 0x0EC 0x816C 0x101 USER 0x0ED 0x816D … … … … 0x1FE USER 0x1EA 0x836A 0x1FF USER 0x1EB 0x836B 0x200 USER 0x1EC 0x836C 0x201 USER 0x1ED 0x836D … … … … 0x3BA USER 0x3A6 0x8726 0x3BB USER 0x3A7 0x8727 16k Memory: END (BLK_SIZE = 1 word/block) 0x3BC USER 0x3A8 0x8728
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 5 of 33 DSPI Address Gen-2 Memory Bank Gen-2 Address Word Pointer (EBV8) Description 0x3BD USER 0x3A9 0x8729 0x3BE USER 0x3AA 0x872A … … … … 0x3DA USER 0x3C6 0x8746 0x3DB USER 0x3C7 0x8747 16k Memory: END (BLK_SIZE = 2 words/block) 0x3DC USER 0x3C8 0x8748 0x3DD USER 0x3C9 0x8749 0x3DE USER 0x3CA 0x874A … … … … 0x3EA USER 0x3D6 0x8756 0x3EB USER 0x3D7 0x8757 16k Memory: END (BLK_SIZE = 4 words/block) 0x3EC USER 0x3D8 0x8758 0x3ED USER 0x3D9 0x8759 0x3EE USER 0x3DA 0x875A … … … … 0x3F3 USER 0x3DF 0x875F 16k Memory: END (BLK_SIZE = 8 words/block) 0x3F4 USER 0x3E0 0x8760 0x3F5 USER 0x3E1 0x8761 0x3F6 USER 0x3E2 0x8762 0x3F7 USER 0x3E3 0x8763 16k Memory: END (BLK_SIZE = 16 words/block) 0x3F8 USER 0x3E4 0x8764 0x3F9 USER 0x3E5 0x8765 16k Memory: END (BLK_SIZE = 32 words/block) 0x3FA USER 0x3E6 0x8766 0x3FB USER 0x3E7 0x8767 (BLK_SIZE > 32 words/block) 0x3FC USER 0x3E8 0x8768 RESERVED 0x3FD USER 0x3E9 0x8769 RESERVED 0x3FE USER 0x3EA 0x876A RESERVED 0x3FF USER 0x3EB 0x876B RESERVED NOTE: When accessing the memory through the DSPI serial port, c are must be taken to ensure that reserved memory required to store critical parameters for the operation of the device is not altered.
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 6 of 33 USER MEMORY BLOCK SIZE DEFINITION x000 x001 x002 x003 x004 x005 x006 x007 x008 x009 x00A x00B x00C x00D x00E x00F x010 x011 BLK:0 BLK:1 BLK_SIZ=111 BLK:0 BLK_SIZ=110 BLK:0 BLK:1 BLK_SIZ=101 BLK:0 BLK:1 BLK_SIZ=100 BLK:0 BLK:1 BLK:2 ... BLK_SIZ=011 BLK:0 BLK:1 BLK:2 BLK:3 BLK:4 ... BLK_SIZ=010 BLK:0 BLK:1 BLK:2 BLK:3 BLK:4 BLK:5 BLK:6 BLK:7 BLK:8 ... BLK_SIZ=001 BLK:0 BLK:1 BLK:2 BLK:3 BLK:4 BLK:5 BLK:6 BLK:7 BLK:8 BLK:9 BLK:10 BLK:11 BLK:12 BLK:13 BLK:14 BLK:15 BLK:16 BLK:17 BLK_SIZ=000 ... USER MEMORY ADDRESS x013 x012 x014 x017 x018 x01F x020 x03F x040 x07F x080 x0FF x100 ... ... ... ... ... ... BLK:1 ... ... ... ...
- The figure shows the minimum number of Gen2 instructions required to perform a SELECT, INVENTORY,
penalty is shown within the context of the protocol. Figure 3. Gen2 Memory Write Cycle Comparison: F-RAM vs. EEPROM Memories DSPI serial port will continue to function normally.
effect on the functionality of the DSPI serial port. are completely programmable. The Protocol Control field is shown in Figure 4. Figure 4. EPC Protocol Control Word shipped from the factory with the EPC memory bank unlocked. bank is permanently locked at the factory and obeys the ISO/IEC 15963 numbering convention.
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 9 of 33 Table 2: TID memory Bank Fields Class Identifier MDID[11:4] MDID[3:0] TMN[11:0] ID[31:16] ID[15:0] 0 7 8 15 16 20 31 32 47 48 63 Figure 5. TID Memory Bank Fields ships from the factory completely unlocked. At the bit-boundary of two consecutive logic 0s. baseband bit period by 2, 4, or 8 as shown in Figure 7, Figure 8, and Figure 9. 00h – 07h E2 ISO/IEC 15963 class-identifier 08h – 13h 016 Mask-Designer Identifier (MDID) – Ramtron International 14h – 1Fh 216 Tag model number 20h – 3Fh 32-bit unique identifier
0 T 2T
Figure 6. FM0 Data Encoding Figure 7. MMS2 Data Encoding Figure 8. MMS4 Data Encoding Figure 9. MMS8 Data Encoding non-volatile memory. The register is located at physical address 0x 016 or USER memory address 0x002. writing the Control/Status register word if it is to remain unlocked. Figure 10. Control/Status Register
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 11 of 33 Table 3: Control/Status Word Register Upon power up, WM72016-6‟s control logic reads the control word out of memory and configures itself accordingly. User applications may ch ange the control word as needed providing the register has not been permanently locked. The Control/Status word may be read by the application at any time. Register Locking: The LOCK and PERMALOCK control bits are implemented in a similar manner as locking bits used for Gen2 memory bank locking with the exception that the lock control bits are i ncorporated into the register they are locking. As such, attention needs to be pla ced on how the contents of the Control/Status word are written when the register is not completely unlocked. Bit Mnemonic Function Initial Value 15 LOCK Memory locking of this register. LOCK PERMALOCK DESCRIPTION 0 0 Register unlocked 0 1 Register permanently unlocked 1 0 Register writeable only from the SECURED state 1 1 Register permanently locked
14 PERMALOCK 0
13 RFU Reserved for future use 0
12 RFU Reserved for future use 0
11 RFU Reserved for future use 0
10 RFU Reserved for future use 0
9 RFU Reserved for future use 0
8 RFU Reserved for future use 0
7 BLKWREN Enables use of the custom command BLOCKWRITE. 1 6 BLKSIZ[2] USER memory block size. BLKSIZ[2:0] # words BLKSIZ[2:0] # words 000 1 100 16 001 2 101 32 010 4 110 64 011 8 111 128
5 BLKSIZ[1] 1
4 BLKSIZ[0] 0
3 WRPSTAT Indicates if the Working Stored Address has wrapped. Logic State Description
0 Wrapping has not occurred
1 Wrapping has occurred at least once
2 WRPEN Enables wrapping of the Working Stored Address when it reaches the
top of logical memory. Logic State Description
0 DISABLE memory wrapping
1 ENABLE memory wrapping.
1 AUTOLOCK Enable Automatic Locking of all user memory between the start of USER
memory and the Working Stored Address register. Logic State Description
0 Auto-lock DISABLED
1 Auto-lock ENABLED
0 AUTOINCR Enable the Working Stored Address word to Auto-Increment when
performing an unaddressed write cycle. Logic State Description
0 DISABLE auto-increment of stored address register
1 ENABLE auto-increment of stored address register
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 12 of 33 Table 4: Control/Status Word Locking LOCK PERMA- LOCK 0 0 Register unlocked. All control bits, including the LOCK and PERMALOCK bits can be written to from the OPEN or SECURED states. 0 1 Register permanently unlocked. All control bits can be written from the OPEN or SECURED states. The LOCK and PERMALOCK bits must be set to logic values 0 and 1 respectively when writing the Control/Status word. 1 0 Register locked. All control bits can be written to only from the SECURED state. The register cannot be written to in the OPEN state. The LOCK and PERMALOCK bits must be set to logic values 1 and 0 respectively when writing the Control/Status word. 1 1 Register permanently locked. The register cannot be written in any circumstance. Block Write Enable : The BLKWREN control bit enables usage of the WM72016-6 custom command BLOCKWRITE. The BLKWREN parameter is internally updated during power -on WM72016-6 initialization. In the event the host application toggles the state of BLKWREN either through the Gen2 or serial interfaces, a WM72016-6 power cycle is required to reflect the change. Block Size: The 3 BLKSIZ[2:0] control bits adjust the USER memory block sizes as shown in Table 5. This provides a host application the ultimate flexibility in determining a balance between the USER memory requirements and th e granularity of the number of USER memory words per block. The larger the granularity of the block size, the greater amount of available USER memory. The effect of the block size on available USER memory is shown in Table 1. The total number of USER me mory words available as a function of the block size is shown in Table 5 below. It is of utmost importance that the 3 -bit block size is not modified once set, which would otherwise result in corruption of block permalocking status bits. Table 5: Available USER Memory Memory BLKSIZ Words/Block Free USER Memory (words) 16k 000 1 931 16k 001 2 963 16k 010 4 979 16k 011 8 987 16k 100 16 991 16k 101 32 993 16k 110 64 993 16k 111 128 993 Wrap Status: The WRPSTAT status bit is asserted to a logic one when the following conditions are true: (a) WRPEN=1, AUTOINCR=1 and AUTOLOCK=0, (b) The contents of the Working Stored Address register address the last USER memory location, and (c) An unaddressed WRITE command is received. Note: The WRPSTAT can be cleared by the RFID interrogator by writing a logic zero to the WRPSTAT bit. Wrap Enable: Asserting the WRPEN control bit to a logic one enables the USER memory wrapping feature. The wrap enable feature allows the stored address pointer to wrap back to the factory-set initial stored address value of 0x006. In this manner, the WM72016-6 memory acts as a circular buffer. Clearing the WRPEN control bit disables wrapping resulting in a write-once memory. In this case, when the Working Stored Address reaches the end of user memory, no additional unaddressed write cycles will be possible. The WRPEN and AUTOLOCK control bits are mutually exclusive – only one of the two control bits may be asserted at any given time. Auto Lock Enable: Asserting the AUTOLOCK control bit to a logi c one enables memory locking of the USER memory span between the start of USER memory and the Working Stored Address. The AUTOLOCK and
time. The automatic locking feature can only be used when AUTOINCR is asserted to a logic one. interrogator to determine where free USER memory is located and manipulating the memory pointer itself. Control/Status register is asserted to a logic one and an unaddressed write command is received. Figure 11. Working Stored Address Register 15 LOCK Memory locking of this register.
10 INITEN When asserted to a logic ‘1’, sets the contents of the Initial Stored
9 through 0 written to this register using a Gen2 write instruction.
Figure 17. Initial Stored Address Example – Block Size = 128 words/block The Initial Stored Address is factory-initialized with a value of 0x0006 (USER memory bank address 0x006). descriptions of these commands.
second set of 8 CLK cycles. The write cycle is terminated by clearing the CS signal. the entire data word, after which it clears the CS to a logic zero to terminate the read cycle. The syntax of the instruction word is detailed in Table 8. cycle. RW is cleared to logic „0‟ for write cycle. Opcode OP 14..10 Instruction opcode. Address A 9..0 MaxArias physical memory address. then tri-states the D0 and D1 signals while receiving data from MaxArias memory. The opcode (OP) parameter is a 5-bit value that can take on the following values shown in Table 9. NORM 11001 Normal read/write instruction. INTEND 11101 Interrupt end instruction.
- NORM – normal opcode for all read/write instructions, and
- INTEND – DSPI serial port control register opcode.
Table 1. In the event that memory arbitration is required between the RFID and serial interfaces, the RFID memory required to store critical parameters for the operation of the device are not altered.
improving bandwidth requirements. Figure 22. DSPI Write Cycle Detail secondary DSPI serial interface. command is received to terminate the interrupt and return control back to the RFID interface. The WM72016-6 has been power-cycled.
XOR of the two memory locations being equal to 0x1234. recommended to use these memory locations as part of the standard USER memory bank. Figure 23. Gen2 Interrupt Generation Select (CS) pin is an input and when it‟s released via a INTEND opcode, the CS pin then becomes an output.
Figure 24. Suggested Implementation for Interfacing an MCU to the WM72016-6
- RF performance of WM72016-6 is heavily dependent on matching impedance on the antenna port ANT+/.
- External voltage VDDR_EXT may be applied to Vddraw to externally power the WM72016 -6.
VDDR_EXT must comply with specifications given in the DC Characteristics of this datasheet.
- In some cases, additional bus termination may be required on the WM72016 -6 end of the DSPI serial bus.
voltages beyond specifications causing unpredictable performance characteristics.
- When powering the WM72016 -6 locally (from Vddraw pi n, not via RF power), the user must use an
I/O pin to power the WM72016-6 and power down the device off after accesses have completed. UHF RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.2.0. persistence and will always return to state „A‟ upon a power cycle. be left in a continuously powered state.
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 24 of 33 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Symbol Description Ratings Notes VDDR, VDDRAW Power Supply Voltage with respect to ANT- -1.0V to +4.5V VIN Voltage on any serial port pin with respect to ANT- -1.0V to +4.5V and VIN < VDD+1.0V TSTG Storage Temperature -55 C to + 125 C TOP Operating Temperature -40oC to +85oC TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD (ANT+, ANT-) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 500V 1kV 50V VESD (All other pins) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 1.5kV 1.5kV 200V ME Memory Endurance: Read or Write or Erase 1x1014 1 RFexp RF Exposure +10dBm (800 ~ 1000 MHz) Package Moisture Sensitivity Level MSL-1 1. A degradation in memory endurance may occur for VDDR_EXT levels beyond the maximum specification. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. RF Operating Characteristics (TA = -40 C to + 85 C unless otherwise specified) Symbol Parameter Min Typ Max Units Notes SR Read Sensitivity -6 dBm 3 SW Write Sensitivity -6 dBm 3 Fr Max Sustainable Read Rate @ SR 640 Kbits/s 1 Fw Max Sustainable Write Rate @ Sw 160 Kbits/s 1 tST Power-on time 1.0 1.5 ms ZIN Input Impedance @ fIN=915MHz 63 – j199 Ohms 2 Note: 1. Actual read & write speeds are constrained by the EPC Class 1 Gen2 data communication standard. 2. ZIN is measured at SR/SW. 3. Typical behavior at room temperature only
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 26 of 33 DSPI Serial Port DC Characteristics (TA = -40 C to + 85 C unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDDR, VDDRAW Power Supply Pins 2.1 2.5 3.0 V 1 IDD Power Supply Operating Current 15 25 µA VIL Input Low Voltage -0.3 0.3 VDDR V VIH Input High Voltage 0.7 VDDR VDDR+0.3 V VOH1 Output High Voltage (IOH = -0.5mA, VDD ≥ 2.7V) 2.4 - V VOH2 Output High Voltage (IOH = -100µA) VDDR – 0.2 - V VOL1 Output Low Voltage (IOL= 1mA, VDD ≥ 2.7V) - 0.4 V VOL2 Output Low Voltage (IOL= 150µA) - 0.2 V NOTES: 1. Measured at the pin. DSPI Serial Port AC Characteristics (TA = -40 C to + 85 C, VDD = 2.1V to 3.0V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes tPSU VDDR Setup Time 1.5 - ms tPH VDDR Hold Time 0 - ns tCSD Chip Select Setup to Data Valid Time 10 - ns tCSH Chip Select Hold Time 10 - ns tSU Data Setup Time 10 tCLK/2 - 10 ns tHD Data Hold Time 10 - ns tDD Read Data Valid Time 600 ns tCLK Clock Period 1.6 - µs tWD Instruction to Data Word Timing tCLK/2 - tACK Interrupt Acknowledge Setup Time 10 - ns
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 27 of 33 SPECIFICATION & COMPLIANCE SUMMARY Refer to EPCTM Radio-Frequency Identity Protocols Class -1 Generation -2 UHF RFID Protocol for Communications at 860MHz-960MHz Version 1.2.0 for all critical RFID specifications. Link to specifications page: http://www.epcglobalus.org/Standards/EPCglobalSpecifications/tabid/335/Default.aspx
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 28 of 33 MECHANICAL DRAWINGS 8-pin UDFN (3.0 mm x 3.0 mm body, 0.65 mm pad pitch) Pin 1 3.0 ±0.1 3.0 ±0.1 0.55 ±0.05 0.25 ±0.05 0.65
0.152 BSC
0.0 - 0.05
1.95 REF
0.30 ±0.05 Pin 1 ID Exposed metal pad should be left floating. Note: All dimensions in millimeters. Care must be taken to ensure PCB traces and vias are not placed within the exposed metal pad area.
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 31 of 33
ORDERING INFORMATION
Note: Contact Ramtron for other ordering options, i.e. bumped die. Product Description Delivery & MOQ WM72016-6-DGTR 8-pin UDFN with 16Kb memory and DSPI serial interface Tape & Reel – 3000 units
WM72016-6 – Secure F-RAM with Gen-2 RFID and Serial Port Document Number: 001-86227 Rev. ** Page 32 of 33
REVISION HISTORY
0.1 12/12/2008 Initial release. 0.2 2/11/2009 Order information and package update 0.3 3/7/2010 Documentation updates 1.0 3/12/2010 Changed to Preliminary status. 1.1 8/23/2010 Changed read/write sensitivity specs. 1.2 9/7/2010 Changed input impedance and the test frequency. 1.3 4/11/2011 Documentation updates and clarifications. 1.4 5/25/2011 Modified Memory Map table on p. 5 (changed line entries for DSPI address 0x3FA – 0x3FB). 1.5 6/4/2012 Added interrupt generation text, included suggested footprint for the IC and modified portions of the formatting 3.0 7/10/2012 Updated content and made into production version Document History Document Title: WM72016-6 16Kbit Secure F-RAM Memory with Gen-2 RFID Access & Serial Port Direct Memory Access Document Number: 001-86227 Revision ECN Orig. of Change Submission Date Description of Change ** 3912936 GVCH 02/25/2013 New Spec
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