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Document overview
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- PDF pages: 19
Technical content
Datasheet sections
- 4.1 Programming
- 4.2 Simultaneous Die Operation
- 4.3 Sequential Reads
- 4.4 Sector/Bulk Erase
- 4.5 Status Registers
- 4.6 Configuration Register
- 4.7 Bank Address Register
- 4.8 Security and DDR Registers
- 4.9 Block Protection
- 10.1 DDR AC Characteristics
- 10.2 Capacitance Characteristics
- 11.1 Valid Combinations — Standard
- 11.2 Valid Combinations — Automotive Grade /
- 12.1 Cypress Flash Memory Road map
- 12.2 Links to Software
- 12.3 Links to Application Notes
- 13.1 SOIC 16 Lead, 300-mil Body Width
Features
CMOS 3.0V Core Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate (DDR) option – Extended Addressing: 32-bit address – Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families – Multi I/O Command set and footprint compatible with S25FL-P SPI family READ Commands – Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR – AutoBoot – power up or reset and execute a Normal or Quad read command automatically at a preselected address – Common Flash Interface (CFI) data for configuration information Programming (1.5 Mbytes/s) – 512-byte Page Programming buffer – Quad-Input Page Programming (QPP) for slow clock systems Erase (0.5 Mbytes/s) – Uniform 256-kbyte sectors Cycling Endurance – 100,000 Program-Erase Cycles, minimum Data Retention – 20 Year Data Retention, minimum Security Features One Time Program (OTP) array of 2048 bytes Block Protection – Status Register bits to control protection against program or erase of a contiguous range of sectors. – Hardware and software control options – Advanced Sector Protection (ASP) – Individual sector protection controlled by boot code or password Cypress ® 65 nm MirrorBit® Technology with Eclipse Architecture Core Supply Voltage: 2.7V to 3.6V I/O Supply Voltage: 1.65V to 3.6V Temperature Range / Grade: – Industrial (40 °C to +85 °C) – Industrial Plus (40 °C to +105 °C) – Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C) – Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C) – Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C) Packages (all Pb-free) – 16-lead SOIC (300 mils) – BGA-24, 8 6 mm –5 5 ball (ZSA024) footprint General Description This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed specifications, refer to the discrete die datasheet provided in the Affected Documents/Related Documents table. Affected Documents/Related Documents Document Title Publication Number S25FL512S 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory Datasheet 001-98284
Document Number: 001-98295 Rev. *M Page 3 of 19 S70FL01GS 1. Block Diagram SI/IO0 SI/IO0 WP#/IO2 WP#/IO2 SO/IO1 HOLD#/IO3 HOLD#/IO3 VSS VSSSCK SCK CS#1 CS# VCC VCC SI/IO0 WP#/IO2 HOLD#/IO3 VSSSCK CS#2 CS# VCC SO/IO1 SO/IO1 FL512S Flash Memory FL512S Flash Memory
Figure 1. 16-Pin Plastic Small Outline Package (SO) Figure 2. 24-Ball BGA, 5 x 5 Ball Footprint (ZSA024), Top View
- V IO is not supported in the S70FL01GS device and is RFU. Refer to Section 7. for more details.
9 WP#/IO2
Table 2. Signal List CS1# Input Chip Select. FL512S #1. CS2# Input Chip Select. FL512S #2. SI / IO0 I/O Serial Input for single bit data commands or IO0 for Dual or Quad commands. SO / IO1 I/O Serial Output for single bit data commands. IO1 for Dual or Quad commands. resistor and may be left unconnected in the host system if not used for Quad commands. VCC Supply Core Power Supply. Section 7. for more details. enhanced features in compatible footprint devices. connect any host system signal to this connection.
Document Number: 001-98295 Rev. *M Page 6 of 19 S70FL01GS 4. Device Operations
4.1 Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
4.2 Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
4.3 Sequential Reads
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the user desires to sequentially read across the two die, data must be read out of the first die via CS1# and then read out of the second die via CS2#.
4.4 Sector/Bulk Erase
A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via a single command is not supported due to the nature of the dual die stack. A Bulk Erase command must be issued for each die.
4.5 Status Registers
Each Flash die of the dual die stack is managed by its own Status Registers. Reads and updates to the Status Registers must be managed separately. It is recommended that Status Register control bit settings of each die are kept identical to maintain consistency when switching between die.
4.6 Configuration Register
Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the Configuration Register control bits must be managed separately. It is recommended that Configuration Register control bit settings of each die are kept identical to maintain consistency when switching between die.
4.7 Bank Address Register
It is recommended that the Bank Address Register bit settings of each die are kept identical to maintain consistency when switching between die.
4.8 Security and DDR Registers
It is recommended that the bit settings for ASP Register, Password Register, PPB Lock Register, PPB Access Register, DYB Access Register, and DDR Data Learning Register in each die are kept identical to maintain consistency when switching between die.
4.9 Block Protection
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and BPNV bits of each die must be managed separately. By default, each die is configured to be protected starting at the top (highest address) of each array, but no address range is protected. It is recommended that the Block Protection settings of each die are kept identical to maintain consistency when switching between die. In addition, any update to the FREEZE bit must be managed separately for each die. If the FREEZE bit is set to a logic 1, it cannot be cleared to a logic 0 until a power-on-reset is executed on each die that has the FREEZE bit set to 1.
- Read Identification (RDID)
identification data as the FL512S die, with the exception of the CFI data at byte 27h, as shown in Table 3.
- Versatile I/O Power Supply (V IO)
supported, and pin 14 and ball E4 are RFU (Reserved for Future Use) in the standard configuration of the S70FL01GS device. Contact your local sales office to confirm availability with the VIO feature enabled. Table 3. Product Group CFI Device Geometry Definition
This section summarizes the DC Characteristics of the device.
- Typical values are at T AI = 25°C and VCC = 3V.
- Output switching current is not included.
- Bulk Erase current is for both die erasing simultaneously.
Table 4. DC Characteristics
- Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
- Regulated V CC range (3.0 - 3.6V) and CL = 30 pF.
- Regulated V CC range (3.0 - 3.6V) and CL = 15 pF.
- ±10% duty cycle is supported for frequencies 50 MHz.
- Maximum value only applies during Program/Erase Suspend/Resume commands.
- When switching between die, a minimum time of t CS must be kept between the rising edge of one chip select and the falling edge of the other for operations and data
Table 6. SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V)
10.1 DDR AC Characteristics
- Regulated V CC range (3.0 - 3.6V) and CL =15 pF.
- Maximum value only applies during Program/Erase Suspend/Resume commands.
10.2 Capacitance Characteristics
- For more information on capacitance, please consult the IBIS models.
Table 7. DDR AC Characteristics 66 MHz and 80 MHz Operation
66 MHz 80 MHz
Table 8. Capacitance
Document Number: 001-98295 Rev. *M Page 12 of 19 S70FL01GS 11. Ordering Information The ordering part number is formed by a valid combination of the following: Notes: 1. EHPLC = Enhanced High Performance Latency Code table. 2. Uniform 256-kB sectors = All sectors are uniform 256-kB with a 512B programming buffer. S70FL 01G S AG M F I 0 1 1 Packing Type (Note 1) 0 = Tray 1 = Tube 3 = 13” Tape and Reel Model Number (Sector Type) 1 = Uniform 256-kB sectors Model Number (Latency Type, Package Details, RESET# support) 0 = EHPLC, SO footprint C = EHPLC, 5 x 5 ball BGA footprint with RESET# Temperature Range / Grade I = Industrial (-40°C to + 85°C) V = Industrial Plus (-40°C to +105°C) A = Automotive, AEC-Q100 Grade 3 (-40°C to +85°C) B = Automotive, AEC-Q100 Grade 2 (-40°C to +105°C) M = Automotive, AEC-Q100 Grade 1(-40°C to +125°C) Package Materials F = Lead (Pb)-free H = Low-Halogen, Lead (Pb)-free Package Type B = 24-ball BGA 8 x 6 mm package, 1.00 mm pitch M = 16-pin SO package Speed AG = 133 MHz DP = 66 MHz DDR DS = 80 MHz DDR Device Technology S = 65 nm MirrorBit Process Technology Density 01G = 1 Gbit Device Family S70FL Cypress Stacked Memory 3.0V-Only, Serial Peripheral Interface (SPI) Flash Memory
11.1 Valid Combinations — Standard
Table 9 lists the valid combinations configurations planned to be supported in volume for this device.
- Package Marking omits the leading “S70” and package type.
11.2 Valid Combinations — Automotive Grade / AEC-Q100
combinations and to check on newly released combinations. Production Part Approval Process (PPAP) support is only provided for AEC-Q100 grade products.
- Package Marking omits the leading “S70” and package type.
Table 9. S70FL01GS Valid Combinations — Standard Table 10. S70FL01GS Valid Combinations — Automotive Grade / AEC-Q100
Document Number: 001-98295 Rev. *M Page 14 of 19 S70FL01GS 12. Other Resources
12.1 Cypress Flash Memory Roadmap
www.cypress.com/product-roadmaps/cypress-flash-memory-roadmap
12.2 Links to Software
www.cypress.com/software-and-drivers-cypress-flash-memory
12.3 Links to Application Notes
www.cypress.com/appnotes
Document Number: 001-98295 Rev. *M Page 15 of 19 S70FL01GS 13. Physical Diagram
13.1 SOIC 16 Lead, 300-mil Body Width
REVSPEC NO.THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION. CYPRESS TITLE SCALE : Company Confidential PACKAGE CODE(S) DRAWN BY APPROVED BY DATE DATE 0.33 C
0.25 M DCA - B
0.20 C A-B
0.10 C 0.10 C
0.10 C D
- DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE. 1. ALL DIMENSIONS ARE IN MILLIMETERS. NOTES: D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H. FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD 4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS 5. DATUMS A AND B TO BE DETERMINED AT DATUM H. 6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED 7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE 8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR LOWER RADIUS OF THE LEAD FOOT. IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 9. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, THEN A PIN 1 10. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE h D N e b c E A 0.75
10.30 BSC
1.27 BSC
0.30 0.33 0.25 0.20
7.50 BSC
0.10 0.31 0.51 2.652.35 A2 2.05 2.55 b1 0.27 0.48 0.300.20c1 0.40L 1.27
1.40 REF
0.25 BSC
0 5° 15° 0 0° 2 - DIMENSIONS SYMBOL MIN. NOM. MAX. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY 0.25 mm FROM THE LEAD TIP. PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT THE PLASTIC BODY. PACKAGE LENGTH. SEATING PLANE. SO3016 KOTA BESY 24-OCT-16 24-OCT-16 *A002-15547 PACKAGE OUTLINE, 16 LEAD SOIC 12TO FIT 10.30X7.50X2.65 MM SO3016/SL3016/SS3016 SL3016 SS3016
Document Number: 001-98295 Rev. *M Page 16 of 19 S70FL01GS 13.2 24-Ball BGA 8 x 6 mm (ZSA024) SHEET OF REVSPEC NO.THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION. CYPRESS TITLE SCALE : Company Confidential PACKAGE CODE(S) DRAWN BY APPROVED BY DATE DATE METALLIZED MARK INDENTATION OR OTHER MEANS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. e REPRESENTS THE SOLDER BALL GRID PITCH. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.8. ALL DIMENSIONS ARE IN MILLIMETERS. PARALLEL TO DATUM C. NOTES: 0.35 eD eE ME MD b n
1.00 BSC
0.00 0.40 MIN. 0.20 D E SYMBOL A
8.00 BSC
4.00 BSC
6.00 BSC
NOM. 0.45 1.20 MAX. DIMENSIONS SE SD 0.00 "SD" = eD/2 AND "SE" = eE/2. "SD" OR "SE" = 0. MD X ME. ZSA024 KOTA SYLI 5-JUL-16 5-JUL-16 **002-15078 8.0X6.0X1.2 MM ZSA024 PACKAGE OUTLINE, 24 BALL FBGA 12TO FIT
Document Number: 001-98295 Rev. *M Page 17 of 19 S70FL01GS 14. Revision History Document Title: S70FL01GS, 1 Gbit (128 Mbyte) 3.0V SPI Flash Document Number: 001-98295 Rev. ECN No. Orig. of Change Submission Date Description of Change ** BWHA 11/06/2012 Initial release *A BWHA 04/25/2013 Global: Datasheet designation updated from Advance Information to Preliminary DC Characteristics: DC Characteristics table: changed Max value of ILI, ILO, ICC1, and ISB BWHA 05/16/2013 SOIC 16 Physical Diagram: Updated package nomenclature from S03016 to SL3016 *C BWHA 08/22/2013 Valid Combinations: Valid Combinations table: added MFV DC Characteristics: DC Characteristics table: added ISB (Automotive) *D BWHA 11/08/2013 Global: Datasheet designation updated from Preliminary to Full Production *E BWHA 03/19/2014 Features: Packages (all Pb-free): added BGA-24, 8 x 6 mm Connections Diagrams: Added figure: 24-Ball BGA, 5 x 5 Ball Footprint (FAB024), Top View Ordering Information: Added options to: Model Number, Package Materials, Package Type, and Speed Valid Combinations: Added option to S70FL01GS Valid Combinations Table SDR AC Characteristics: SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V) table: updated tv Min DDR AC Characteristics:Updated DDR AC Characteristics 66 MHz Operation table Capacitance Characteristics: Capacitance table: updated Max values and removed note BWHA 11/07/2014 Valid Combinations: Added DP Speed Option for BGA 5x5 package *G BWHA 04/21/2015 Valid Combinations: Added BHV option *H 4871631 BWHA 08/24/2015 Updated to Cypress template. Changed Automotive Temperature Range to Industrial Plus Temperature Range in Features and Section 4. *I 5123878 BWHA 02/03/2016 Updated General Description. *J 5536564 BWHA 12/02/2016 Updated Features on page 1: Added Extended and Automotive Grade temperatures. Updated DDR AC Characteristics 66 MHz and 80 MHz Operation on page 11 table: Corrected tHO Min value, tCSH and tSU Max value. Ordering Information on page 12: Added Extended and Automotive Grade. Added Other Resources on page 14. *K 5612027 ECAO 01/17/2017 Added ICC1 value for Quad DDR @ 80 MHz in Table 4, DC Characteristics on page 8 Updated ICC5 value in Table 4, DC Characteristics on page 8 Updated DDR AC Characteristics 66 MHz and 80 MHz Operation on page 11 Removed Extended (-40°C to +125°C) temperature option in Ordering Infor- mation Updated Physical Diagram: Updated package name and drawing from SL3016 to SS3016. Updated package name and drawing from FAB024 to ZSA024.
Document Number: 001-98295 Rev. *M Page 18 of 19 S70FL01GS *L 5669602 ECAO 04/05/2017 Updated Figure 2, 24-Ball BGA, 5 x 5 Ball Footprint (ZSA024), Top View on page 4. Removed SS3016 from Section 13.1, SOIC 16 Lead, 300-mil Body Width on page 15. Removed CS# from Table 2, Signal List on page 5. Updated tSU in Table 6, SDR AC Characteristics (Single Die Package, VCC = 2.7V to 3.6V) on page 10. Updated Cypress logo. Updated Sales page. *M 5783913 ECAO 06/23/2017 Changed OTP total space in Security Features. Updated I SB values in Table 4. Document Title: S70FL01GS, 1 Gbit (128 Mbyte) 3.0V SPI Flash Document Number: 001-98295 Rev. ECN No. Orig. of Change Submission Date Description of Change
Document Number: 001-98295 Rev. *M Revised June 23, 2017 Page 19 of 19 © Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subs idiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IM PLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. Cypress is not liable, in whol e or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. S70FL01GS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless PSoC® Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support