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Technical content
Datasheet sections
Features
■ Universal serial bus (USB) integration ❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0 ❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0 ❐ High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement Version 2.0 ❐ Thirty-two physical endpoints ❐ Support for battery charging Spec 1.1 and accessory charger adaptor (ACA) detection ■ General Programmable Interface (GPIF™ II) ❐ Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices ❐ 8-, 16-, and 32-bit data bus ❐ As many as16 configurable control signals ■ Fully accessible 32-bit CPU ❐ ARM926EJ core with 200-MHz operation ❐ 512-KB or 256-KB embedded SRAM ■ Additional connectivity to the following peripherals ❐ I2C master controller at 1 MHz ❐ I2S master (transmitter only) at sampling frequencies of 32 kHz, 44.1 kHz, and 48 kHz ❐ UART support of up to 4 Mbps ❐ SPI master at 33 MHz ■ Selectable clock input frequencies ❐ 19.2, 26, 38.4, and 52 MHz ❐ 19.2-MHz crystal input support ■ Ultra low-power in core power-down mode ❐ Less than 60 µA with VBATT on and 20 µA with VBATT off ■ Independent power domains for core and I/O ❐ Core operation at 1.2 V ❐ I2S, UART, and SPI operation at 1.8 to 3.3 V ❐ I2C operation at 1.2 V ■ Package option ❐ 121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA) ❐ 131-ball, 4.7- × 5.1-mm, 0.4-mm pitch wafer-level chip scale package (WLCSP) ■ EZ-USB® software and development kit (DVK) for easy code development
Applications
■ Digital video camcorders ■ Digital still cameras ■ Printers ■ Scanners ■ Video capture cards ■ Test and measurement equipment ■ Surveillance cameras ■ Personal navigation devices ■ Medical imaging devices ■ Video IP phones ■ Portable media players ■ Industrial cameras
Document Number: 001-52136 Rev. *N Page 2 of 45 EPsGPIF™ II HS/FS Peripheral SS Peripheral HS/FS/LS OTG Host ARM926EJ -S JTAG UART SPI I2S Embedded SRAm (512 kB/
256 KB)
EZ-Dtect™ CTL[12:0] INT# RESET # TDI TDO TRST# TMS TCK DQ[31:0]/ DQ[15:0] PMODE[2:0] OTG_ID SSRX - SSRX + SSTX - SSTX + FSLC[0] FSLC[1] FSLC[2] CLKIN CLKIN_32 XTALIN XTALOUT I2C_SCL I2C_SDA TX RX CTS RTS I2S_CLK I2S_SD I2S_WS I2S_MSCLK SSN SCK MISO MOSI I2C Logic Block Diagram
peripheral controller, providing integrated and flexible features. data multiplexed interfaces, and parallel ATA. from GPIF II to the USB interface. function as an OTG Host to MSC as well as HID-class devices. accelerating time to market. diagram when FX3 functions as the main processor. Figure 1. EZ-USB FX3 as a Coprocessor
- Assuming that GPIF II is configured for a 32-bit data bus (available with certain part numbers; see Ordering Information on page 41), synchronous interface operating
at 100 MHz. This number also includes protocol overheads.
identities of multiple distinct USB devices. ReNumeration, happens instantly when the device is plugged in. FX3 supports USB Charger and accessory detection (EZ-Dtect). support to detect the resistance values on the ID pin. Table 7 for the operating range of VBUS and VBATT. Figure 4. System Diagram with OVP Device For VBUS In the Carkit UART mode, the output signaling voltage is 3.3 V. shown in Figure 5 on page 7. In this mode, FX3 supports a rate of up to 9600 bps.
CPU-core's on-chip-debug circuitry. can be used for the FX3 application development. UART interface is available on GPIO[53] to GPIO[56]. The UART interface of FX3 supports full-duplex communication. It includes the signals noted in Table 1. output signal, when it is ready to receive data. connected to the I2C interface, as a selectable boot option. voltage than the other serial interfaces. feature to enable slower devices to exercise flow control. resistors. The pull-up resistors must be connected to VIO5. FX3 has an I2S port to support external audio codec devices. port. The maximum operation frequency is 33 MHz. supports transaction sizes ranging from 4 bits to 32 bits. Table 1. UART Interface Signals
tristated during a hard reset. does not need to be reloaded following a CPU Reset. ■ Whole Device Reset – This reset is identical to Hard Reset. can be left unconnected if they are not used. clock frequencies supported are 19.2, 26, 38.4, and 52 MHz. 19.2-MHz (±100 ppm) crystal (when the crystal option is used). configuration options are shown in Table 3. ments specified in Table 4 on page 10. clock multiply option depending on the input frequency. Table 2. FX3 Booting Options Table 3. Crystal/Clock Frequency Selection
supplied from an external source on a dedicated FX3 pin. The firmware can disable the watchdog timer. digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V.
- AVDD: This is the 1.2-V supply for the PLL, crystal oscilla- tor, and other core analog circuits U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt- ages for the USB 3.0 interface. ■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply for the USB I/O and analog circuits. This supply powers the USB transceiver through FX3's internal voltage regulator. VBATT is internally regulated to 3.3 V. Power Modes FX3 supports the following power modes: ■ Normal mode: This is the full-functional operating mode. The internal CPU clock and the internal PLLs are enabled in this mode. ❐ Normal operating power consumption does not exceed the sum of ICC Core max and ICC USB max (see Table 7 for current consumption specifications). ❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be turned off when the corresponding interface is not in use. VIO1 cannot be turned off at any time if the GPIF II interface is used in the application. ■ Low-power modes (see Table 6 on page 11): ❐ Suspend mode with USB 3.0 PHY enabled (L1) ❐ Suspend mode with USB 3.0 PHY disabled (L2) ❐ Standby mode (L3) ❐ Core power-down mode (L4)
Table 4. FX3 Input Clock Specifications Table 5. 32-kHz Clock Input Requirements
Table 6. Entry and Exit Methods for Low-Power Modes
■ ARM926EJ-S core is powered down. Table 6. Entry and Exit Methods for Low-Power Modes (continued)
Configuration options are availa ble for specific usage models. Contact Cypress Applications or Marketing for details. configured separately for each interface. (except CTL[15]) on the GPIF II interface can be used as GPIOs. specifications and continue to function as expected. based on IEC61000-4-2 level 4C. ESD events up to the levels stated in this section. ±2.2-KV HBM internal ESD protection. Figure 7. FX3 121-ball BGA Ball Map (Top View)
Figure 8. FX3 131-Ball CSP Ball Map (Bottom View)
Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width)
- When GPIF II is configured for the 32-bit da ta bus width, GPIO[50]-GPIO[52] may be configured as GPIOs or I2S, and GPIO[53] to GPIO[56] may be configured as
GPIOs or UART interface only.
Table 7. CYUSB3012 and CYUSB3014 Pin List (GPIF II with 32-bit Data Bus Width) (continued)
Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width)
Table 8. CYUSB3011 and CYUSB3013 Pin List (GPIF II with 16-bit Data Bus Width) (continued)
Document Number: 001-52136 Rev. *N Page 22 of 45 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. Ambient temperature with Ambient temperature with Supply voltage to ground potential DC voltage applied to (VCC is the corresponding I/O voltage) Static discharge voltage ESD protection levels: ■ ± 2.2-KV HBM based on JESD22-A114 ■ Additional ESD protection levels on D+, D–, and GND pins, and serial peripheral pins ■ ± 6-KV contact discharge, ± 8-KV air gap discharge based on IEC61000-4-2 level 3A, ± 8-KV contact discharge, and ± 15-KV air gap discharge based on IEC61000-4-2 level 4C Maximum output short-circuit current Operating Conditions TA (ambient temperature under bias) V DD, AVDDQ, U3TXVDDQ, U3RXVDDQ V VIO1, VIO2, VIO3, VIO4, CVDDQ V DC Specifications Parameter Description Min Max Units Notes VDD Core voltage supply 1.15 1.25 V 1.2-V typical AVDD Analog voltage supply 1.15 1.25 V 1.2-V typical VBATT USB voltage supply 3.2 6 V 3.7-V typical VBUS USB voltage supply 4.0 6 V 5-V typical required on this power supply. required on this power supply. CVDDQ Clock voltage supply 1.7 3.6 V 1.8-, 3.3-V typical VIH1 Input HIGH voltage 1 0.625 × VCC VCC + 0.3 V For 2.0 V VCC 3.6 V (except USB port).VCC is the corresponding I/O voltage supply. VIH2 Input HIGH voltage 2 VCC – 0.4 VCC + 0.3 V For 1.7 V VCC 2.0 V (except USB port).VCC is the corre- sponding I/O voltage supply. VIL Input LOW voltage –0.3 0.25 × VCC V VCC is the corresponding I/O voltage supply. VOH Output HIGH voltage 0.9 × VCC – V I OH (max) = –100 µA tested at quarter drive strength. VCC is the corresponding I/O voltage supply.
Document Number: 001-52136 Rev. *N Page 23 of 45 VOL Output LOW voltage – 0.1 × VCC V I OL (min) = +100 µA tested at quarter drive strength. VCC is the corresponding I/O voltage supply. I IX Input leakage current for all pins except SSTXP/SSXM/SSRXP/SSRXM –1 1 µA All I/O signals held at V DDQ (For I/Os with a pull-up or pull-down resistor connected, the leakage current increases by VDDQ/Rpu or VDDQ/RPD IOZ Output High-Z leakage current for all pins except SSTXP/ SSXM/ SSRXP/SSRXM –1 1 µA All I/O signals held at V DDQ ICC Core Core and analog voltage operating current – 200 mA Total current through A VDD, VDD ICC USB USB voltage supply operating current – 60 mA ISB1 Total suspend current during suspend mode with USB 3.0 PHY enabled (L1) – – mA Core current: 1.5 mA I/O current: 20 µA USB current: 2 mA For typical PVT (typical silicon, all power supplies at their respective nominal levels at 25 °C.) I SB2 Total suspend current during suspend mode with USB 3.0 PHY disabled (L2) – – mA Core current: 250 µA I/O current: 20 µA USB current: 1.2 mA For typical PVT (Typical silicon, all power supplies at their respective nominal levels at 25 °C.) I SB3 Total standby current during standby mode (L3) – – µA Core current: 60 µA I/O current: 20 µA USB current: 40 µA For typical PVT (typical silicon, all power supplies at their respective nominal levels at 25 °C.) I SB4 Total standby current during core power-down mode (L4) – – µA Core current: 0 µA I/O current: 20 µA USB current: 40 µA For typical PVT (typical silicon, all power supplies at their respective nominal levels at 25 °C.) V RAMP Voltage ramp rate on core and I/O supplies 0.2 50 V/ms Voltage ramp must be monotonic VN Noise level permitted on VDD and I/O supplies – 100 mV Max p-p noise level permitted on all supplies except AVDD VN_AVDD Noise level permitted on AVDD supply – 20 mV Max p-p noise level permitted on A VDD DC Specifications (continued) Parameter Description Min Max Units Notes
Figure 9. GPIF II Timing in Synchronous Mode Table 9. GPIF II Timing Parameters in Synchronous Mode [4]
- All parameters guaranteed by design and validated through characterization.
Table 10. GPIF II Timing in Asynchronous Mode[5, 6] latches are always close at the deasserting edge. latches always close at the deasserting edge. (DLE) to latch the DQ inputs in DDR mode. (DLE) to latch the DQ inputs in DDR mode. update whose data was already established.
- All parameters guaranteed by design and validated through characterization.
- "alpha" output corresponds to "e arly output" and "beta" corresponds to "delayed output". Please refer to the GPIFII Designer Tool for the use of these outputs.
function is to drive the data bus. The same sequence of events is shown for a burst read. data value is placed on the data bus. Figure 12. Synchronous Slave FIFO Read Mode
be driven as shown in Figure 13 on page 28. dedicated thread or the current thread that is addressed. Figure 13. Synchronous Slave FIFO Write Mode
Document Number: 001-52136 Rev. *N Page 29 of 45 Asynchronous Slave FIFO Read Sequence
Description
■ FIFO address is stable and the SLCS# signal is asserted. ■ SLOE# is asserted. This results in driving the data bus. ■ SLRD # is asserted. ■ Data from the FIFO is driven after assertion of SLRD#. This data is valid after a propagation delay of tRDO from the falling edge of SLRD#. ■ FIFO pointer is incremented on deassertion of SLRD# In Figure 14, data N is the first valid data read from the FIFO. For data to appear on the data bus during the read cycle, SLOE# must be in an asserted state. SLRD# and SLOE# can also be tied. The same sequence of events is also shown for a burst read. Note In the burst read mode, during SLOE# assertion, the data bus is in a driven state (data is driven from a previously addressed FIFO). After assertion of SLRD# data from the FIFO is driven on the data bus (SLOE# must also be asserted). The FIFO pointer is incremented after deassertion of SLRD#. Table 11. Synchronous Slave FIFO Parameters[7]
- All parameters guaranteed by design and validated through characterization.
Document Number: 001-52136 Rev. *N Page 30 of 45 Figure 14. Asynchronous Slave FIFO Read Mode ■ FIFO address is driven and SLCS# is asserted ■ SLWR# is asserted. SLCS# must be asserted with SLWR# or before SLWR# is asserted ■ Data must be present on the tWRS bus before the deasserting edge of SLWR# ■ Deassertion of SLWR# causes the data to be written from the data bus to the FIFO, and then the FIFO pointer is incremented ■ The FIFO flag is updated after the tWFLG from the deasserting edge of SLWR. The same sequence of events is shown for a burst write. Note that in the burst write mode, after SLWR# deassertion, the data is written to the FIFO, and then the FIFO pointer is incre- mented. Short Packet: A short packet can be committed to the USB host by using the PKTEND#. The external device or processor should be designed to assert the PKTEND# along with the last word of data and SLWR# pulse corresponding to the last word. The FIFOADDR lines must be held constant during the PKTEND# assertion. Zero-Length Packet : The external device or processor can signal a zero-length packet (ZLP) to FX3 simply by asserting PKTEND#, without asserting SLWR#. SLCS# and the address must be driven as shown in Figure 15 on page 31. FLAG Usage: The FLAG signals are monitored by the external processor for flow control. FLAG signals are FX3 outputs that can be configured to show empty, full, and partial status for a dedicated address or the current address. FIFO ADDR tAS SLCS SLRD tRDl SLOE FLAGA dedicated thread Flag for An (1=Not empty 0 = Empty) tOE Data Out High-Z tAH DN(An) tRDO tOE tRDOtOH tOH tRDh tRDO tLZ DN(An) D N(Am) DN+1(Am) DN+2(Am) SLWR (HIGH) An Am FLAGB dedicated thread Flag for Am (1=Not empty 0 = Empty) tRFLGtFLG
Figure 15. Asynchronous Slave FIFO Write Mode Note: PKTEND must be asserted at the same time as SLWR#.
Table 12. Asynchronous Slave FIFO Parameters[8]
- All parameters guaranteed by design and validated through characterization.
Figure 16. I2C Timing Definition
Table 13. I2C Timing Parameters[9]
- All parameters guaranteed by design and validated through characterization.
Figure 17. I2S Transmit Cycle Table 13. I2C Timing Parameters[9] (continued) Table 14. I2S Timing Parameters[10] Note tT is selectable through clock gears. Max Ttr is designed for 96-kHz codec at 32 bits to be 326 ns (3.072 MHz).
- All parameters guaranteed by design and validated through characterization.
Figure 18. SPI Timing
Table 15. SPI Timing Parameters[11]
- All parameters guaranteed by design and validated through characterization.
- Depends on LAG and LEAD setting in the SPI_CONFIG register.
FX3’s hard reset sequence requirements are specified in this section. Figure 19. Reset Sequence Table 16. Reset and Standby Timing Parameters
Figure 20. 121-ball FBGA Package Diagram
Figure 21. 131-ball WLCSP Package Diagram Note Underfill is required on the board design. Contact Cypress Applications for details.
Document Number: 001-52136 Rev. *N Page 41 of 45
Ordering Information
Table 17. Ordering Information
Document Number: 001-52136 Rev. *N Page 42 of 45 Acronyms Document Conventions Units of MeasureAcronym Description DMA direct memory access HNP host negotiation protocol MMC multimedia card MTP media transfer protocol PLL phase locked loop PMIC power management IC SD secure digital SD secure digital SDIO secure digital input / output SLC single-level cell SLCS Slave Chip Select SLOE Slave Output Enable SLRD Slave Read SLWR Slave Write SPI serial peripheral interface SRP session request protocol USB universal serial bus WLCSP wafer level chip scale package Symbol Unit of Measure °C degree Celsius µA microamperes µs microseconds mA milliamperes Mbps Megabits per second MBps Megabytes per second MHz mega hertz ms milliseconds ns nanoseconds ohms pF pico Farad Vv o l t s
Document Number: 001-52136 Rev. *N Page 43 of 45 Document History Page Document Title: CYUSB301X, EZ-USB® FX3: SuperSpeed USB Controller Document Number: 001-52136 Revision ECN Orig. of Change Submission Date Description of Change ** 2669761 VSO/PYRS 03/06/09 New data sheet *A 2758370 VSO 09/01 /09 Updated the part# from CYX01XXBB to CYUSB3011-BZXI Changed the title from “ADVANCE” to “ADVANCE INFORMATION” In page 1, the second bullet (Flexible Host Interface), add “32-bit, 100 MHz” to first sub bullet. In page 1, changed the second bullet “Flexible Host Interface” to General Programmable Interface”. In page 1, the second bullet (Flexible Host Interface), removed "DMA Slave Support” and "MMC Slave support with Pass through Boot" sub bullets. In page 1, third bullet, changed "50 A with Core Power" to "60 A with Core Power" In page 1, fifth bullet, added "at 1 MHz" In page 1, seventh bullet, added "up to 4MHz" to UART In page 1, Applications Section, move “Digital Still Cameras” to second line. In page 1, Applications Section, added “Machine Vision” and Industrial Cameras” Added ™ to GPIF and FX3. In page 1, updated Logic Block Diagram. In page 2, section of “Functional Overview”, updated the whole section. In page 2, removed the section of “Product Interface” In page 2, removed the section of “Processor Interface (P-Port)” In page 2, removed the section of “USB Interface (U-Port)” In page 2, removed the section of “Other Interfaces” In page 2, added a section of "GPIF II" In page 2, added a section of "CPU" In page 2, added a section of "JTAG Interface" In page 2, added a section of "Boot Options" In page 2, added a section of "ReNumeration" In page 2, added a section of "Power" In the section of “Package”, replaced “West Bridge USB 3.0 Platform” by FX3. In the section of “Package”, added 0.8 mm pitch in front of BGA. Added Pin List (Table 1) *B 2779196 VSO/PYRS 09/29/09 Features: Added the thrid bullet “Fully accessible 32-bit ARM9 core with 512kB of embedded SRAM” Added the thrid line “EZ USB™ Software and DVK for easy code development” Table 1: Pin 74, corrected to NC - No Connect. Changed title to EZ-USB™ FX3: SuperSpeed USB Controller *C 2823531 OSG 12/08/09 Added data sheet to the USB 3.0 EROS spec 001-51884. No technical updates. *D 3080927 OSG 11/08/2010 Changed status from Advance to Preliminary Changed part number from CYUSB3011 to CYUSB3014 Added the following sections: Power, Configuration Options, Digital I/Os, System-level ESD, Absolute Maximum Ratings, AC Timing Parameters, Reset Sequence, Package Diagram Added DC Specifications table Updated feature list Updated Pin List Added support for selectable clock input frequencies. Updated block diagram Updated part number Updated package diagram
Document Number: 001-52136 Rev. *N Page 44 of 45 *E 3204393 OSG 03/24/2011 Updated Slave FIFO pr otocol and added ZLP signaling protocol Changed GPIFII asynchronous tDO parameter Changed Async Slave FIFO tOE parameter Changed Async Slave FIFO tRDO parameter Added tCOE parameter to GPIFII Sync mode timing parameters Renamed GPIFII Sync mode tDO to tCO and tDO_ss0 to tCO_ss0 Modified description of GPIFII Sync tCO (previously tDO) parameter Changed tAH(address hold time) parameter in Async Slave FIFO modes to be with respect to rising edge of SLWR#/SLRD# instead of falling edge. Correspondingly, changed the tAH number. Removed 24 bit data bus support for GPIFII. *F 3219493 OSG 04/07/2011 Minor ECN - Release to web. No content changes. *G 3235250 GSZ 04/20/2011 Minor updates in Features. *H 3217917 OSG 04/06/2011 Updated GPIFII Synchronous Timing diagram. Added SPI Boot option. Corrected values of R_USB2 and R_USB3. Corrected TCK and TRST# pull-up/pull-down configuration. Minor updates to block diagrams. Corrected Synchronous Slave FIFO tDH parameter. *I 3305568 DSG 07/07/2011 Minor ECN - Correct ECN number in revision *F. No content changes. *J 3369042 OSG 12/06/2011 Changed tWRPE parameter to 2ns Updated tRR and tRPW for crystal input Added clarification regarding I OZ and IIX Updated Sync SLave FIFO Read timing diagram Updated SPI timing diagram Removed tGRANULARITY parameter Updated I2S Timing diagram and tTd parameter Updated 121-ball FBGA package diagram. Added clarification regarding VCC in DC Specifications table In Power Modes description, stated that VIO1 cannot be turned off at any time if the GPIFII is used in the application Updated Absolute Maximum Ratings Added requirement for by-pass capacitor on U3RX VDDQ and U3TXVDDQ Updated tPEI parameter in Async Slave FIFO timing table Updated Sync Slave FIFO write and read timing diagrams Updated I2C interface tVD:ACK parameter for 1MHz operation Clarified that CTL[15] is not usable as a GPIO Changed datasheet status from Preliminary to Final. *K 3534275 OSG 02/24/2012 Corrected typo in the block diagram. *L 3649782 OSG 08/16/2012 Changed part number to CYUSB301X. Added 256 KB range for embedded SRAM. Updated Functional Overview, Other Interfaces, and Clocking sections. Added Pin List for CYUSB3011 and CYUSB3013 parts. Updated Ordering Information with new part numbers. *M 3848148 OSG 12/20/2012 Updated 121-ball FBGA package diagram to current revision. *N 4016006 OSG 05/31/2013 Updated Features (Added 131-ball WLCSP under Package option). Updated Pin Configurations (Added FX3 131-ball WLCSP Ball Map (Figure 8)). Updated Pin Description (Updated Table 7). Updated Absolute Maximum Ratings (Included Commercial Temperature Range related information). Updated Operating Conditions (Included Commercial Temperature Range related information). Updated Package Diagram (Added 131-ball WLCSP Package Diagram (Figure 21)). Updated Ordering Information (Updated part numbers). Document History Page (continued) Document Title: CYUSB301X, EZ-USB® FX3: SuperSpeed USB Controller Document Number: 001-52136 Revision ECN Orig. of Change Submission Date Description of Change
Document Number: 001-52136 Rev. *N Revised May 31, 2013 Page 45 of 45 EZ-USB™ is a trademark and West Bridge ® is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders. CYUSB301X © Cypress Semiconductor Corporation, 2009-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subj ect to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to t he materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.co m/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress. com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cyp ress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5