S70GL02GP CYPRESS | Alldatasheet
Document overview
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- PDF pages: 11
Technical content
Datasheet sections
- 1.1 Recommended Combinations
- 2.1 Special Handling Instructions for BGA Package
2 Gbit, 3V Page Mode
better performance and lower power consumption. specifications, refer to the discrete die datasheet provided in Table 1. Table 1. Affected Documents/Related Documents
1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash with 90 nm MirrorBit
Document Number: 002-01338 Rev. *D Page 2 of 11 Performance Characteristics Notes 1. Access times are dependent on V CC and VIO operating ranges. See Ordering Information on page 4 for further details. 2. Contact a sales representative for availability. Max. Read Access Times (ns)(Note 1) Parameter 2 Gb Random Access Time (tACC)1 1 0 Page Access Time (tPACC)2 5 CE# Access Time (tCE) 110 OE# Access Time (tOE) 25 Current Consumption (typical values) Random Access Read 30 mA 8-Word Page Read 1 mA Program/Erase 50 mA Standby 2 µA Program & Erase Times (typical values) Single Word Programming 60 µs Effective Write Buffer Programming (V CC) Per Word 15 µs Effective Write Buffer Programming (VACC) Per Word 15 µs Sector Erase Time (64 Kword Sector) 0.5 s
Document Number: 002-01338 Rev. *D Page 4 of 11 1. Ordering Information The ordering part number is formed by a valid combination of the following:
1.1 Recommended Combinations
Recommended Combinations table below list various configurations planned to be available in volume. The table below will be updated as new combinations are released. Check with your local sales representative to confirm availability of specific configuration not listed or to check on newly released combinations. Notes 1. Contact a local sales representative for availability. 2. BGA package marking omits leading “S29” and packing type designator from ordering part number. 3. Packing Type “0” is standard option. S70GL02GP 11 F F C R1 0 PACKING TYPE 0 = Tray (standard; see (Note 3) 2 = 7” Tape and Reel 3 = 13” Tape and Reel MODEL NUMBER (V IO range, protection when WP# =VIL) R1 = V IO = VCC = 3.0 to 3.6V, highest address sector protected R2 = V IO = VCC = 3.0 to 3.6V, lowest address sector protected TEMPERATURE RANGE I = Industrial (–40 °C to +85 °C) C = Commercial (0 °C to +85 °C) PACKAGE MATERIALS SET A = Pb (Note 1) F = Pb-free PACKAGE TYPE F = Fortified Ball Grid Array, 1.0 mm pitch package SPEED OPTION 11 = 110 ns DEVICE NUMBER/DESCRIPTION S70GL02GP 3.0V-only, 2048 Megabit (128 M x 16-Bit/256 M x 8-Bit) Page-Mode Flash Memory Manufactured on 90 nm MirrorBit process technology S29GL-P Recommended Combinations (Note 1) Base OPN Speed (ns) Package and Temperature Model Number Packing Type Ordering Part Number (x = Packing Type) S70GL02GP 110 FFC, FAC (Note 2) R1, R2 0, 2, 3 (Note 3) S70GL02GP11FFCR1x S70GL02GP11FFCR2x S70GL02GP11FACR1x S70GL02GP11FACR2x
- Input/Output Descrip tion and Logic Symbol
Table 1 identifies the input and output package connections provided on the device. Table 1. Input/Output Description DQ14–DQ0 I/O Data input/output. DQ15/A-1 I/O DQ15: Data input/output in word mode. A-1: LSB address input in byte mode. VCC Supply Device Power Supply. VIO Supply Versatile IO Input. device is actively erasing or programming. At High Z, the device is in ready. active. At VIH, the device is in word configuration and data I/O pins DQ0-DQ15 are active. RESET# Input Hardware Reset. Low = device re sets and returns to reading array data. sectors. At VHH, accelerates programming; automatically places device in unlock bypass mode. Should be at VIH for all other conditions. NC No Connect Not connected internally.
Document Number: 002-01338 Rev. *D Page 6 of 11
2.1 Special Handling Instructions for BGA Package
Special handling is required for Flash Memory products in BGA packages. Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Figure 2.1 64-ball Fortified Ball Grid Array 64-ball Fortified BGA Top View, Balls Facing Down A2 C2 D2 E2 F2 G2 H2 A3 C3 D3 E3 F3 G3 H3 A4 C4 D4 E4 F4 G4 H4 A5 C5 D5 E5 F5 G5 H5 A6 C6 D6 E6 F6 G6 H6 A7 C7 D7 E7 F7 G7 H7 DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A21RESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 A1 C1 D1 E1 F1 G1 H1 NC NCVIONCNCNCA26NC A8 C8 B8 D8 E8 F8 G8 H8 A25 NCA24VSSVIOA23A22NC
Document Number: 002-01338 Rev. *D Page 7 of 11
2.2 LSE064—64 ball Fortified Ball Grid Array, 13 11 mm
Figure 2.2 LSE064—64-ball Fortified Ball Grid Array (FBGA), 13 x 11 mm 3611 \\ 16-038.15 \\ 11.13.6 PACKAGE LSE 064 JEDEC N/A D x E 13.00 mm x 11.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.40 PROFILE A1 0.40 --- --- BALL HEIGHT A2 0.79 --- 0.91 BODY THICKNESS D 13.00 BSC. BODY SIZE E 11.00 BSC. BODY SIZE D1 7.00 BSC. MATRIX FOOTPRINT E1 7.00 BSC. MATRIX FOOTPRINT MD 8 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION n 64 BALL COUNT Øb 0.50 0.60 0.70 BALL DIAMETER eE 1.00 BSC. BALL PITCH eD 1.00 BSC BALL PITCH SD / SE 0.50 BSC. SOLDER BALL PLACEMENT --- DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS.
9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
The S70GL02GP consist of uniform 64 Kword (128 Kb) sectors organized as shown in Table 2.
- Erase And Programming Performance
- Typical program and erase times assume the following conditions: 25°C, 3.6 V V CC, 10,000 cycles, checkerboard pattern.
- Under worst case conditions of -40°C, V CC = 3.0 V, 100,000 cycles.
- In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
- System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
Table 2. S70GL02GP Sector & Memory Address Map
64 Kword/128 Kb 2048
Table 3. Autoselect Addresses in System Secure Device Verify (Base) + 03h For S70GL02GPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked. For S70GL02GPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked. Table 4. Erase And Programming Performance
Document Number: 002-01338 Rev. *D Page 9 of 11 6. BGA Package Capacitance Notes 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 12 20 pF COUT Output Capacitance V OUT = 0 20 24 pF CIN2 Control Pin Capacitance V IN = 0 16 20 pF RESET#, WP#/ACC Separated Control Pin V IN = 0 84 90 pF CE# Separated Control Pin V IN = 0 44 50 pF
Document Number: 002-01338 Rev. *D Page 10 of 11 S70GL02GP 7. Revision History Document History Page Document Title: S70GL02GP, 2 Gbit, 3V Page Mode S70GL-P MirrorBit® Flash Document Number: 002-01338 Rev. ECN No. Orig. of Change Submission Date Description of Change ** RYSU 12/04/2006 Initial release *A RYSU 05/19/2008 Global: Changed data sheet designation Added Product Life-cycle notice Removed Table of Figures and Table of Tables Ordering Information: Changed sample OPN Added Commercial temperature range Changed configuration in “Device Number/description” Modified “Recommended Combination” table removed TSOP package option Erase And Program Performance: Chip Program Time - removed comment Common Flash Memory Interface: Removed section (see publication S29GL-P_00 for details) RYSU 02/23/2010 Global: Updated available model options. Corrected Chip Program Time. *C 4950184 RYSU 10/06/2015 Updated to Cypress template *D 5177489 RYSU 03/16/2016 Updated General Description and Distinctive Characteristics.
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