S6E2H4

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Technical content

Features

32-bit ARM Cortex-M4F Core  Processor version: r0p1  Up to 160 MHz Frequency Operation  FPU built-in  Support DSP instruction  Memory Protection Unit (MPU): improves the reliability of an embedded system  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories  Flash memory These series are based on two independent on-chip Flash memories.  MainFlash memory

• Up to 512 Kbytes
• Built-in Flash Accelerator System with 16 Kbytes trace buffer memory
• The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.
• Security function for code protection  WorkFlash memory
• 32 Kbytes
• Read cycle:
• 6 wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz
• 4 wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz
• 2 wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz
• 0 wait-cycle: the operation frequency up to 40 MHz
• Security function is shared with code protection  SRAM This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core.  SRAM0: Up to 32 Kbytes  SRAM1: Up to 16 Kbytes  SRAM2: Up to 16 Kbytes External Bus Interface  Supports SRAM, NOR, NAND Flash and SDRAM device  Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)  8-/16-bit Data width  Up to 25-bit Address bit  Supports Address/Data multiplex  Supports external RDY function  Supports scramble function
• Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units.
• Possible to set two kinds of the scramble key
• Note: It is necessary to prepare the dedicated software library to use the scramble function. CAN Interface (Max 2 channels)  Compatible with CAN Specification 2.0A/B  Maximum transfer rate: 1 Mbps  Built-in 32 message buffer Multi-function Serial Interface (Max 8 channels)  64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C  UART  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)

Document Number: 001-98941 Rev.*B Page 2 of 160 S6E2H4 Series  Various error detect functions available (parity errors, framing errors, and overrun errors)  CSIO  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detect function available  Serial chip select function (ch.6 and ch.7 only)  Supports high-speed SPI (ch.4 and ch.6 only)  Data length 5 to 16-bit  LIN  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/Slave mode supported  LIN break field generation (can change to 13 to 16-bit length)  LIN break delimiter generation (can change to 1 to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors)  I2C  Standard mode (Max 100 kbps) / High-speed mode (Max 400 kbps) supported  Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.7=ch.B) supported DMA Controller (8 channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: bytes/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536 DSTC (Descriptor System data Transfer Controller) (256 channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation and the chain activation functions. A/D Converter (Max 24 channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 3 units  Conversion time: 0.5 μs @ 5 V  Priority conversion available (priority at 2 levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) DA Converter (Max 2 channels)  R-2R type  12-bit resolution Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer  Event counter mode ( external clock mode ) General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 100 high-speed general-purpose I/O ports @ 120 pin Package  Some pin is 5 V tolerant I/O. See 4. Pin Description and 5. I/O Circuit Type for the corresponding pins. Multi-function Timer (Max 3 units) The Multi-function timer is composed of the following blocks. Minimum resolution: 6.25 ns  16-bit free-run timer × 3ch./unit  Input capture × 4ch./unit  Output compare × 6ch./unit  A/D activation compare × 6ch./unit  Waveform generator × 3ch./unit  16-bit PPG timer × 3ch./unit The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function

Document Number: 001-98941 Rev.*B Page 3 of 160 S6E2H4 Series  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function Real-time Clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC) (Max 3 channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.  The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot Watch Counter The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source. Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz External Interrupt Controller Unit  External interrupt input pin: Max 16 pins  Both edges(Rise edge and Fall edge) detect  Include one non-maskable interrupt (NMI) Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. Hardware watchdog timer is clocked by low-speed internal CR oscillator. Therefore, Hardware watchdog is active in any power saving mode except Stop. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  High-speed internal CR Clock: 4 MHz  Low-speed internal CR Clock: 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low voltage detector reset  Clock supervisor reset Clock SuperVisor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  External OSC clock failure (clock stop) is detected, reset is asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Low-power Consumption Mode Six low-power consumption modes are supported.  Sleep  Timer  RTC

Document Number: 001-98941 Rev.*B Page 4 of 160 S6E2H4 Series  Stop  Deep standby RTC (selectable from with/without RAM retention)  Deep standby stop (selectable from with/without RAM retention) VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used.  RTC  32 kHz oscillation circuit  Power-on circuit  Back up register: 32 bytes  Port circuit Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities. Unique ID Unique value of the device (41-bit) is set. Power Supply Two Power Supplies  Wide range voltage: VCC = 2.7 V to 5.5 V  Power supply for VBAT: VBAT = 2.7 V to 5.5 V

Document Number: 001-98941 Rev.*B Page 5 of 160 S6E2H4 Series Table of Contents

12.4.5 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for Input Clock

Document Number: 001-98941 Rev.*B Page 6 of 160 S6E2H4 Series

Document Number: 001-98941 Rev.*B Page 7 of 160 S6E2H4 Series 1. Product Lineup Memory Size Product name S6E2H44E0A S6E2H44F0A S6E2H44G0A S6E2H46E0A S6E2H46F0A S6E2H46G0A MainFlash memory 256 Kbytes 512 Kbytes WorkFlash memory 32 Kbytes 32 Kbytes On-chip SRAM 32 Kbytes 64 Kbytes SRAM0 16 Kbytes 32 Kbytes SRAM1 8 Kbytes 16 Kbytes SRAM2 8 Kbytes 16 Kbytes Function Product name S6E2H44E0A S6E2H46E0A S6E2H44F0A S6E2H46F0A S6E2H44G0A S6E2H46G0A Pin count 80 100 120/121 CPU Cortex-M4F, MPU, NVIC 128ch. Freq. 160 MHz Power supply voltage range 2.7 V to 5.5 V CAN 2ch. (Max) DMAC 8ch. DSTC 256ch. External Bus Interface Addr:19-bit (Max), R/W data: 8-bit (Max), CS:5 (Max), SRAM, NOR Flash Addr:25-bit (Max), R/W data: 8-/16-bit (Max), CS:9 (Max), SRAM, NOR Flash, SDRAM Addr:25-bit (Max), R/W data: 8-/16-bit (Max), CS:9 (Max), SRAM, NOR Flash, NAND Flash, SDRAM Multi-function Serial Interface (UART/CSIO/LIN/I2C) 8ch. (Max) Base Timer (PWC/Reload timer/PWM/PPG) 8ch. (Max) MF Timer A/D activation compare 6ch. 3 units (Max) Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG 3ch. QPRC 3ch. (Max) Dual Timer 1 unit Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog Timer 1ch. (SW) + 1ch. (HW) External Interrupts 16 pins (Max) + NMI × 1 I/O Ports 63 pins (Max) 80 pins (Max) 100 pins (Max) 12-bit A/D Converter 16ch. (3 units) 24ch. (3 units) 12-bit D/A Converter 2 units (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. Built-in CR High-speed 4 MHz (±2%) Low-speed 100 kHz (Typ) Debug Function SWJ-DP/ETM Unique ID Yes

Document Number: 001-98941 Rev.*B Page 8 of 160 S6E2H4 Series Notes: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. − See 12.4.3 Built-in CR Oscillation Characteristics for the accuracy of the built-in CR. 2. Packages Product Name Package S6E2H44E0A S6E2H46E0A S6E2H44F0A S6E2H46F0A S6E2H44G0A S6E2H46G0A LQFP: LQH080 (0.5-mm pitch)  - - LQFP: LQI100 (0.5-mm pitch) -  - LQFP: LQM120 (0.5-mm pitch) - -  FBGA: FDI121 (0.5-mm pitch) - -  : Supported Note : − See 14. Package Dimensions for detailed information on each package.

Document Number: 001-98941 Rev.*B Page 9 of 160 S6E2H4 Series 3. Pin Assignment LQH080 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/IC20_0/AIN2_1 P80/IC21_0/BIN2_1 VCC P60/SCK5_0/FRCK2_0/TIOA2_2/NMIX/WKUP0/MRDY_0 P61/SOT5_0/TIOB2_2/ZIN2_1/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/TX0_2/IC22_0/INT04_1/MOEX_0 P63/RX0_2/IC23_0/INT03_0/MWEX_0/CROUT_1 P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P09/AN19/SOT1_0/IC23_1/TIOA3_2/MCSX5_0 P0A/SIN1_0/FRCK1_0/INT12_2/MCSX1_0 P0B/SIN6_1/IC10_0/TIOB6_1/INT00_1/MCSX0_0 P0C/SOT6_1/IC11_0/TIOA6_1/MALE_0 P0D/SCK6_1/IC12_0/TIOA5_2/MDQM0_0 P0E/SCS6_1/IC13_0/TIOB5_2/MDQM1_0 VCC VCC 1 60 VSS P50/CTS4_0/RTO10_0/AIN0_2/INT00_0/MADATA00_0 2 59 P21/AN17/SIN0_0/RTO24_0/INT06_1 P51/RTS4_0/RTO11_0/BIN0_2/INT01_0/MADATA01_0 3 58 P22/AN16/SOT0_0/RTO23_0/TIOB7_1/CROUT_0 P52/SCK4_0/RTO12_0/ZIN0_2/MADATA02_0 4 57 P23/AN15/SCK0_0/RTO00_1/TIOA7_1 P53/SOT4_0/RTO13_0/TIOA1_2/MADATA03_0 5 56 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P54/SIN4_0/RTO14_0/TIOB1_2/INT02_0/MADATA04_0 6 55 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 54 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 53 P18/AN08/SCK2_2/DTTI2X_0/MAD15_0 P30/RTS4_2/RTO25_1/TIOB0_1/INT15_2/WKUP1/MADATA07_0 9 52 AVRH P31/SIN3_1/DTTI2X_1/TIOB1_1/INT09_2/MADATA08_0 10 51 AVRL P32/SOT3_1/TIOB2_1/INT10_1/MADATA09_0 11 50 AVSS P33/ADTG_6/SCK3_1/TIOB3_1/INT04_0/MADATA10_0 12 49 AVCC P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2 13 48 P17/AN07/SOT2_2/RTO20_0/AIN2_2/WKUP3/MAD14_0 P3A/RTO00_0/TIOA0_1/AIN0_0 14 47 P16/AN06/SIN2_2/RTO21_0/BIN2_2/INT14_1/MAD13_0 P3B/RTO01_0/TIOA1_1/BIN0_0 15 46 P15/AN05/SCK0_1/RTO22_0/ZIN2_2/MAD12_0 P3C/RTO02_0/TIOA2_1/ZIN0_0 16 45 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3D/RTO03_0/TIOA3_1/MAD00_0 17 44 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3E/RTO04_0/TIOA4_1/MAD01_0 18 43 P12/AN02/SCK1_1/IC01_2/MAD09_0/RTCCO_1/SUBOUT_1 P3F/RTO05_0/TIOA5_1/MAD02_0 19 42 P11/AN01/SOT1_1/TX1_2/IC00_2/MAD08_0 VSS 20 41 P10/AN00/SIN1_1/RX1_2/FRCK0_2/INT02_1/MAD07_0 P44/DA0/RTO14_1/TIOA4_0 P45/DA1/RTO15_1/TIOB0_0 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/SCS7_1/TIOB1_0/MAD03_0 P4C/SCK7_1/TIOB2_0/AIN1_2/MAD04_0 P4D/SOT7_1/TIOB3_0/BIN1_2/INT13_2/MAD05_0 P4E/SIN7_1/FRCK1_1/TIOB4_0/ZIN1_2/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 80

Document Number: 001-98941 Rev.*B Page 10 of 160 S6E2H4 Series LQI100 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/IC20_0/AIN2_1 P80/IC21_0/BIN2_1 VCC P60/SCK5_0/FRCK2_0/TIOA2_2/NMIX/WKUP0/MRDY_0 P61/SOT5_0/TIOB2_2/ZIN2_1/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/TX0_2/IC22_0/INT04_1/MOEX_0 P63/RX0_2/IC23_0/INT03_0/MWEX_0/CROUT_1 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/SIN7_0/FRCK2_1/INT01_1/MCSX2_0/TRACECLK P06/AN22/SOT7_0/IC20_1/TIOB0_2/MCSX3_0/TRACED3 P07/AN21/SCK7_0/IC21_1/TIOA0_2/MCLKOUT_0/TRACED2 P08/AN20/SCK1_0/IC22_1/TIOB3_2/MCSX4_0/TRACED1 P09/AN19/SOT1_0/IC23_1/TIOA3_2/MCSX5_0/TRACED0 P0A/SIN1_0/FRCK1_0/INT12_2/MCSX1_0 P0B/SIN6_1/IC10_0/TIOB6_1/INT00_1/MCSX0_0 P0C/SOT6_1/IC11_0/TIOA6_1/MALE_0 P0D/SCK6_1/IC12_0/TIOA5_2/MDQM0_0 P0E/SCS6_1/IC13_0/TIOB5_2/MDQM1_0 VCC 100 VCC 1 75 VSS P50/CTS4_0/RTO10_0/AIN0_2/INT00_0/MADATA00_0 2 74 P20/AN18/RTO25_0/AIN1_1/INT05_0/MAD24_0 P51/RTS4_0/RTO11_0/BIN0_2/INT01_0/MADATA01_0 3 73 P21/AN17/SIN0_0/RTO24_0/BIN1_1/INT06_1/MAD23_0 P52/SCK4_0/RTO12_0/ZIN0_2/MADATA02_0 4 72 P22/AN16/SOT0_0/RTO23_0/TIOB7_1/ZIN1_1/CROUT_0 P53/SOT4_0/RTO13_0/TIOA1_2/MADATA03_0 5 71 P23/AN15/SCK0_0/RTO00_1/TIOA7_1/MAD22_0 P54/SIN4_0/RTO14_0/TIOB1_2/INT02_0/MADATA04_0 6 70 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 69 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 68 P1C/AN12/CTS4_1/IC03_1/MAD19_0 P30/RTS4_2/RTO25_1/TIOB0_1/INT15_2/WKUP1/MADATA07_0 9 67 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P31/SIN3_1/DTTI2X_1/TIOB1_1/INT09_2/MADATA08_0 10 66 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P32/SOT3_1/TIOB2_1/INT10_1/MADATA09_0 11 65 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P33/ADTG_6/SCK3_1/TIOB3_1/INT04_0/MADATA10_0 12 64 P18/AN08/SCK2_2/DTTI2X_0/MAD15_0 P34/TX0_1/FRCK0_0/TIOB4_1/MADATA11_0 13 63 AVRH P35/RX0_1/IC03_0/TIOB5_1/INT08_1/MADATA12_0 14 62 AVRL P36/SIN5_2/IC02_0/INT09_1/MADATA13_0 15 61 AVSS P37/SOT5_2/IC01_0/INT05_2/MADATA14_0 16 60 AVCC P38/SCK5_2/IC00_0/INT06_2/MADATA15_0 17 59 P17/AN07/SOT2_2/RTO20_0/AIN2_2/WKUP3/MAD14_0 P39/ADTG_2/DTTI0X_0/MSDCLK_0/RTCCO_2/SUBOUT_2 18 58 P16/AN06/SIN2_2/RTO21_0/BIN2_2/INT14_1/MAD13_0 P3A/RTO00_0/TIOA0_1/AIN0_0/MSDCKE_0 19 57 P15/AN05/SCK0_1/RTO22_0/ZIN2_2/MAD12_0 P3B/RTO01_0/TIOA1_1/BIN0_0/MRASX_0 20 56 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3C/RTO02_0/TIOA2_1/ZIN0_0/MCASX_0 21 55 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3D/RTO03_0/TIOA3_1/MAD00_0 22 54 P12/AN02/SCK1_1/IC01_2/MAD09_0/RTCCO_1/SUBOUT_1 P3E/RTO04_0/TIOA4_1/MAD01_0 23 53 P11/AN01/SOT1_1/TX1_2/IC00_2/MAD08_0 P3F/RTO05_0/TIOA5_1/MAD02_0 24 52 P10/AN00/SIN1_1/RX1_2/FRCK0_2/INT02_1/MAD07_0 VSS 25 51 VCC VCC P40/RTO10_1/TIOA0_0/INT12_1 P41/RTO11_1/TIOA1_0/AIN2_0/INT13_1 P42/RTO12_1/TIOA2_0/BIN2_0/MDWEX_0 P43/ADTG_7/RTO13_1/TIOA3_0/ZIN2_0/MCSX8_0 P44/DA0/RTO14_1/TIOA4_0 P45/DA1/RTO15_1/TIOB0_0 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/SCS7_1/TIOB1_0/MAD03_0 P4C/SCK7_1/TIOB2_0/AIN1_2/MAD04_0 P4D/SOT7_1/TIOB3_0/BIN1_2/INT13_2/MAD05_0 P4E/SIN7_1/FRCK1_1/TIOB4_0/ZIN1_2/INT11_1/WKUP2/MAD06_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 100

Document Number: 001-98941 Rev.*B Page 11 of 160 S6E2H4 Series LQM120 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/IC20_0/AIN2_1 P80/IC21_0/BIN2_1 VCC P60/SCK5_0/FRCK2_0/TIOA2_2/NMIX/WKUP0/MRDY_0 P61/SOT5_0/TIOB2_2/ZIN2_1/RTCCO_0/SUBOUT_0 P62/ADTG_3/SIN5_0/TX0_2/IC22_0/INT04_1/MOEX_0 P63/SIN5_1/RX0_2/IC23_0/INT03_0/MWEX_0/CROUT_1 P64/SOT5_1/TIOA7_0/INT10_2 P65/SCK5_1/TIOB7_0 P66/ADTG_8/SIN3_0/INT11_2 P67/SOT3_0/TIOA7_2 P68/SCK3_0/TIOB7_2/INT00_2 VSS P00/TRSTX/MCSX7_0 P01/TCK/SWCLK P02/TDI/MCSX6_0 P03/TMS/SWDIO P04/TDO/SWO P05/AN23/ADTG_0/SIN7_0/FRCK2_1/INT01_1/MCSX2_0/TRACECLK P06/AN22/SOT7_0/IC20_1/TIOB0_2/MCSX3_0/TRACED3 P07/AN21/SCK7_0/IC21_1/TIOA0_2/MCLKOUT_0/TRACED2 P08/AN20/SCK1_0/IC22_1/TIOB3_2/MCSX4_0/TRACED1 P09/AN19/SOT1_0/IC23_1/TIOA3_2/MCSX5_0/TRACED0 P0A/SIN1_0/FRCK1_0/INT12_2/MCSX1_0 P0B/SIN6_1/IC10_0/TIOB6_1/INT00_1/MCSX0_0 P0C/SOT6_1/IC11_0/TIOA6_1/MALE_0 P0D/SCK6_1/IC12_0/TIOA5_2/MDQM0_0 P0E/SCS6_1/IC13_0/TIOB5_2/MDQM1_0 VCC 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 VCC 1 90 VSS P50/CTS4_0/RTO10_0/AIN0_2/INT00_0/MADATA00_0 2 89 P20/AN18/RTO25_0/AIN1_1/INT05_0/MAD24_0 P51/RTS4_0/RTO11_0/BIN0_2/INT01_0/MADATA01_0 3 88 P21/AN17/SIN0_0/RTO24_0/BIN1_1/INT06_1/MAD23_0 P52/SCK4_0/RTO12_0/ZIN0_2/MADATA02_0 4 87 P22/AN16/SOT0_0/RTO23_0/TIOB7_1/ZIN1_1/CROUT_0 P53/SOT4_0/RTO13_0/TIOA1_2/MADATA03_0 5 86 P23/AN15/SCK0_0/RTO00_1/TIOA7_1/MAD22_0 P54/SIN4_0/RTO14_0/TIOB1_2/INT02_0/MADATA04_0 6 85 P24/SIN2_1/RX1_0/RTO01_1/INT01_2 P55/ADTG_1/SIN6_0/RTO15_0/INT07_2/MADATA05_0 7 84 P25/SOT2_1/TX1_0/RTO02_1/TIOA5_0 P56/SOT6_0/DTTI1X_0/INT08_2/MADATA06_0 8 83 P26/SCK2_1/RTO03_1/TIOB5_0 P57/SCK6_0/RTO20_1/MADATA07_0 9 82 P27/RTO04_1/TIOA6_2/INT02_2 P58/SIN4_2/RTO21_1/AIN1_0/INT04_2/MADATA08_0 10 81 P1F/ADTG_4/RTO05_1/TIOB6_2 P59/SOT4_2/RX1_1/RTO22_1/BIN1_0/INT07_1/MADATA09_0 11 80 P1E/AN14/ADTG_5/FRCK0_1/MAD21_0 P5A/SCK4_2/TX1_1/RTO23_1/ZIN1_0/MADATA10_0 12 79 P1D/AN13/RTS4_1/DTTI0X_1/MAD20_0 P5B/CTS4_2/RTO24_1/MADATA11_0 13 78 P1C/AN12/CTS4_1/IC03_1/MAD19_0 P30/RTS4_2/RTO25_1/TIOB0_1/INT15_2/WKUP1/MADATA12_0 14 77 P1B/AN11/SCK4_1/IC02_1/MAD18_0 P31/SIN3_1/DTTI2X_1/TIOB1_1/INT09_2/MADATA13_0 15 76 P1A/AN10/SOT4_1/IC01_1/MAD17_0 P32/SOT3_1/TIOB2_1/INT10_1/MADATA14_0 16 75 P19/AN09/SIN4_1/IC00_1/INT05_1/MAD16_0 P33/ADTG_6/SCK3_1/TIOB3_1/INT04_0/MADATA15_0 17 74 P18/AN08/SCK2_2/DTTI2X_0/MAD15_0 P34/TX0_1/FRCK0_0/TIOB4_1/MNALE_0 18 73 AVRH P35/RX0_1/IC03_0/TIOB5_1/INT08_1/MNCLE_0 19 72 AVRL P36/SIN5_2/IC02_0/INT09_1/MNWEX_0 20 71 AVSS P37/SOT5_2/IC01_0/INT05_2/MNREX_0 21 70 AVCC P38/SCK5_2/IC00_0/INT06_2 22 69 P17/AN07/SOT2_2/RTO20_0/AIN2_2/WKUP3/MAD14_0 P39/ADTG_2/DTTI0X_0/MSDCLK_0/RTCCO_2/SUBOUT_2 23 68 P16/AN06/SIN2_2/RTO21_0/BIN2_2/INT14_1/MAD13_0 P3A/RTO00_0/TIOA0_1/AIN0_0/MSDCKE_0 24 67 P15/AN05/SCK0_1/RTO22_0/ZIN2_2/MAD12_0 P3B/RTO01_0/TIOA1_1/BIN0_0/MRASX_0 25 66 P14/AN04/SOT0_1/IC03_2/MAD11_0 P3C/RTO02_0/TIOA2_1/ZIN0_0/MCASX_0 26 65 P13/AN03/SIN0_1/IC02_2/INT03_1/MAD10_0 P3D/RTO03_0/TIOA3_1/MAD00_0 27 64 P12/AN02/SCK1_1/IC01_2/MAD09_0/RTCCO_1/SUBOUT_1 P3E/RTO04_0/TIOA4_1/MAD01_0 28 63 P11/AN01/SOT1_1/TX1_2/IC00_2/MAD08_0 P3F/RTO05_0/TIOA5_1/MAD02_0 29 62 P10/AN00/SIN1_1/RX1_2/FRCK0_2/INT02_1/MAD07_0 VSS 30 61 VCC VCC P40/RTO10_1/TIOA0_0/INT12_1 P41/RTO11_1/TIOA1_0/AIN2_0/INT13_1 P42/RTO12_1/TIOA2_0/BIN2_0/MDWEX_0 P43/ADTG_7/RTO13_1/TIOA3_0/ZIN2_0/MCSX8_0 P44/DA0/RTO14_1/TIOA4_0 P45/DA1/RTO15_1/TIOB0_0 INITX P46/X0A P47/X1A P48/VREGCTL P49/VWAKEUP VBAT C VSS VCC P4B/SCS7_1/TIOB1_0/MAD03_0 P4C/SCK7_1/TIOB2_0/AIN1_2/MAD04_0 P4D/SOT7_1/TIOB3_0/BIN1_2/INT13_2/MAD05_0 P4E/SIN7_1/FRCK1_1/TIOB4_0/ZIN1_2/INT11_1/WKUP2/MAD06_0 P70/TX0_0/IC13_1/TIOA4_2/AIN0_1 P71/RX0_0/IC12_1/TIOB4_2/BIN0_1/INT15_1 P72/SIN2_0/IC11_1/TIOA6_0/ZIN0_1/INT14_2 P73/SOT2_0/IC10_1/TIOB6_0/INT03_2 P74/SCK2_0/DTTI1X_1 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 120

Document Number: 001-98941 Rev.*B Page 12 of 160 S6E2H4 Series FDI121 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 1 2 3 4 5 6 7 8 9 10 11 A VSS P81 P80 VCC TRSTX VSS P06 P0A P0D VCC VSS B VCC P60 P61 P63 TCK TDO P07 P0B P0E P24 P20 C P50 P51 P62 P64 TDI TMS P08 P0C P25 P22 P21 D P52 P53 P54 P65 P66 P05 P09 P26 P1E P1D P23 E P30 P55 P56 P57 P67 P68 P27 P1C P1B P1A P19 F P34 P33 P32 P31 P58 P59 P1F P18 P17 P16 AVRH G P35 P36 P37 P38 P5A P5B P72 P15 P14 P13 AVRL H P39 P3A P3B P3C P43 P70 P71 P73 P12 P11 AVSS J P3D P3E P41 P45 P42 P4B P4C P4D P74 P10 AVCC K VCC P3F P44 X1A P48 P49 VCC P4E MD0 VSS VCC L VSS P40 INITX X0A VBAT C VSS MD1 X0 X1 VSS

Document Number: 001-98941 Rev.*B Page 13 of 160 S6E2H4 Series 4. Pin Description List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 1 1 1 B1 VCC - - 2 2 2 C1 P50 E K CTS4_0 AIN0_2 RTO10_0 (PPG10_0) INT00_0 MADATA00_0 3 3 3 C2 P51 E K RTS4_0 BIN0_2 RTO11_0 (PPG10_0) INT01_0 MADATA01_0 4 4 4 D1 P52 E I SCK4_0 (SCL4_0) ZIN0_2 RTO12_0 (PPG12_0) MADATA02_0 5 5 5 D2 P53 E I TIOA1_2 SOT4_0 (SDA4_0) RTO13_0 (PPG12_0) MADATA03_0 6 6 6 D3 P54 E K TIOB1_2 SIN4_0 RTO14_0 (PPG14_0) INT02_0 MADATA04_0

Document Number: 001-98941 Rev.*B Page 14 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 7 7 7 E2 P55 E K ADTG_1 SIN6_0 RTO15_0 (PPG14_0) INT07_2 MADATA05_0 8 8 8 E3 P56 E K SOT6_0 (SDA6_0) DTTI1X_0 INT08_2 MADATA06_0 9 - - E4 P57 E I SCK6_0 (SCL6_0) MADATA07_0 RTO20_1 10 - - F5 P58 E K SIN4_2 AIN1_0 INT04_2 MADATA08_0 RTO21_1 11 - - F6 P59 E K SOT4_2 (SDA4_2) BIN1_0 INT07_1 MADATA09_0 RTO22_1 RX1_1 12 - - G5 P5A E I SCK4_2 (SCL4_2) ZIN1_0 MADATA10_0 RTO23_1 TX1_1 13 - - G6 P5B E I CTS4_2 MADATA11_0 RTO24_1

Document Number: 001-98941 Rev.*B Page 15 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 14 9 9 E1 P30 E Q TIOB0_1 RTS4_2 INT15_2 WKUP1 - - MADATA07_0 14 - - E1 MADATA12_0 9 9 RTO25_1 15 10 10 F4 P31 I K TIOB1_1 SIN3_1 INT09_2 - - MADATA08_0 15 - - F4 MADATA13_0 10 10 DTTI2X_1 16 11 11 F3 P32 N K TIOB2_1 SOT3_1 (SDA3_1) INT10_1 - - MADATA09_0 16 - - F3 MADATA14_0 17 12 12 F2 P33 N K ADTG_6 TIOB3_1 SCK3_1 (SCL3_1) INT04_0 - - MADATA10_0 17 - - F2 MADATA15_0 18 13 - F1 P34 E I TIOB4_1 FRCK0_0 TX0_1 - - MADATA11_0 18 - - F1 MNALE_0 19 14 - G1 P35 E K TIOB5_1 IC03_0 INT08_1 RX0_1 - - MADATA12_0 19 - - G1 MNCLE_0

Document Number: 001-98941 Rev.*B Page 16 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 20 15 - G2 P36 E K SIN5_2 IC02_0 INT09_1 - - MADATA13_0 20 - - G2 MNWEX_0 21 16 - G3 P37 E K SOT5_2 (SDA5_2) IC01_0 INT05_2 - - MADATA14_0 21 - - G3 MNREX_0 22 17 - G4 P38 E K SCK5_2 (SCL5_2) IC00_0 INT06_2 - - MADATA15_0 23 18 13 H1 P39 L I ADTG_2 DTTI0X_0 RTCCO_2 SUBOUT_2 - MSDCLK_0 24 19 14 H2 P3A G I TIOA0_1 AIN0_0 RTO00_0 (PPG00_0) - MSDCKE_0 25 20 15 H3 P3B G I TIOA1_1 BIN0_0 RTO01_0 (PPG00_0) - MRASX_0 26 21 16 H4 P3C G I TIOA2_1 ZIN0_0 RTO02_0 (PPG02_0) - MCASX_0 27 22 17 J1 P3D G I TIOA3_1 RTO03_0 (PPG02_0) MAD00_0

Document Number: 001-98941 Rev.*B Page 17 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 28 23 18 J2 P3E G I TIOA4_1 RTO04_0 (PPG04_0) MAD01_0 29 24 19 K2 P3F G I TIOA5_1 RTO05_0 (PPG04_0) MAD02_0 30 25 20 L1 VSS - - 31 26 - K1 VCC - - 32 27 - L2 P40 G K TIOA0_0 RTO10_1 (PPG10_1) INT12_1 33 28 - J3 P41 G K TIOA1_0 RTO11_1 (PPG10_1) INT13_1 AIN2_0 34 29 - J5 P42 G I TIOA2_0 RTO12_1 (PPG12_1) MSDWEX_0 BIN2_0 35 30 - H5 P43 G I ADTG_7 TIOA3_0 RTO13_1 (PPG12_1) MCSX8_0 ZIN2_0 36 31 21 K3 P44 R J TIOA4_0 RTO14_1 (PPG14_1) DA0 37 32 22 J4 P45 R J TIOB0_0 RTO15_1 (PPG14_1) DA1 38 33 23 L3 INITX B C 39 34 24 L4 P46 P S

Document Number: 001-98941 Rev.*B Page 18 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 X0A 40 35 25 K4 P47 Q T X1A 41 36 26 K5 P48 O U VREGCTL 42 37 27 K6 P49 O U VWAKEUP 43 38 28 L5 VBAT - - 44 39 29 L6 C - - 45 40 30 L7 VSS - - 46 41 31 K7 VCC - - 47 42 32 J6 P4B E I TIOB1_0 SCS7_1 MAD03_0 48 43 33 J7 P4C N I TIOB2_0 SCK7_1 (SCL7_1) AIN1_2 MAD04_0 49 44 34 J8 P4D N K TIOB3_0 SOT7_1 (SDA7_1) BIN1_2 INT13_2 MAD05_0 50 45 35 K8 P4E I Q TIOB4_0 SIN7_1 ZIN1_2 FRCK1_1 INT11_1 WKUP2 MAD06_0 51 - - H6 P70 E I TIOA4_2 AIN0_1 IC13_1 TX0_0

Document Number: 001-98941 Rev.*B Page 19 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 52 - - H7 P71 E K TIOB4_2 BIN0_1 IC12_1 INT15_1 RX0_0 53 - - G7 P72 E K TIOA6_0 SIN2_0 ZIN0_1 IC11_1 INT14_2 54 - - H8 P73 E K TIOB6_0 SOT2_0 (SDA2_0) IC10_1 INT03_2 55 - - J9 P74 E I SCK2_0 (SCL2_0) DTTI1X_1 56 46 36 L8 PE0 C E MD1 57 47 37 K9 MD0 J D 58 48 38 L9 PE2 A A X0 59 49 39 L10 PE3 A B X1 60 50 40 L11 VSS - - 61 51 - K11 VCC - - 62 52 41 J10 P10 F M AN00 SIN1_1 FRCK0_2 INT02_1 MAD07_0 RX1_2 63 53 42 H10 P11 F L AN01 SOT1_1 (SDA1_1) IC00_2 MAD08_0 TX1_2

Document Number: 001-98941 Rev.*B Page 20 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 64 54 43 H9 P12 F L AN02 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1 MAD09_0 65 55 44 G10 P13 F M AN03 SIN0_1 IC02_2 INT03_1 MAD10_0 66 56 45 G9 P14 F L AN04 SOT0_1 (SDA0_1) IC03_2 MAD11_0 67 57 46 G8 P15 F L AN05 SCK0_1 (SCL0_1) MAD12_0 ZIN2_2 RTO22_0 68 58 47 F10 P16 F M AN06 SIN2_2 INT14_1 MAD13_0 BIN2_2 RTO21_0 69 59 48 F9 P17 F P AN07 SOT2_2 (SDA2_2) WKUP3 MAD14_0 AIN2_2 RTO20_0 70 60 49 J11 AVCC - - 71 61 50 H11 AVSS - - 72 62 51 G11 AVRL - - 73 63 52 F11 AVRH - -

Document Number: 001-98941 Rev.*B Page 21 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 74 64 53 F8 P18 F L AN08 SCK2_2 (SCL2_2) MAD15_0 DTTI2X_0 75 65 54 E11 P19 F M AN09 SIN4_1 IC00_1 INT05_1 MAD16_0 76 66 55 E10 P1A M L AN10 SOT4_1 (SDA4_1) IC01_1 MAD17_0 77 67 56 E9 P1B M L AN11 SCK4_1 (SCL4_1) IC02_1 MAD18_0 78 68 - E8 P1C F L AN12 CTS4_1 IC03_1 MAD19_0 79 69 - D10 P1D F L AN13 RTS4_1 DTTI0X_1 MAD20_0 80 70 - D9 P1E F L AN14 ADTG_5 FRCK0_1 MAD21_0 81 - - F7 P1F E I ADTG_4 TIOB6_2 RTO05_1 (PPG04_1)

Document Number: 001-98941 Rev.*B Page 22 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 82 - - E7 P27 E K TIOA6_2 RTO04_1 (PPG04_1) INT02_2 83 - - D8 P26 E I TIOB5_0 SCK2_1 (SCL2_1) RTO03_1 (PPG02_1) 84 - - C9 P25 E I TIOA5_0 SOT2_1 (SDA2_1) RTO02_1 (PPG02_1) TX1_0 85 - - B10 P24 E K SIN2_1 RTO01_1 (PPG00_1) INT01_2 RX1_0 86 71 57 D11 P23 F L AN15 TIOA7_1 SCK0_0 (SCL0_0) RTO00_1 (PPG00_1) - MAD22_0 87 72 C10 P22 F L CROUT_0 AN16 TIOB7_1 SOT0_0 (SDA0_0) - ZIN1_1

58 RTO23_0

SIN0_0 - BIN1_1

59 INT06_1

• MAD23_0

59 RTO24_0

Document Number: 001-98941 Rev.*B Page 23 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 89 74 - B11 P20 F M AN18 AIN1_1 INT05_0 MAD24_0 RTO25_0 90 75 60 A11 VSS - - 91 76 61 A10 VCC - - 92 77 62 B9 P0E L I TIOB5_2 SCS6_1 IC13_0 MDQM1_0 93 78 63 A9 P0D L I TIOA5_2 SCK6_1 (SCL6_1) IC12_0 MDQM0_0 94 79 64 C8 P0C L I TIOA6_1 SOT6_1 (SDA6_1) IC11_0 MALE_0 95 80 65 B8 P0B L K TIOB6_1 SIN6_1 IC10_0 INT00_1 MCSX0_0 96 81 66 A8 P0A L K SIN1_0 FRCK1_0 INT12_2 MCSX1_0

Document Number: 001-98941 Rev.*B Page 24 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 97 82 P09 M N AN19 - TRACED0 TIOA3_2 SOT1_0 (SDA1_0) MCSX5_0 IC23_1 98 83 - C7 P08 F N AN20 TRACED1 TIOB3_2 SCK1_0 (SCL1_0) MCSX4_0 IC22_1 99 84 - B7 P07 M N AN21 TRACED2 TIOA0_2 SCK7_0 (SCL7_0) MCLKOUT_0 IC21_1 100 85 - A7 P06 F N AN22 TRACED3 TIOB0_2 SOT7_0 (SDA7_0) MCSX3_0 IC20_1 101 86 - D6 P05 F O AN23 ADTG_0 TRACECLK SIN7_0 INT01_1 MCSX2_0 FRCK2_1 102 87 68 B6 P04 E G TDO SWO 103 88 69 C6 P03 E G TMS SWDIO

Document Number: 001-98941 Rev.*B Page 25 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 104 89 70 C5 P02 E H TDI MCSX6_0 105 90 71 B5 P01 E G TCK SWCLK 106 91 72 A5 P00 E H TRSTX MCSX7_0 107 92 - A6 VSS - - 108 - - E6 P68 E K TIOB7_2 SCK3_0 (SCL3_0) INT00_2 109 - - E5 P67 E I TIOA7_2 SOT3_0 (SDA3_0) 110 - - D5 P66 E K ADTG_8 SIN3_0 INT11_2 111 - - D4 P65 E I TIOB7_0 SCK5_1 (SCL5_1) 112 - - C4 P64 E K TIOA7_0 SOT5_1 (SDA5_1) INT10_2 113 93 73 P63 E K CROUT_1 - - SIN5_1 93 73 INT03_0 MWEX_0 IC23_0 RX0_2 114 94 74 C3 P62 I K ADTG_3 SIN5_0 INT04_1 MOEX_0 IC22_0 TX0_2

Document Number: 001-98941 Rev.*B Page 26 of 160 S6E2H4 Series Pin Number Pin Name I/O Circuit Type Pin State Type LQFP120 LQFP100 LQFP80 FBGA121 115 95 75 B3 P61 E I TIOB2_2 SOT5_0 (SDA5_0) RTCCO_0 SUBOUT_0 ZIN2_1 116 96 76 B2 P60 I F TIOA2_2 SCK5_0 (SCL5_0) NMIX WKUP0 MRDY_0 FRCK2_0 117 97 77 A4 VCC - - 118 98 78 A3 P80 E *1 I BIN2_1 IC21_0 119 99 79 A2 P81 E *1 I AIN2_1 IC20_0 120 100 80 A1 VSS - - - - - K10 VSS - - *1 without pullup control register

Document Number: 001-98941 Rev.*B Page 27 of 160 S6E2H4 Series List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 ADC ADTG_0 A/D converter external trigger input pin 101 86 - D6 ADTG_1 7 7 7 E2 ADTG_2 23 18 13 H1 ADTG_3 114 94 74 C3 ADTG_4 81 - - F7 ADTG_5 80 70 - D9 ADTG_6 17 12 12 F2 ADTG_7 35 30 - H5 ADTG_8 110 - - D5 AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 62 52 41 J10 AN01 63 53 42 H10 AN02 64 54 43 H9 AN03 65 55 44 G10 AN04 66 56 45 G9 AN05 67 57 46 G8 AN06 68 58 47 F10 AN07 69 59 48 F9 AN08 74 64 53 F8 AN09 75 65 54 E11 AN10 76 66 55 E10 AN11 77 67 56 E9 AN12 78 68 - E8 AN13 79 69 - D10 AN14 80 70 - D9 AN15 86 71 57 D11 AN16 87 72 58 C10 AN17 88 73 59 C11 AN18 89 74 - B11 AN19 97 82 67 D7 AN20 98 83 - C7 AN21 99 84 - B7 AN22 100 85 - A7 AN23 101 86 - D6 Base Timer TIOA0_0 Base timer ch.0 TIOA pin 32 27 - L2 TIOA0_1 24 19 14 H2 TIOA0_2 99 84 - B7 TIOB0_0 Base timer ch.0 TIOB pin 37 32 22 J4 TIOB0_1 14 9 9 E1 TIOB0_2 100 85 - A7

Document Number: 001-98941 Rev.*B Page 28 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Base Timer TIOA1_0 Base timer ch.1 TIOA pin 33 28 - J3 TIOA1_1 25 20 15 H3 TIOA1_2 5 5 5 D2 TIOB1_0 Base timer ch.1 TIOB pin 47 42 32 J6 TIOB1_1 15 10 10 F4 TIOB1_2 6 6 6 D3 Base Timer TIOA2_0 Base timer ch.2 TIOA pin 34 29 - J5 TIOA2_1 26 21 16 H4 TIOA2_2 116 96 76 B2 TIOB2_0 Base timer ch.2 TIOB pin 48 43 33 J7 TIOB2_1 16 11 11 F3 TIOB2_2 115 95 75 B3 Base Timer TIOA3_0 Base timer ch.3 TIOA pin 35 30 - H5 TIOA3_1 27 22 17 J1 TIOA3_2 97 82 67 D7 TIOB3_0 Base timer ch.3 TIOB pin 49 44 34 J8 TIOB3_1 17 12 12 F2 TIOB3_2 98 83 - C7 Base Timer TIOA4_0 Base timer ch.4 TIOA pin 36 31 21 K3 TIOA4_1 28 23 18 J2 TIOA4_2 51 - - H6 TIOB4_0 Base timer ch.4 TIOB pin 50 45 35 K8 TIOB4_1 18 13 - F1 TIOB4_2 52 - - H7 Base Timer TIOA5_0 Base timer ch.5 TIOA pin 84 - - C9 TIOA5_1 29 24 19 K2 TIOA5_2 93 78 63 A9 TIOB5_0 Base timer ch.5 TIOB pin 83 - - D8 TIOB5_1 19 14 - G1 TIOB5_2 92 77 62 B9 Base Timer TIOA6_0 Base timer ch.6 TIOA pin 53 - - G7 TIOA6_1 94 79 64 C8 TIOA6_2 82 - - E7 TIOB6_0 Base timer ch.6 TIOB pin 54 - - H8 TIOB6_1 95 80 65 B8 TIOB6_2 81 - - F7 Base Timer TIOA7_0 Base timer ch.7 TIOA pin 112 - - C4 TIOA7_1 86 71 57 D11 TIOA7_2 109 - - E5 TIOB7_0 Base timer ch.7 TIOB pin 111 - - D4 TIOB7_1 87 72 58 C10 TIOB7_2 108 - - E6

Document Number: 001-98941 Rev.*B Page 29 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Debugger SWCLK Serial wire debug interface clock input pin 105 90 71 B5 SWDIO Serial wire debug interface data input / output pin 103 88 69 C6 SWO Serial wire viewer output pin 102 87 68 B6 TCK JTAG test clock input pin 105 90 71 B5 TDI JTAG test data input pin 104 89 70 C5 TDO JTAG debug data output pin 102 87 68 B6 TMS JTAG test mode state input/output pin 103 88 69 C6 TRACECLK Trace CLK output pin of ETM 101 86 - D6 TRACED0 Trace data output pin of ETM 97 82 - D7 TRACED1 98 83 - C7 TRACED2 99 84 - B7 TRACED3 100 85 - A7 TRSTX JTAG test reset Input pin 106 91 72 A5 External Bus MAD00_0 External bus interface address bus 27 22 17 J1 MAD01_0 28 23 18 J2 MAD02_0 29 24 19 K2 MAD03_0 47 42 32 J6 MAD04_0 48 43 33 J7 MAD05_0 49 44 34 J8 MAD06_0 50 45 35 K8 MAD07_0 62 52 41 J10 MAD08_0 63 53 42 H10 MAD09_0 64 54 43 H9 MAD10_0 65 55 44 G10 MAD11_0 66 56 45 G9 MAD12_0 67 57 46 G8 MAD13_0 68 58 47 F10 MAD14_0 69 59 48 F9 MAD15_0 74 64 53 F8 MAD16_0 75 65 54 E11 MAD17_0 76 66 55 E10 MAD18_0 77 67 56 E9 MAD19_0 78 68 - E8 MAD20_0 79 69 - D10 MAD21_0 80 70 - D9 MAD22_0 86 71 - D11 MAD23_0 88 73 - C11 MAD24_0 89 74 - B11

Document Number: 001-98941 Rev.*B Page 30 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 External Bus MCSX0_0 External bus interface chip select output pin 95 80 65 B8 MCSX1_0 96 81 66 A8 MCSX2_0 101 86 - D6 MCSX3_0 100 85 - A7 MCSX4_0 98 83 - C7 MCSX5_0 97 82 67 D7 MCSX6_0 104 89 70 C5 MCSX7_0 106 91 72 A5 MCSX8_0 35 30 - H5 MADATA00_0 External bus interface data bus (Address / data multiplex bus) 2 2 2 C1 MADATA01_0 3 3 3 C2 MADATA02_0 4 4 4 D1 MADATA03_0 5 5 5 D2 MADATA04_0 6 6 6 D3 MADATA05_0 7 7 7 E2 MADATA06_0 8 8 8 E3 MADATA07_0 9 9 9 E4 MADATA08_0 10 10 10 F5 MADATA09_0 11 11 11 F6 MADATA10_0 12 12 12 G5 MADATA11_0 13 13 - G6 MADATA12_0 14 14 - E1 MADATA13_0 15 15 - F4 MADATA14_0 16 16 - F3 MADATA15_0 17 17 - F2 MDQM0_0 External bus interface byte mask signal output pin 93 78 63 A9 MDQM1_0 92 77 62 B9 MALE_0 External bus interface Address Latch enable output signal for multiplex 94 79 64 C8 MRDY_0 External bus interface external RDY input signal 116 96 76 B2 MCLKOUT_0 External bus interface external clock output pin 99 84 - B7 MNALE_0 External bus interface ALE signal to control NAND Flash output pin 18 - - F1 MNCLE_0 External bus interface CLE signal to control NAND Flash output pin 19 - - G1 MNREX_0 External bus interface read enable signal to control NAND Flash 21 - - G3 MNWEX_0 External bus interface write enable signal to control NAND Flash 20 - - G2 MOEX_0 External bus interface read enable signal for SRAM 114 94 74 C3 MWEX_0 External bus interface write enable signal for SRAM 113 93 73 B4

Document Number: 001-98941 Rev.*B Page 31 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 External Bus MSDCLK_0 SDRAM interface SDRAM clock output pin 23 18 - H1 MSDCKE_0 SDRAM interface SDRAM clock enable pin 24 19 - H2 MRASX_0 SDRAM interface SDRAM row address strobe pin 25 20 - H3 MCASX_0 SDRAM interface SDRAM column address strobe pin 26 21 - H4 MSDWEX_0 SDRAM interface SDRAM write enable pin 34 29 - J5 External Interrupt INT00_0 External interrupt request 00 input pin 2 2 2 C1 INT00_1 95 80 65 B8 INT00_2 108 - - E6 INT01_0 External interrupt request 01 input pin 3 3 3 C2 INT01_1 101 86 - D6 INT01_2 85 - - B10 INT02_0 External interrupt request 02 input pin 6 6 6 D3 INT02_1 62 52 41 J10 INT02_2 82 - - E7 INT03_0 External interrupt request 03 input pin 113 93 73 B4 INT03_1 65 55 44 G10 INT03_2 54 - - H8 INT04_0 External interrupt request 04 input pin 17 12 12 F2 INT04_1 114 94 74 C3 INT04_2 10 - - F5 INT05_0 External interrupt request 05 input pin 89 74 - B11 INT05_1 75 65 54 E11 INT05_2 21 16 - G3 INT06_1 External interrupt request 06 input pin 88 73 59 C11 INT06_2 22 17 - G4 INT07_1 External interrupt request 07 input pin 11 - - F6 INT07_2 7 7 7 E2 INT08_1 External interrupt request 08 input pin 19 14 - G1 INT08_2 8 8 8 E3 INT09_1 External interrupt request 09 input pin 20 15 - G2 INT09_2 15 10 10 F4 INT10_1 External interrupt request 10 input pin 16 11 11 F3 INT10_2 112 - - C4 INT11_1 External interrupt request 11 input pin 50 45 35 K8 INT11_2 110 - - D5 INT12_1 External interrupt request 12 input pin 32 27 - L2 INT12_2 96 81 66 A8 INT13_1 External interrupt request 13 input pin 33 28 - J3 INT13_2 49 44 34 J8 INT14_1 External interrupt request 14 input pin 68 58 47 F10 INT14_2 53 - - G7 INT15_1 External interrupt request 15 input pin 52 - - H7 INT15_2 14 9 9 E1

Document Number: 001-98941 Rev.*B Page 32 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 External Interrupt NMIX Non-Maskable Interrupt input pin 116 96 76 B2 GPIO P00 General-purpose I/O port 0 106 91 72 A5 P01 105 90 71 B5 P02 104 89 70 C5 P03 103 88 69 C6 P04 102 87 68 B6 P05 101 86 - D6 P06 100 85 - A7 P07 99 84 - B7 P08 98 83 - C7 P09 97 82 67 D7 P0A 96 81 66 A8 P0B 95 80 65 B8 P0C 94 79 64 C8 P0D 93 78 63 A9 P0E 92 77 62 B9 P10 General-purpose I/O port 1 62 52 41 J10 P11 63 53 42 H10 P12 64 54 43 H9 P13 65 55 44 G10 P14 66 56 45 G9 P15 67 57 46 G8 P16 68 58 47 F10 P17 69 59 48 F9 P18 74 64 53 F8 P19 75 65 54 E11 P1A 76 66 55 E10 P1B 77 67 56 E9 P1C 78 68 - E8 P1D 79 69 - D10 P1E 80 70 - D9 P1F 81 - - F7 P20 General-purpose I/O port 2 89 74 - B11 P21 88 73 59 C11 P22 87 72 58 C10 P23 86 71 57 D11 P24 85 - - B10 P25 84 - - C9 P26 83 - - D8 P27 82 - - E7

Document Number: 001-98941 Rev.*B Page 33 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 GPIO P30 General-purpose I/O port 3 14 9 9 E1 P31 15 10 10 F4 P32 16 11 11 F3 P33 17 12 12 F2 P34 18 13 - F1 P35 19 14 - G1 P36 20 15 - G2 P37 21 16 - G3 P38 22 17 - G4 P39 23 18 13 H1 P3A 24 19 14 H2 P3B 25 20 15 H3 P3C 26 21 16 H4 P3D 27 22 17 J1 P3E 28 23 18 J2 P3F 29 24 19 K2 P40 General-purpose I/O port 4 32 27 - L2 P41 33 28 - J3 P42 34 29 - J5 P43 35 30 - H5 P44 36 31 21 K3 P45 37 32 22 J4 P46 39 34 24 L4 P47 40 35 25 K4 P48 41 36 26 K5 P49 42 37 27 K6 P4B 47 42 32 J6 P4C 48 43 33 J7 P4D 49 44 34 J8 P4E 50 45 35 K8 P50 General-purpose I/O port 5 2 2 2 C1 P51 3 3 3 C2 P52 4 4 4 D1 P53 5 5 5 D2 P54 6 6 6 D3 P55 7 7 7 E2 P56 8 8 8 E3 P57 9 - - E4 P58 10 - - F5 P59 11 - - F6 P5A 12 - - G5 P5B 13 - - G6

Document Number: 001-98941 Rev.*B Page 34 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 GPIO P60 General-purpose I/O port 6 116 96 76 B2 P61 115 95 75 B3 P62 114 94 74 C3 P63 113 93 73 B4 P64 112 - - C4 P65 111 - - D4 P66 110 - - D5 P67 109 - - E5 P68 108 - - E6 P70 General-purpose I/O port 7 51 - - H6 P71 52 - - H7 P72 53 - - G7 P73 54 - - H8 P74 55 - - J9 P80 General-purpose I/O port 8 118 98 78 A3 P81 119 99 79 A2 PE0 General-purpose I/O port E 56 46 36 L8 PE2 58 48 38 L9 PE3 59 49 39 L10 Multi- function Serial 0 SIN0_0 Multi-function serial interface ch.0 input pin 88 73 59 C11 SIN0_1 65 55 44 G10 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). 87 72 58 C10 SOT0_1 (SDA0_1) 66 56 45 G9 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SCL0 when it is used in an I2C (operation mode 4). 86 71 57 D11 SCK0_1 (SCL0_1) 67 57 46 G8 Multi- function Serial 1 SIN1_0 Multi-function serial interface ch.1 input pin 96 81 66 A8 SIN1_1 62 52 41 J10 SOT1_0 (SDA1_0) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). 97 82 67 D7 SOT1_1 (SDA1_1) 63 53 42 H10 SCK1_0 (SCL1_0) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I2C (operation mode 4). 98 83 - C7 SCK1_1 (SCL1_1) 64 54 43 H9

Document Number: 001-98941 Rev.*B Page 35 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Multi- function Serial 2 SIN2_0 Multi-function serial interface ch.2 input pin 53 - - G7 SIN2_1 85 - - B10 SIN2_2 68 58 47 F10 SOT2_0 (SDA2_0) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). 54 - - H8 SOT2_1 (SDA2_1) 84 - - C9 SOT2_2 (SDA2_2) 69 59 48 F9 SCK2_0 (SCL2_0) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I2C (operation mode 4). 55 - - J9 SCK2_1 (SCL2_1) 83 - - D8 SCK2_2 (SCL2_2) 74 64 53 F8 Multi- function Serial 3 SIN3_0 Multi-function serial interface ch.3 input pin 110 - - D5 SIN3_1 15 10 10 F4 SOT3_0 (SDA3_0) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). 109 - - E5 SOT3_1 (SDA3_1) 16 11 11 F3 SCK3_0 (SCL3_0) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I2C (operation mode 4). 108 - - E6 SCK3_1 (SCL3_1) 17 12 12 F2

Document Number: 001-98941 Rev.*B Page 36 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Multi- function Serial 4 SIN4_0 Multi-function serial interface ch.4 input pin 6 6 6 D3 SIN4_1 75 65 54 E11 SIN4_2 10 - - F5 SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). 5 5 5 D2 SOT4_1 (SDA4_1) 76 66 55 E10 SOT4_2 (SDA4_2) 11 - - F6 SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I2C (operation mode 4). 4 4 4 D1 SCK4_1 (SCL4_1) 77 67 56 E9 SCK4_2 (SCL4_2) 12 - - G5 CTS4_0 Multi-function serial interface ch.4 CTS input pin 2 2 2 C1 CTS4_1 78 68 - E8 CTS4_2 13 - - G6 RTS4_0 Multi-function serial interface ch.4 RTS output pin 3 3 3 C2 RTS4_1 79 69 - D10 RTS4_2 14 9 9 E1 Multi- function Serial 5 SIN5_0 Multi-function serial interface ch.5 input pin 114 94 74 C3 SIN5_1 113 - - B4 SIN5_2 20 15 - G2 SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). 115 95 75 B3 SOT5_1 SOT5_2 (SDA5_2) 21 16 - G3 SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation modes 2) and as SCL5 when it is used in an I2C (operation mode 4). 116 96 76 B2 SCK5_1 SCK5_2 (SCL5_2) 22 17 - G4

Document Number: 001-98941 Rev.*B Page 37 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Multi- function Serial 6 SIN6_0 Multi-function serial interface ch.6 input pin 7 7 7 E2 SIN6_1 95 80 65 B8 SOT6_0 (SDA6_0) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). 8 8 8 E3 SOT6_1 (SDA6_1) 94 79 64 C8 SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I2C (operation mode 4). 9 - - E4 SCK6_1 (SCL6_1) 93 78 63 A9 SCS6_1 Multi-function serial interface ch.6 serial chip select pin 92 77 62 B9 Multi- function Serial 7 SIN7_0 Multi-function serial interface ch.7 input pin 101 86 - D6 SIN7_1 50 45 35 K8 SOT7_0 (SDA7_0) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). 100 85 - A7 SOT7_1 (SDA7_1) 49 44 34 J8 SCK7_0 (SCL7_0) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation modes 2) and as SCL7 when it is used in an I2C (operation mode 4). 99 84 - B7 SCK7_1 (SCL7_1) 48 43 33 J7 SCS7_1 Multi-function serial interface ch.7 serial chip select pin 47 42 32 J6

Document Number: 001-98941 Rev.*B Page 38 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Multi- function Timer 0 DTTI0X_0 Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 23 18 13 H1 DTTI0X_1 79 69 - D10 FRCK0_0 16-bit free-run timer ch.0 external clock input pin 18 13 - F1 FRCK0_1 80 70 - D9 FRCK0_2 62 52 41 J10 IC00_0 16-bit input capture ch.0 input pin of Multi-function timer 0. ICxx describes channel number. 22 17 - G4 IC00_1 75 65 54 E11 IC00_2 63 53 42 H10 IC01_0 21 16 - G3 IC01_1 76 66 55 E10 IC01_2 64 54 43 H9 IC02_0 20 15 - G2 IC02_1 77 67 56 E9 IC02_2 65 55 44 G10 IC03_0 19 14 - G1 IC03_1 78 68 - E8 IC03_2 66 56 45 G9 RTO00_0 (PPG00_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 24 19 14 H2 RTO00_1 (PPG00_1) 86 71 57 D11 RTO01_0 (PPG00_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 25 20 15 H3 RTO01_1 (PPG00_1) 85 - - B10 RTO02_0 (PPG02_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 26 21 16 H4 RTO02_1 RTO03_0 (PPG02_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 27 22 17 J1 RTO03_1 RTO04_0 (PPG04_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 28 23 18 J2 RTO04_1 RTO05_0 (PPG04_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 29 24 19 K2 RTO05_1

Document Number: 001-98941 Rev.*B Page 39 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Multi- function Timer 1 DTTI1X_0 Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 8 8 8 E3 DTTI1X_1 55 - - J9 FRCK1_0 16-bit free-run timer ch.1 external clock input pin 96 81 66 A8 FRCK1_1 50 45 35 K8 IC10_0 16-bit input capture ch.1 input pin of Multi-function timer 1. ICxx describes channel number. 95 80 65 B8 IC10_1 54 - - H8 IC11_0 94 79 64 C8 IC11_1 53 - - G7 IC12_0 93 78 63 A9 IC12_1 52 - - H7 IC13_0 92 77 62 B9 IC13_1 51 - - H6 RTO10_0 (PPG10_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 2 2 2 C1 RTO10_1 (PPG10_1) 32 27 - L2 RTO11_0 (PPG10_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 3 3 3 C2 RTO11_1 (PPG10_1) 33 28 - J3 RTO12_0 (PPG12_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 4 4 4 D1 RTO12_1 (PPG12_1) 34 29 - J5 RTO13_0 (PPG12_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 5 5 5 D2 RTO13_1 (PPG12_1) 35 30 - H5 RTO14_0 (PPG14_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 6 6 6 D3 RTO14_1 (PPG14_1) 36 31 21 K3 RTO15_0 (PPG14_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 7 7 7 E2 RTO15_1 (PPG14_1) 37 32 22 J4

Document Number: 001-98941 Rev.*B Page 40 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Multi- function Timer 2 DTTI2X_0 Input signal controlling wave form generator outputs RTO20 to RTO25 of Multi-function timer 2. 74 64 53 F8 DTTI2X_1 15 10 10 F4 FRCK2_0 16-bit free-run timer ch.2 external clock input pin 116 96 76 B2 FRCK2_1 101 86 - D6 IC20_0 16-bit input capture ch.2 input pin of Multi-function timer 2. ICxx describes channel number. 119 99 79 A2 IC20_1 100 85 - A7 IC21_0 118 98 78 A3 IC21_1 99 84 - B7 IC22_0 114 94 74 C3 IC22_1 98 83 - C7 IC23_0 113 93 73 B4 IC23_1 97 82 67 D7 RTO20_0 (PPG20_0) Wave form generator output pin of Multi-function timer 2. This pin operates as PPG10 when it is used in PPG2 output modes. 69 59 48 F9 RTO20_1 (PPG20_1) 9 - - E4 RTO21_0 (PPG20_0) Wave form generator output pin of Multi-function timer 2. This pin operates as PPG20 when it is used in PPG2 output modes. 68 58 47 F10 RTO21_1 RTO22_0 (PPG22_0) Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. 67 57 46 G8 RTO22_1 RTO23_0 (PPG22_0) Wave form generator output pin of Multi-function timer 2. This pin operates as PPG22 when it is used in PPG2 output modes. 87 72 58 C10 RTO23_1 RTO24_0 (PPG24_0) Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. 88 73 59 C11 RTO24_1 RTO25_0 (PPG24_0) Wave form generator output pin of Multi-function timer 2. This pin operates as PPG24 when it is used in PPG2 output modes. 89 74 - B11 RTO25_1 (PPG24_1) 14 9 9 E1 Quadrature Position/ Revolution Counter 0 AIN0_0 QPRC ch.0 AIN input pin 24 19 14 H2 AIN0_1 51 - - H6 AIN0_2 2 2 2 C1 BIN0_0 QPRC ch.0 BIN input pin 25 20 15 H3 BIN0_1 52 - - H7 BIN0_2 3 3 3 C2 ZIN0_0 QPRC ch.0 ZIN input pin 26 21 16 H4 ZIN0_1 53 - - G7 ZIN0_2 4 4 4 D1

Document Number: 001-98941 Rev.*B Page 41 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Quadrature Position/ Revolution Counter 1 AIN1_0 QPRC ch.1 AIN input pin 10 - - F5 AIN1_1 89 74 - B11 AIN1_2 48 43 33 J7 BIN1_0 QPRC ch.1 BIN input pin 11 - - F6 BIN1_1 88 73 - C11 BIN1_2 49 44 34 J8 ZIN1_0 QPRC ch.1 ZIN input pin 12 - - G5 ZIN1_1 87 72 - C10 ZIN1_2 50 45 35 K8 Quadrature Position/ Revolution Counter 2 AIN2_0 QPRC ch.2 AIN input pin 33 28 - J3 AIN2_1 119 99 79 A2 AIN2_2 69 59 48 F9 BIN2_0 QPRC ch.2 BIN input pin 34 29 - J5 BIN2_1 118 98 78 A3 BIN2_2 68 58 47 F10 ZIN2_0 QPRC ch.2 ZIN input pin 35 30 - H5 ZIN2_1 115 95 75 B3 ZIN2_2 67 57 46 G8 Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock 115 95 75 B3 RTCCO_1 64 54 43 H9 RTCCO_2 23 18 13 H1 SUBOUT_0 Sub clock output pin 115 95 75 B3 SUBOUT_1 64 54 43 H9 SUBOUT_2 23 18 13 H1 Low-Power Consumption Mode WKUP0 Deep standby mode return signal input pin 0 116 96 76 B2 WKUP1 Deep standby mode return signal input pin 1 14 9 9 E1 WKUP2 Deep standby mode return signal input pin 2 50 45 35 K8 WKUP3 Deep standby mode return signal input pin 3 69 59 48 F9 DAC DA0 D/A converter ch.0 analog output pin 36 31 21 K3 DA1 D/A converter ch.1 analog output pin 37 32 22 J4 VBAT VREGCTL On-board regulator control pin 41 36 26 K5 VWAKEUP The return signal input pin from a hibernation state 42 37 27 K6 CAN0 TX0_0 CAN interface ch.0 TX output pin 51 - - H6 TX0_1 18 13 - F1 TX0_2 114 94 74 C3 RX0_0 CAN interface ch.0 RX input pin 52 - - H7 RX0_1 19 14 - G1 RX0_2 113 93 73 B4 CAN1 TX1_0 CAN interface ch.1 TX output pin 84 - - C9 TX1_1 12 - - G5 TX1_2 63 53 42 H10 RX1_0 CAN interface ch.1 RX input pin 85 - - B10 RX1_1 11 - - F6 RX1_2 62 52 41 J10

Document Number: 001-98941 Rev.*B Page 42 of 160 S6E2H4 Series Pin Function Pin Name Function Description Pin No LQFP 120 LQFP 100 LQFP FBGA 121 Reset INITX External Reset Input pin. A reset is valid when INITX=L. 38 33 23 L3 Mode MD1 Mode 1 pin. During serial programming to Flash memory, MD1=L must be input. 56 46 36 L8 MD0 Mode 0 pin. During normal operation, MD0=L must be input. During serial programming to Flash memory, MD0=H must be input. 57 47 37 K9 Power VCC Power supply Pin 1 1 1 B1 31 26 - K1 46 41 31 K7 61 51 - K11 91 76 61 A10 117 97 77 A4 GND VSS GND Pin 107 92 - A6 30 25 20 L1 45 40 30 L7 60 50 40 L11 90 75 60 A11 120 100 80 A1 - - - K10 Clock X0 Main clock (oscillation) input pin 58 48 38 L9 X1 Main clock (oscillation) I/O pin 59 49 39 L10 X0A Sub clock (oscillation) input pin 39 34 24 L4 X1A Sub clock (oscillation) I/O pin 40 35 25 K4 CROUT_0 Built-in high-speed CR-osc clock output port 87 72 58 C10 CROUT_1 113 93 73 B4 ADC Power AVCC A/D converter and D/A converter analog power supply pin 70 60 49 J11 AVRL A/D converter analog reference voltage input pin 72 62 51 G11 AVRH A/D converter analog reference voltage input pin 73 63 52 F11 VBAT Power VBAT VBAT power supply pin. Backup power supply (battery etc.) and system power supply. 43 38 28 L5 ADC GND AVSS A/D converter and D/A converter GND pin 71 61 50 H11 C pin C Power supply stabilization capacity pin 44 39 29 L6 Notes: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.

Document Number: 001-98941 Rev.*B Page 43 of 160 S6E2H4 Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected. − Oscillation feedback resistor : Approximately 1MΩ − With Standby mode control When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA B − CMOS level hysteresis input − Pull-up resistor : Approximately 50 kΩ P-chP-ch N-ch R R P-chP-ch N-ch Standby mode control Digital input Standby mode control Digital output Digital output Clock input Digital input Standby mode control Pull-up resistor control Pull-up resistor control Digital output Digital output Pull-up resistor Digital input

Document Number: 001-98941 Rev.*B Page 44 of 160 S6E2H4 Series Type Circuit Remarks C − Open drain output − CMOS level hysteresis input E − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is always off. F − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is always off. N-ch P-chP-ch N-ch R P-chP-ch N-ch R Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

Document Number: 001-98941 Rev.*B Page 45 of 160 S6E2H4 Series Type Circuit Remarks G − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -12 mA, IOL = 12 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is always off. I − CMOS level output − CMOS level hysteresis input − 5V tolerant − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − Available to control of PZR registers. J CMOS level hysteresis input P-chP-ch N-ch R P-chP-ch N-ch R Standby mode control Pull-up resistor control Digital input Digital output Digital output Standby mode control Pull-up resistor control Digital input Digital output Digital output Mode input

Document Number: 001-98941 Rev.*B Page 46 of 160 S6E2H4 Series Type Circuit Remarks L − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -8 mA, IOL = 8 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is always off. M − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -8 mA, IOL = 8 mA P-chP-ch N-ch R P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

Document Number: 001-98941 Rev.*B Page 47 of 160 S6E2H4 Series Type Circuit Remarks N − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA (GPIO) − IOL = 20 mA (Fast Mode Plus) − When this pin is used as an I2C pin, the digital output P-ch transistor is always off. O − CMOS level output − CMOS level hysteresis input − 5 V tolerant − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual P-chP-ch N-ch R P-ch P-ch N-ch R Digital output Digital output Digital input Pull-up resistor control Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control

Document Number: 001-98941 Rev.*B Page 48 of 160 S6E2H4 Series Type Circuit Remarks P − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual Q It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. − Oscillation feedback resistor : Approximately 10 MΩ − With Standby mode control − When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual P-ch P-ch N-ch R P-ch P-ch N-ch R RX Digital output Digital output Digital input Pull-up resistor control Standby mode control OSC X0A X1A Digital output Digital output Digital input Pull-up resistor control Standby mode control OSC Standby mode control Clock input

Document Number: 001-98941 Rev.*B Page 49 of 160 S6E2H4 Series Type Circuit Remarks R − CMOS level output − CMOS level hysteresis input − Analog output − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -12 mA, IOL = 12 mA (4.5 V to 5.5 V) − IOH = -8 mA, IOL = 8 mA (2.7 V to 4.5 V) P-ch N-ch R P-ch Pull-up resistor control Digital input Standby mode control Analog output Digital output Digital output

Document Number: 001-98941 Rev.*B Page 50 of 160 S6E2H4 Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins sho uld be connected through an appropriate resistance to a power supply pin or ground pin. Code: DS00-00004-3E

Document Number: 001-98941 Rev.*B Page 51 of 160 S6E2H4 Series Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions.

Document Number: 001-98941 Rev.*B Page 52 of 160 S6E2H4 Series Lead-Free Packaging CAUTION: When ball grid array (FBGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

Document Number: 001-98941 Rev.*B Page 53 of 160 S6E2H4 Series

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments inv olving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf

Document Number: 001-98941 Rev.*B Page 54 of 160 S6E2H4 Series 7. Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. Power Supply Pins A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.  Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF  Lead type Load capacitance: Approximately 6 pF to 7 pF

Document Number: 001-98941 Rev.*B Page 55 of 160 S6E2H4 Series Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Handling when Using Multi-function Serial Pin as I2C Pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Set as External clock input Device C VSS CS GND

Document Number: 001-98941 Rev.*B Page 56 of 160 S6E2H4 Series Notes on Power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on: VBAT → VCC VCC → AVCC → AVRH Turning off: VCC → VBAT AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features among the Products with Different Memory Sizes and between Flash Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Adjoining Wiring on Circuit Board If wiring of the crystal oscillation circuit X1A adjoins and also runs in parallel with the wiring of P48/VREGCTL, there is a possibility that the oscillation erroneously counts because X1A has noise with the change of P48/VREGCTL. Keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. Handling when Using Debug Pins When debug pins(TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input. P47/ X1A P48/ VREGCTL Ground P46/ X0A P49/ VWAKEUP Not allowed to run both wirings in parallel Insert the ground pattern Device

Document Number: 001-98941 Rev.*B Page 57 of 160 S6E2H4 Series 8. Block Diagram *: For the S6E2H44E0A and S6E2H46E0A, ETM is not available. Cortex-M4 Core @160 MHz(Max) MainFlash I/F Clock Reset Generator Dual-Timer Watchdog Timer (Hardware) DMAC 8ch. Watch Counter Unit 0 CSV External Interrupt Controller 16pin + NMI Power-On Reset SRAM0 16/32 Kbytes AHB-APB Bridge : APB1 (Max 160 MHz) SRAM1 8/16 Kbytes AHB-APB Bridge: APB0(Max 80 MHz) I D Sys CLK S6E2H44E/F/G, S6E2H46E/F/G AHB-APB Bridge : APB2 (Max 80 MHz) NVIC Watchdog Timer (Software) Security Unit 1 TRSTX,TCK, TDI,TMS TRACEDx, TRACECLK AVCC, AVSS, AVRH ANxx TIOAx TIOBx C TDO X0A X1A SCKx SINx SOTx INTx NMIX P0x, P1x, PEx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator CRC Accelerator AHB-AHB Bridge ADTGx RTS4 CTS4 MADx MADATAx MainFlash

512 Kbytes/

256 Kbytes

8ch. HW flow control(ch.4) External Bus I/F GPIO PIN-Function-Ctrl LVD Multi-layer AHB (Max 160 MHz) TPIU* ROM Table ETM*SWJ-DP Main Osc PLL CR 100 kHz LVD Ctrl Base Timer 16-bit 16ch./ 32-bit 8ch. Peripheral Clock Gating Low-speed CR Prescaler RTCCO, SUBOUT Deep Standby Ctrl WKUPx 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. A/D Activation Compare 6ch. 16-bit PPG 3ch. DTTI0X FRCK0 QPRC 3ch.BINx ZINx IC0x RTO0x AINx 12-bit A/D Converter Multi-function Timer × 3 MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT,MSDWEX, MSDCLK,MSDCKE, MRASX,MCASX Waveform Generator 3ch. MPUFPU 12-bit D/A Converter 2units SRAM2 8/16 Kbytes WorkFlash

32 KbytesWorkFlash I/F

(16 Kbytes) DSTC CAN CAN TX0, RX0 TX1, RX1 CAN Prescaler VREGCTL VWAKEUP Unit 2 DAx Real-Time Clock Port Ctrl. Sub Osc VBAT Domain VBAT Domain CR

4 MHz

Document Number: 001-98941 Rev.*B Page 58 of 160 S6E2H4 Series 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0x4007_0000 0x4006_F000 GPIO 0xFFFF_FFFF 0xE010_0000 0xE000_0000 0x4006_3000 CAN ch.1 0x4006_2000 CAN ch.0 0xD000_0000 0x4006_1000 DSTC 0x4006_0000 DMAC 0x4004_0000 0x4003_F000 EXT-bus I/F 0x6000_0000 0x4400_0000 0x4003_C800 0x4003_C100 Peripheral Clock Gating 0x4200_0000 0x4003_C000 Low Speed CR Prescaler 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter 0x4000_0000 0x4003_9000 CRC 0x4003_8000 MFS 0x4003_7000 CAN prescaler 0x2400_0000 0x4003_6000 Reserved 0x4003_5000 LVD/DS mode 0x2200_0000 0x4003_4000 0x4003_3000 0x4003_2000 0x2010_0000 0x4003_1000 Int-Req.Read 0x200E_0000 Work Flash I/F 0x4003_0000 EXTI 0x200C_0000 Work Flash 0x4002_F000 Reserved 0x4002_E000 CR Trim 0x2004_4000 0x2004_0000 SRAM2 0x2003_C000 SRAM1 0x4002_8000 0x2000_0000 Reserved 0x4002_7000 A/DC 0x1FFF_8000 SRAM0 0x4002_6000 QPRC 0x0050_0000 Reserved 0x4002_5000 Base Timer 0x0040_0000 Security/CR Trim 0x4002_4000 PPG 0x4002_3000 Reserved 0x4002_2000 MFT Unit2 0x4002_1000 MFT Unit1 0x0000_0000 0x4002_0000 MFT Unit0 0x4001_6000 0x4001_5000 Dual Timer 0x4001_3000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 MainFlash I/F Reserved Reg. Area Reserved External Device Area

32 Mbytes

See "Memory Map(2)" for the memory size details. Reserved Reserved MainFlash Reserved Reserved Cortex-M4 Private Peripherals Peripherals Reserved

Document Number: 001-98941 Rev.*B Page 59 of 160 S6E2H4 Series Memory Map (2) S6E2H46E0A S6E2H46F0A S6E2H46G0A S6E2H44E0A S6E2H44F0A S6E2H44G0A 0x2020_0000 0x2020_0000 0x200C_8000 0x200C_8000 0x200C_0000 0x200C_0000 0x2004_4000 0x2004_2000 0x2004_0000 0x2004_0000 0x2003_E000 0x2003_C000 0x2000_0000 0x2000_0000 0x1FFF_C000 0x1FFF_8000 0x0040_6000 0x0040_6000 0x0040_4000 0x0040_4000 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security 0x0008_0000 0x0004_0000 0x0000_0000 0x0000_0000 SRAM2

16 Kbytes

512 Kbytes

32 Kbytes

8 Kbytes

Document Number: 001-98941 Rev.*B Page 60 of 160 S6E2H4 Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB MainFlash I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_1FFF Multi-function timer unit1 0x4002_2000 0x4002_2FFF Multi-function timer unit2 0x4002_3000 0x4003_FFFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_4FFF Reserved 0x4003_3000 0x4003_3FFF D/A Converter 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF Reserved 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF RTC/Port Ctrl 0x4003_C000 0x4003_C0FF Low-speed CR Prescaler 0x4003_C100 0x4003_C7FF Peripheral Clock Gating 0x4003_C800 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External Memory interface 0x4004_0000 0x4005_FFFF AHB Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF DSTC register 0x4006_2000 0x4006_2FFF CAN ch.0 0x4006_3000 0x4006_3FFF CAN ch.1 0x4006_4000 0x4006_EFFF Reserved 0x4006_F000 0x4006_FFFF GPIO 0x4006_7000 0x41FF_FFFF Reserved 0x200E_0000 0x200E_FFFF WorkFlash I/F register

Document Number: 001-98941 Rev.*B Page 61 of 160 S6E2H4 Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the L level.  INITX=1 This is the period when the INITX pin is the H level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.  Setting prohibition Prohibition of a setting by specification limitation.

Document Number: 001-98941 Rev.*B Page 62 of 160 S6E2H4 Series List of Pin Status Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at 0 / or Input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled

Document Number: 001-98941 Rev.*B Page 63 of 160 S6E2H4 Series Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected F NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state G JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected H JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected I Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected

Document Number: 001-98941 Rev.*B Page 64 of 160 S6E2H4 Series Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - J Analog output selected Setting disabled Setting disabled Setting disabled Maintain previous state *2 *3 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected K External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected L Analog input selected Hi-Z Hi-Z / Internal input fixedat 0 / Analog input enabled Hi-Z / Internal input fixedat 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected

Document Number: 001-98941 Rev.*B Page 65 of 160 S6E2H4 Series Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - M Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected N Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected

Document Number: 001-98941 Rev.*B Page 66 of 160 S6E2H4 Series Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - O Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External interrupt enabled selected Maintain previous state Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected P Analog input selected Hi-Z Hi-Z / Internal input fixedat 0 / Analog input enabled Hi-Z / Internal input fixedat 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected

Document Number: 001-98941 Rev.*B Page 67 of 160 S6E2H4 Series Pin status Type Function Group Power-on Reset or Low-voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - Q WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep standby RTC mode, and Deep standby Stop mode. *2: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.

Document Number: 001-98941 Rev.*B Page 68 of 160 S6E2H4 Series List of VBAT Domain Pin Status VBAT Pin Status Type Function Group VBAT Power-on reset INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Sode or Deep Standby Stop Mode State Return from Deep Standby Mode State VBAT RTC Mode State Return from VBAT RTC Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 - - ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - - - S GPIO selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting prohibitio n Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state Maintain previous state T GPIO selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting prohibitio n External sub clock input selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state /When oscillatio n stops, Hi-Z* Maintain previous state /When oscillation stops, Hi-Z* Maintain previous state /When oscillation stops, Hi-Z* Maintain previous state /When oscillation stops, Hi-Z* Maintain previous state Maintain previous state Maintain previous state U Resource selected Hi-Z Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected *: When The SOSCNTL bit in the WTOSCCNT Register is 0, Sub crystal oscillator output pin is maintain previous state. When The SOSCNTL bit in the WTOSCCNT Register is 1, Oscillation is stopped at Stop mode and Deep standby Stop mode.

Document Number: 001-98941 Rev.*B Page 69 of 160 S6E2H4 Series 12. Electrical Characteristics

12.1 Absolute Maximum Ratings

Power supply voltage *1, *2 VCC VSS - 0.5 VSS + 6.5 V Power supply voltage (VBAT) *1 ,*3 VBAT VSS - 0.5 VSS + 6.5 V Analog power supply voltage *1 ,*4 AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage *1 ,*4 AVRH VSS - 0.5 VSS + 6.5 V Input voltage *1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V VSS - 0.5 VSS + 6.5 V 5 V tolerant Analog pin input voltage *1 VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5 V) V Output voltage *1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V "L" level maximum output current *5 IOL - 10 mA 4 mA type 20 mA 8 mA type 20 mA 12 mA type 22.4 mA I2C Fm+ "L" level average output current *6 IOLAV - 4 mA 4 mA type 8 mA 8 mA type 12 mA 12 mA type 20 mA I2C Fm+ "L" level total maximum output current ∑IOL - 100 mA "L" level total average output current *7 ∑IOLAV - 50 mA "H" level maximum output current *5 IOH - - 10 mA 4 mA type 20 mA 8 mA type - 20 mA 12 mA type "H" level average output current *6 IOHAV - - 4 mA 4 mA type 8 mA 8 mA type - 12 mA 12 mA type "H" level total maximum output current ∑IOH - - 100 mA "H" level total average output current *7 ∑IOHAV - - 50 mA Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: VBAT must not drop below VSS - 0.5 V. *4: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100-ms period. *7: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100-ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

Document Number: 001-98941 Rev.*B Page 70 of 160 S6E2H4 Series

12.2 Recommended Operating Conditions

Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 2.7*4 5.5 V Power supply voltage (VBAT) VBAT - 2.7 5.5 V Analog power supply voltage AVCC - 2.7 5.5 V AVCC=VCC Analog reference voltage AVRH - *3 AVCC V Smoothing capacitor CS - 1 10 μF for built-in regulator *1 Operating temperature Junction temperature TJ - - 40 + 125 °C Ambient temperature TA - - 40 *2 °C *1: See "●C pin" in "Handling Devices" for the connection of the smoothing capacitor. *2: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (TJ). The calculation formula of the ambient temperature (TA) is shown below. TA (Max) = TJ (Max) - Pd(Max) × θja Pd: Power dissipation (W) θja: Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage *3 :The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See 12.5 12-bit A/D Converter for the details. *4: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table for Package Thermal Resistance and Maximum Permissible Power Package Printed Circuit Board Thermal Resistance θja (°C/W) Maximum Permissible Power (mW) TA=+85°C TA=+105°C LQH080 (0.5-mm pitch) Single-layered both sides 82 488 244 4 layers 56 714 357 LQI100 (0.5-mm pitch) Single-layered both sides 59 678 339 4 layers 39 1026 513 LQM120 (0.5-mm pitch) Single-layered both sides 71 563 282 4 layers 50 800 400 FDI121 (0.5-mm pitch) Single-layered both sides 63 635 317 4 layers 37 1081 540 WARNING: 1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Document Number: 001-98941 Rev.*B Page 71 of 160 S6E2H4 Series Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT): Current consumed in internal logic and memory, etc. through regulator ΣICC(IO): Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by "(1) Current Rating" in "3. DC Characteristics" (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) × VCC × fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Symbol Conditions Capacitance Value Pin internal load capacitance CINT 4 mA type 1.93 pF 8 mA type 3.45 pF 12 mA type 3.42 pF Calculate ICC (Max) as follows when the power dissipation can be evaluated by yourself. 1. Measure current value ICC (Typ) at normal temperature (+25°C). 2. Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) Parameter Symbol Conditions Current Value Maximum leak current at operating ICC(leak_max) TJ = +125°C 16.8 mA TJ = +105°C 8.6 mA TJ = +85°C 5.8 mA

Document Number: 001-98941 Rev.*B Page 72 of 160 S6E2H4 Series Current Explanation Diagram A V ・・・ ・・・ ・・・ V A A Regulator Logic Flash RAM ICC ICC(INT) ΣICC(IO) IOL VOL VOH IOH ICC(IO) Chip VCC CEXT Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH)) ICC = ICC(INT)＋ΣICC(IO)

Document Number: 001-98941 Rev.*B Page 73 of 160 S6E2H4 Series

12.3 DC Characteristics

12.3.1 Current Rating

Table 12-1 Typical and Maximum Current Consumption in Normal Operation(PLL), Code Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Enabled) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL) *5, *6 *9

160 MHz 51 71

144 MHz 47 67

120 MHz 39 59

100 MHz 33 53

80 MHz 27 47

60 MHz 20 40

40 MHz 14 34

20 MHz 7.6 28 8 MHz 3.9 24 4 MHz 2.7 23

160 MHz 30 51

144 MHz 28 48

120 MHz 23 43

100 MHz 20 40

80 MHz 16 36

60 MHz 12 32

40 MHz 8.7 29 20 MHz 5.0 25 8 MHz 2.8 23 4 MHz 2.1 22 Table 12-2 Typical and Maximum Current Consumption in Normal Operation(PLL), Code with Data Accessing Running from Flash Memory (Flash Accelerator Mode and Trace Buffer Function Disabled) Parameter Symbol Pin Name Conditions Frequency*7 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL) *8 *9

160 MHz 56 76

144 MHz 51 71

120 MHz 43 63

100 MHz 37 57

80 MHz 30 50

60 MHz 23 43

40 MHz 16 36

20 MHz 8.5 29 8 MHz 4.3 25 4 MHz 2.9 23

120 MHz 24 44

100 MHz 20 41

80 MHz 17 37

60 MHz 13 33

40 MHz 9.2 30 20 MHz 5.3 26 8 MHz 3.0 23 4 MHz 2.2 23 *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are fixed.

Document Number: 001-98941 Rev.*B Page 74 of 160 S6E2H4 Series *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to MainFlash memory *7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK *8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0) *9: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit) Table 12-3 Typical and Maximum Current Consumption in Normal Operation(PLL), Code with Data Accessing Running from Flash Memory (Flash 0 wait-cycle Mode and Read Access 0 wait) Parameter Symbol Pin Name Conditions Frequency*4 (MHz) Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL) *5 *6

72 MHz 38 58

60 MHz 33 53

48 MHz 28 48

36 MHz 22 42

24 MHz 16 36

12 MHz 9.5 30 8 MHz 6.9 27 4 MHz 4.2 25

72 MHz 29 49

60 MHz 26 46

48 MHz 22 42

36 MHz 18 38

24 MHz 13 33

12 MHz 7.8 28 8 MHz 5.8 26 4 MHz 3.7 24 *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) *6: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)

Document Number: 001-98941 Rev.*B Page 75 of 160 S6E2H4 Series Table 12-4 Typical and Maximum Current Consumption in Normal Operation(other than PLL), Code with Data Accessing Running from Flash Memory (Flash 0 wait-cycle Mode and Read Access 0 wait) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (main oscillation) *5*6 4 MHz 4.0 24 mA When all peripheral clocks are ON 3.2 24 mA When all peripheral clocks are OFF Normal operation (built-in high-speed CR) *5 4 MHz 3.2 24 mA When all peripheral clocks are ON 2.7 23 mA When all peripheral clocks are OFF Normal operation (sub oscillation) *5 32 kHz 0.34 21 mA When all peripheral clocks are ON 0.30 21 mA When all peripheral clocks are OFF Normal operation (built-in low-speed CR) *5 100 kHz 0.36 21 mA When all peripheral clocks are ON 0.33 21 mA When all peripheral clocks are OFF *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) *6: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)

Document Number: 001-98941 Rev.*B Page 76 of 160 S6E2H4 Series Table 12-5 Typical and Maximum Current Consumption in Sleep Operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation *6 (PLL)

160 MHz 35 55

144 MHz 32 52

120 MHz 27 47

100 MHz 23 43

80 MHz 18 39

60 MHz 14 34

40 MHz 9.9 30 20 MHz 5.5 26 8 MHz 3.1 23 4 MHz 2.3 23

160 MHz 14 35

144 MHz 13 33

120 MHz 11 31

100 MHz 9.5 30 80 MHz 7.8 28 60 MHz 6.3 27 40 MHz 4.6 25 20 MHz 2.9 23 8 MHz 2.2 23 4 MHz 2.0 22

Document Number: 001-98941 Rev.*B Page 77 of 160 S6E2H4 Series Table 12-6 Typical and Maximum Current Consumption in Sleep Operation(PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK Parameter Symbol Pin Name Conditions Frequency*5 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation *6 (PLL)

72 MHz 23 43

60 MHz 19 39

48 MHz 16 36

36 MHz 12 32

24 MHz 8.5 29 12 MHz 5.1 25 8 MHz 3.9 24 4 MHz 2.7 23 72 MHz 8.8 29 mA When all peripheral clocks are OFF 60 MHz 7.6 28 48 MHz 6.3 27 36 MHz 5.1 25 24 MHz 3.9 24 12 MHz 2.7 23 8 MHz 2.3 23 4 MHz 1.9 22 *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *6: When using the crystal oscillator of 4 MHz (including the current consumption of the oscillation circuit)

Document Number: 001-98941 Rev.*B Page 78 of 160 S6E2H4 Series Table 12-7 Typical and Maximum Current Consumption in Sleep Operation(other than PLL), when PCLK0 = PCLK1 = PCLK2 = HCLK/2 *1: TA=+25°C, VCC=3.3 V *2: TJ=+125°C, VCC=5.5 V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When using the crystal oscillator of 4 M Hz (including the current consumption of the oscillation circuit) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation *5 (main oscillation) 4MHz 2.1 22 mA When all peripheral clocks are ON 1.3 22 mA When all peripheral clocks are OFF Sleep operation (built-in high-speed CR) 1.3 22 mA When all peripheral clocks are ON 0.8 21 mA When all peripheral clocks are OFF Sleep operation (sub oscillation) 32 kHz 0.28 21 mA When all peripheral clocks are ON 0.27 21 mA When all peripheral clocks are OFF Sleep operation (built-in low-speed CR) 100 kHz 0.29 21 mA When all peripheral clocks are ON 0.28 21 mA When all peripheral clocks are OFF

Document Number: 001-98941 Rev.*B Page 79 of 160 S6E2H4 Series Table 12-8 Typical and Maximum Current Consumption in Stop Mode, Timer Mode and RTC Mode *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are fixed. *4: When LVD is OFF *5: When using the crystal oscillator of 4 M Hz (including the current consumption of the oscillation circuit) Parameter Symbol Pin Name Conditions Frequency Value Unit Remarks Typ*1 Max*2 Power supply current ICCH VCC Stop mode - TA=+25°C - 7.6 mA *3, *4 TA=+85°C - 10 mA *3, *4 TA=+105°C ICCT Timer mode *5 (main oscillation) 4 MHz 1.4 2.1 mA *3, *4 TA=+25°C - 8.8 mA *3, *4 TA=+85°C - 11 mA *3, *4 TA=+105°C Timer mode (built-in high-speed CR) 0.49 1.2 mA *3, *4 TA=+25°C - 7.9 mA *3, *4 TA=+85°C - 11 mA *3, *4 TA=+105°C Timer mode (sub oscillation) 32 kHz TA=+25°C - 7.6 mA *3, *4 TA=+85°C - 10 mA *3, *4 TA=+105°C Timer mode (built-in low-speed CR) 100 kHz TA=+25°C - 7.6 mA *3, *4 TA=+85°C - 10 mA *3, *4 TA=+105°C ICCR RTC mode (sub oscillation) 32 kHz TA=+25°C - 7.6 mA *3, *4 TA=+85°C - 10 mA *3, *4 TA=+105°C

Document Number: 001-98941 Rev.*B Page 80 of 160 S6E2H4 Series Table 12-9 Typical and Maximum Current Consumption in Deep Standby Stop Mode, Deep Standby RTC Mode and VBAT *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are fixed. *4: When LVD is OFF *5: When sub oscillation is OFF *6: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit) Parameter Symbol Pin Name Conditions Frequency Value Unit Remarks Typ*1 Max*2 Power supply current ICCHD VCC Deep standby Stop mode (When RAM is OFF) 24 40 µA *3, *4 TA=+25°C - 640 µA *3, *4 TA=+85°C - 813 µA *3, *4 TA=+105°C Deep standby Stop mode (When RAM is ON) 41 146 µA *3, *4 TA=+25°C - 1616 µA *3, *4 TA=+85°C - 2059 µA *3, *4 TA=+105°C ICCRD Deep standby RTC mode (When RAM is OFF) 32kHz 24 40 µA *3, *4 TA=+25°C - 640 µA *3, *4 TA=+85°C - 813 µA *3, *4 TA=+105°C Deep standby RTC mode (When RAM is ON) 41 146 µA *3, *4 TA=+25°C - 1616 µA *3, *4 TA=+85°C - 2059 µA *3, *4 TA=+105°C ICCVBAT VBAT RTC stop TA=+25°C TA=+85°C TA=+105°C RTC operation 1.3 2.4 µA *3, *4 TA=+25°C - 6.2 µA *3, *4 TA=+85°C - 12 µA *3, *4 TA=+105°C

Document Number: 001-98941 Rev.*B Page 81 of 160 S6E2H4 Series Table 12-10 Typical and Maximum Current Consumption in Low-voltage Detection Circuit, Main Flash Memory Write/erase Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC At operation - 4 7 μA For occurrence of interrupt Main flash memory write/erase current ICCFLASH At Write/Erase - 13.4 15.9 mA Work flash memory write/erase current ICCWFLASH At Write/Erase - 11.5 13.6 mA *1 1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power supply current (ICC). Table 12-11 Peripheral Current Dissipation Clock System Peripheral Unit Frequency (MHz) Unit Remarks 40 80 160 HCLK GPIO All ports 0.16 0.32 0.62 mA TA=+25°C, VCC=3.3 V DMAC - 0.68 1.35 2.63 DSTC - 0.93 1.88 3.65 External bus I/F - 0.17 0.34 0.71 CAN 1ch. 0.01 0.02 0.03 PCLK1 Base timer 4ch. 0.18 0.37 0.73 mA TA=+25°C, VCC=3.3 V Multi-functional timer/PPG 1unit/4ch. 0.61 1.22 2.43 Quadrature position/Revolution counter 1unit 0.04 0.07 0.14 A/DC 1unit 0.22 0.44 0.88 PCLK2 Muli-function serial 1ch. 0.30 0.60 - mA TA=+25°C, VCC=3.3 V

Document Number: 001-98941 Rev.*B Page 82 of 160 S6E2H4 Series

12.3.2 Pin Characteristics

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max H level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 - VCC×0.8 - VCC + 0.3 V

5 V tolerant

input pin - VCC×0.8 - VSS + 5.5 V Input pin doubled as I2C Fm+ - VCC×0.7 - VSS + 5.5 V L level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 - VSS - 0.3 - VCC×0.2 V input pin - VSS - 0.3 - VCC×0.2 V Input pin doubled as I2C Fm+ - VSS - VCC×0.3 V H level output voltage VOH 4 mA type VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 2 mA 8 mA type VCC ≥ 4.5 V, IOH = - 8 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 4 mA 12 mA type VCC ≥ 4.5 V, IOH = - 12 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 8 mA The pin doubled as I2C Fm+ VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V At GPIO VCC < 4.5 V, IOH = - 3 mA

Document Number: 001-98941 Rev.*B Page 83 of 160 S6E2H4 Series Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max L level output voltage VOL 4 mA type VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA 8 mA type VCC ≥ 4.5 V, IOH = 8 mA VSS - 0.4 V VCC < 4.5 V, IOH = 4 mA 12 mA type VCC ≥ 4.5 V, IOL = 12 mA VSS - 0.4 V VCC < 4.5 V, IOL = 8 mA The pin doubled as I2C Fm+ VCC ≥ 4.5 V, IOH = 4 mA VSS - 0.4 V At GPIO VCC < 4.5 V, IOH = 3 mA VCC ≤ 5.5 V, IOH = 20 mA At I2C Fm+ Input leak current IIL - - - 5 - + 5 μA Pull-up resistor value RPU Pull-up pin VCC ≥ 4.5 V 25 50 100 kΩ VCC < 4.5 V 30 80 200 Input capacitance CIN Other than VCC, VBAT, VSS, AVCC, AVSS, AVRH - - 5 15 pF

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12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 4.5 V 4 48 MHz When crystal oscillator is connected VCC < 4.5 V 4 20 VCC ≥ 4.5 V 4 48 MHz When using external clock VCC < 4.5 V 4 20 Input clock cycle tCYLH VCC ≥ 4.5 V 20.83 250 ns When using external clock VCC < 4.5 V 50 250 Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF, tCR - - 5 ns When using external clock Internal operating clock*1 frequency fCC - - - 160 MHz Base clock (HCLK/FCLK) fCP0 - - - 80 MHz APB0 bus clock*2 fCP1 - - - 160 MHz APB1 bus clock*2 fCP2 - - - 80 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 6.25 - ns Base clock (HCLK/FCLK) tCYCP0 - - 12.5 - ns APB0 bus clock*2 tCYCP1 - - 6.25 - ns APB1 bus clock*2 tCYCP2 - - 12.5 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part(MN709-00001). *2: For about each APB bus which each peripheral is connected to, see 8. Block Diagram in this data sheet.

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12.4.2 Sub Clock Input Characteristics

(VBAT = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Input frequency 1/ tCYLL X0A, X1A - - 32.76 8 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock

12.4.3 Built-in CR Oscillation Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH TJ = -20°C to + 105°C 3.92 4 4.08 MHz When trimming*1 TJ = - 40°C to + 125°C 3.88 4 4.12 Clock frequency fCRH TJ = - 40°C to + 125°C 2.9 4 5 When not trimming Frequency Stabilization time tCRWT - - - 30 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use high-speed CR clock as source clock. Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbo l Condition Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz X0A VBAT VBAT VBAT VBAT 0.8 × VBAT

Document Number: 001-98941 Rev.*B Page 86 of 160 S6E2H4 Series

12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency fPLLO 200 - 320 MHz Main PLL clock frequency*2 fCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part(MN709-00001). 12.4.5 Operating Conditions of Main PLL (In the Case of Using Built-in High-speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 50 - 75 multiplier PLL macro oscillation clock frequency fPLLO 190 - 320 MHz Main PLL clock frequency*2 fCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM4 Family Peripheral Manual Main part(MN709-00001). Note: − Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed.

12.4.6 Reset Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Condition Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns

Document Number: 001-98941 Rev.*B Page 87 of 160 S6E2H4 Series

12.4.7 Power-on Reset Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Max Power supply rising time tVCCR VCC 0 - ms Power supply shut down time tOFF 1 - ms Time until releasing Power-on reset tPRT 0.33 0.60 ms 0.2V VDH_minimum VCC_minimum tPRT Internal RST VCC CPU Operation start RST Active Release tVCCR 0.2V 0.2V tOFF Glossary  VCC_minimum: Minimum VCC of recommended operating conditions.  VDH_minimum: Minimum detection voltage of Low-Voltage detection reset. See 8. Low-Voltage Detection Characteristics.

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12.4.8 GPIO Output Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Output frequency tPCYCLE Pxx* VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz *: GPIO is a target. Pxx tPCYCLE

Document Number: 001-98941 Rev.*B Page 89 of 160 S6E2H4 Series

12.4.9 External Bus Timing

External Bus Clock Output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT*1 VCC ≥ 4.5 V - 50*2 MHz VCC < 4.5 V - 32*3 MHz *1: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see Chapter 14: External Bus Interface in FM4 Family Peripheral Manual Main part(MN709-00001). *2: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 100 MHz. *3: Generate MCLKOUT at setting more than 4 division when the AHB bus clock exceeds 64 MHz. External Bus Signal Input/output Characteristics (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V 0.8 × Vcc0.8 × Vcc tCYCLE VIH VIL VIL VIH VOH VOL VOL VOH MCLK Signal input Signal output

Document Number: 001-98941 Rev.*B Page 90 of 160 S6E2H4 Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max MOEX Mininum pulse width tOEW MOEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MCSX↓→Address output delay time tCSL – AV MCSX[7:0], MAD[24:0] VCC ≥ 4.5 V -9 +9 ns VCC < 4.5 V -12 +12 MOEX↑→Address hold time tOEH - AX MOEX, MAD[24:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX↓→ MOEX↓ delay time tCSL - OEL MOEX, MCSX[7:0] VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MOEX↑→ MCSX↑ time tOEH - CSH VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX↓→MDQM↓ delay time tCSL - RDQML MCSX, MDQM[1:0] VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 Data set up→MOEX↑ time tDS - OE MOEX, MADATA[15:0] VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 38 - MOEX↑→ Data hold time tDH - OE MOEX, MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MWEX Mininum pulse width tWEW MWEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MWEX↑→Address output delay time tWEH - AX MWEX, MAD[24:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX↓→MWEX↓ delay time tCSL - WEL MWEX, MCSX[7:0] VCC ≥ 4.5 V MCLK×n-9 MCLK×n+9 ns VCC < 4.5 V MCLK×n-12 MCLK×n+12 MWEX↑→MCSX↑ delay time tWEH - CSH VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX↓→MDQM↓ delay time tCSL-WDQML MCSX, MDQM[1:0] VCC ≥ 4.5 V MCLK×n-9 MCLK×n+9 ns VCC < 4.5 V MCLK×n-12 MCLK×n+12 MWEX↓→ Data output time tCSL-DX MCSX, MADATA[15:0] VCC ≥ 4.5 V MCLK-9 MCLK+9 ns VCC < 4.5 V MCLK-12 MCLK+12 MWEX↑→ Data hold time tWEH - DX MWEX, MADATA[15:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16)

Document Number: 001-98941 Rev.*B Page 91 of 160 S6E2H4 Series Invalid Address tCSL-OEL tCSL-AV RD Address WD tDH-OEtDS-OE tWEH-DX tOEW tOEH-AX tOEH-CSH tWEW tCYCLE tCSL-WEL tCSL-AV tWEH-CSH tWEH-AX tCSL-WDQMLtCSL-RDQML tCSL-DX MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

Document Number: 001-98941 Rev.*B Page 92 of 160 S6E2H4 Series Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Address delay time tAV MCLK, MAD[24:0] VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 MCSX delay time tCSL MCLK, MCSX[7:0] VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 tCSH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 MOEX delay time tREL MCLK, MOEX VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 tREH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 Data set up →MCLK↑ time tDS MCLK, MADATA[15:0] VCC ≥ 4.5 V 19 - ns VCC < 4.5 V 37 MCLK↑→ Data hold time tDH MCLK, MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MWEX delay time tWEL MCLK, MWEX VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 tWEH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 MDQM[1:0] delay time tDQML MCLK, MDQM[1:0] VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 tDQMH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 MCLK↑→ Data output time tODS MCLK, MADATA[15:0] VCC ≥ 4.5 V MCLK+1 MCLK+18 ns VCC < 4.5 V MCLK+24 MCLK↑→ Data hold time tOD MCLK, MADATA[15:0] VCC ≥ 4.5 V 1 18 ns VCC < 4.5 V 24 Note: − When the external load capacitance CL = 30 pF

Document Number: 001-98941 Rev.*B Page 93 of 160 S6E2H4 Series Invalid tDQML tREH Address tCSL tAV tREL RD Address WD tDQMH tWEHtWEL tDHtDS tOD tAV tCSH tCYCLE tDQML tDQMH tODS MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

Document Number: 001-98941 Rev.*B Page 94 of 160 S6E2H4 Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Multiplexed address delay time tALE-CHMADV MALE, MADATA[15:0] VCC ≥ 4.5 V 0 10 ns VCC < 4.5 V 20 Multiplexed address hold time tCHMADH VCC ≥ 4.5 V MCLK×n+0 MCLK×n+10 ns VCC < 4.5 V MCLK×n+0 MCLK×n+20 Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

Document Number: 001-98941 Rev.*B Page 95 of 160 S6E2H4 Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK, ALE VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 ns tCHAH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 ns MCLK↑→ Multiplexed address delay time tCHMADV MCLK, MADATA[15:0] VCC ≥ 4.5 V 1 tOD ns VCC < 4.5 V MCLK↑→ Multiplexed data output time tCHMADX VCC ≥ 4.5 V 1 tOD ns VCC < 4.5 V Note: − When the external load capacitance CL = 30 pF MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

Document Number: 001-98941 Rev.*B Page 96 of 160 S6E2H4 Series NAND Flash Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max MNREX Min pulse width tNREW MNREX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V Data set up →MNREX↑ time tDS – NRE MNREX, MADATA[15:0] VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 38 - MNREX↑→ Data hold time tDH – NRE MNREX, MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MNALE↑→ MNWEX delay time tALEH - NWEL MNALE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNALE↓→ MNWEX delay time tALEL - NWEL MNALE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNCLE↑→ MNWEX delay time tCLEH - NWEL MNCLE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MNWEX Min pulse width tNWEW MNWEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MNWEX↓→ Data output time tNWEL – DV MNWEX, MADATA[15:0] VCC ≥ 4.5 V - 9 + 9 ns VCC < 4.5 V -12 +12 MNWEX↑→ Data hold time tNWEH – DX MNWEX, MADATA[15:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16) NAND Flash Read MCLK MNREX MADATA[15:0] Read

Document Number: 001-98941 Rev.*B Page 97 of 160 S6E2H4 Series NAND Flash Address Write NAND Flash Command Write MCLK MNALE MNCLE MADATA[15:0] MNWEX Write MCLK MNALE MNCLE MADATA[15:0] MNWEX Write

Document Number: 001-98941 Rev.*B Page 98 of 160 S6E2H4 Series External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max MCLK↑ MRDY input setup time tRDYI MCLK, MRDY VCC ≥ 4.5 V 19 - ns VCC < 4.5 V 37  When RDY is input  When RDY is released

• · · Over 2cycle tRDYI 2 cycle tRDYI 0.5×VCC MCLK Original MOEX MWEX MRDY MCLK Extended MOEX MWEX MRDY

Document Number: 001-98941 Rev.*B Page 99 of 160 S6E2H4 Series SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin Name Value Unit Min Max Output frequency tCYCSD MSDCLK - 32 MHz Address delay time tAOSD MSDCLK, MAD[15:0] 2 12 ns MSDCLK↑→Data output delay time tDOSD MSDCLK, MADATA[31:0] 2 12 ns MSDCLK↑→Data output Hi-Z time tDOZSD MSDCLK, MADATA[31:0] 2 20 ns MDQM[1:0] delay time tWROSD MSDCLK, MDQM[1:0] 1 12 ns MCSX delay time tMCSSD MSDCLK, MCSX8 2 12 ns MRASX delay time tRASSD MSDCLK, MRASX 2 12 ns MCASX delay time tCASSD MSDCLK, MCASX 2 12 ns MSDWEX delay time tMWESD MSDCLK, MSDWEX 2 12 ns MSDCKE delay time tCKESD MSDCLK, MSDCKE 2 12 ns Data set up time tDSSD MSDCLK, MADATA[31:0] 23 - ns Data hold time tDHSD MSDCLK, MADATA[31:0] 0 - ns Note: − When the external load capacitance CL = 30 pF

Document Number: 001-98941 Rev.*B Page 100 of 160 S6E2H4 Series RD WD MSDCLK MDQM[1:0] MCSX MRASX MCASX MSDWEX MSDCKE MADATA[15:0] Address MADATA[15:0] MAD[24:0] tCYCSD tAOSD tWROSD tMCSSD tRASSD tCASSD tMWESD tCKESD tDOSD tDOZSD tDSSD tDHSD SDRAM Access

Document Number: 001-98941 Rev.*B Page 101 of 160 S6E2H4 Series

12.4.10 Base Timer Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet. tTIWH VIHS VIHS VILS VILS tTIWL tTRGH VIHS VIHS VILS VILS tTRGL ECK TIN TGIN

Document Number: 001-98941 Rev.*B Page 102 of 160 S6E2H4 Series

12.4.11 CSIO Timing

Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 103 of 160 S6E2H4 Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI t SLSH t SHSL V IH t F tR V IH V OH V IH V IL V IL V OL V IH V IL V IH V IL t SLOVE t IVSHE t SHIXE SCK SOT SIN SCK SOT SIN

Document Number: 001-98941 Rev.*B Page 104 of 160 S6E2H4 Series Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 105 of 160 S6E2H4 Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI t SHSL t SLSH V IH tF tR V IH V OH V IL V IL V IL V OL V IH V IL V IH V IL t SHOVE t IVSLE t SLIXE SCK SOT SIN SCK SOT SIN

Document Number: 001-98941 Rev.*B Page 106 of 160 S6E2H4 Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 107 of 160 S6E2H4 Series MS bit = 0 MS bit = 1 *: Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR t SLSH t SHSL t SHOVE V IL V IL V IH V IH V IH V OH V OL V OH V OL V IH V IL V IH V IL t IVSLE t SLIXE SCK SOT SIN SCK SOT SIN

Document Number: 001-98941 Rev.*B Page 108 of 160 S6E2H4 Series Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 109 of 160 S6E2H4 Series MS bit = 0 MS bit = 1 tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI t SHSL tR t SLSH tF t SLOVE V IL V IL V IL V IH V IH V IH V OH V OL V OH V OL V IH V IL V IH V IL t IVSHE t SHIXE SCK SOT SIN SCK SOT SIN

Document Number: 001-98941 Rev.*B Page 110 of 160 S6E2H4 Series When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↓→SCK↓setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SUT delay time tDSE - 40 - 40 ns SCS↑→SUT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part(MN709-00001). − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 111 of 160 S6E2H4 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SOT (SPI=0) SOT (SPI=1) SCK output SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 001-98941 Rev.*B Page 112 of 160 S6E2H4 Series When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↑ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↓→SCK↑setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↓→SOT delay time tDSE - 40 - 40 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part(MN709-00001). − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 113 of 160 S6E2H4 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 001-98941 Rev.*B Page 114 of 160 S6E2H4 Series When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↓ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↑→SCK↓setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part(MN709-00001). − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 115 of 160 S6E2H4 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 001-98941 Rev.*B Page 116 of 160 S6E2H4 Series When Using Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↓ hold time tCSHI (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns SCS deselect time tCSDI (*3)-50 +5tCYCP (*3)+50 +5tCYCP (*3)-50 +5tCYCP (*3)+50 +5tCYCP ns SCS↑→SCK↑setup time tCSSE External shift clock operation 3tCYCP+30 - 3tCYCP+30 - ns SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+30 - 3tCYCP+30 - ns SCS↑→SOT delay time tDSE - 40 - 40 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part(MN709-00001). − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 117 of 160 S6E2H4 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 001-98941 Rev.*B Page 118 of 160 S6E2H4 Series High-speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns 12.5* SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, 5 - 5 - ns SINx SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN4_1, SOT4_1, SCK4_1 − Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 001-98941 Rev.*B Page 119 of 160 S6E2H4 Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI t SLSH t SHSL V IH t F tR V IH V OH V IH V IL V IL V OL V IH V IL V IH V IL t SLOVE t IVSHE t SHIXE SCK SOT SIN SCK SOT SIN

Document Number: 001-98941 Rev.*B Page 120 of 160 S6E2H4 Series High-speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN4_1, SOT4_1, SCK4_1 − Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 001-98941 Rev.*B Page 121 of 160 S6E2H4 Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI t SHSL t SLSH V IH tF tR V IH V OH V IL V IL V IL V OL V IH V IL V IH V IL t SHOVE t IVSLE t SLIXE SCK SOT SIN SCK SOT SIN

Document Number: 001-98941 Rev.*B Page 122 of 160 S6E2H4 Series High-speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN4_1, SOT4_1, SCK4_1 − Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 001-98941 Rev.*B Page 123 of 160 S6E2H4 Series MS bit = 0 MS bit = 1 *: Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR t SLSH t SHSL t SHOVE V IL V IL V IH V IH V IH V OH V OL V OH V OL V IH V IL V IH V IL t IVSLE t SLIXE SCK SOT SIN SCK SOT SIN

Document Number: 001-98941 Rev.*B Page 124 of 160 S6E2H4 Series High-speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Internal shift clock operation tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns 12.5* SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock L pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN4_1, SOT4_1, SCK4_1 − Chip select: SIN6_1, SOT6_1, SCK6_1, SCS6_1 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 001-98941 Rev.*B Page 125 of 160 S6E2H4 Series MS bit = 0 MS bit = 1 tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI t SHSL tR t SLSH tF t SLOVE V IL V IL V IL V IH V IH V IH V OH V OL V OH V OL V IH V IL V IH V IL t IVSHE t SHIXE SCK SOT SIN SCK SOT SIN

Document Number: 001-98941 Rev.*B Page 126 of 160 S6E2H4 Series When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↓→SCK↓setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 127 of 160 S6E2H4 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 001-98941 Rev.*B Page 128 of 160 S6E2H4 Series When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↑ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↓→SCK↑setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part(MN709-00001). − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 129 of 160 S6E2H4 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 001-98941 Rev.*B Page 130 of 160 S6E2H4 Series When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 0, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↓ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↑→SCK↓setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part(MN709-00001). − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 131 of 160 S6E2H4 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 001-98941 Rev.*B Page 132 of 160 S6E2H4 Series When Using High-speed Synchronous Serial Chip Select (SPI = 1, SCINV = 1, MS=0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↓ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20 +5tCYCP (*3)+20 +5tCYCP (*3)-20 +5tCYCP (*3)+20 +5tCYCP ns SCS↑→SCK↑setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which multi-function serial is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part(MN709-00001). − When the external load capacitance CL = 30 pF.

Document Number: 001-98941 Rev.*B Page 133 of 160 S6E2H4 Series tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 001-98941 Rev.*B Page 134 of 160 S6E2H4 Series External Clock (EXT = 1): when in Asynchronous Mode Only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Value Unit Remarks Min Max Serial clock L pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns t SHSL V I L V I L V I L V IH V IH V IH tR tF t SLSH SCK

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12.4.12 External Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP*1 - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP*1 - ns Waveform generator INT00 to INT15, NMIX - 2tCYCP + 100*1 - ns External interrupt, NMI 500*2 - ns WKUPx - 500*3 - ns Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see 8. Block Diagram in this data sheet. *2: When in Stop mode, in timer mode. *3: When in deep standby RTC mode, in deep standby Stop mode.

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12.4.13 Quadrature Position/Revolution Counter Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Min Max AIN pin H width tAHL - 2tCYCP* - ns AIN pin L width tALL - BIN pin H width tBHL - BIN pin L width tBLL - BIN rising time from AIN pin H level tAUBU PC_Mode2 or PC_Mode3 AIN falling time from BIN pin H level tBUAD PC_Mode2 or PC_Mode3 BIN falling time from AIN pin L level tADBD PC_Mode2 or PC_Mode3 AIN rising time from BIN pin L level tBDAU PC_Mode2 or PC_Mode3 AIN rising time from BIN pin H level tBUAU PC_Mode2 or PC_Mode3 BIN falling time from AIN pin H level tAUBD PC_Mode2 or PC_Mode3 AIN falling time from BIN pin L level tBDAD PC_Mode2 or PC_Mode3 BIN rising time from AIN pin L level tADBU PC_Mode2 or PC_Mode3 ZIN pin H width tZHL QCR:CGSC="0" ZIN pin L width tZLL QCR:CGSC="0" AIN/BIN rising and falling time from determined ZIN level tZABE QCR:CGSC="1" Determined ZIN level from AIN/BIN rising and falling time tABEZ QCR:CGSC="1" *: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see "8. Block Diagram" in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

Document Number: 001-98941 Rev.*B Page 137 of 160 S6E2H4 Series BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ZIN ZIN AIN/BIN

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12.4.14 I2C Timing

Standard-mode，Fast-mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency fSCL CL = 30 pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) Start condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs (Repeated) Start condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between Stop condition and Start condition tBUF 4.7 - 1.3 - μs Noise filter tSP

2 MHz ≤

tCYCP<40 MHz 2tCYCP*4 - 2tCYCP*4 - ns

40 MHz ≤

tCYCP<60 MHz 4tCYCP*4 - 4tCYCP*4 - ns

60 MHz ≤

tCYCP<80 MHz 6tCYCP*4 - 6tCYCP*4 - ns

80 MHz ≤

tCYCP<100 MHz 8tCYCP*4 - 8tCYCP*4 - ns

100 MHz ≤

tCYCP<120 MHz 10tCYCP*4 - 10tCYCP*4 - ns

120 MHz ≤

tCYCP<140 MHz 12tCYCP*4 - 12tCYCP*4 - ns

140 MHz ≤

tCYCP<160 MHz 14tCYCP*4 - 14tCYCP*4 - ns

160 MHz ≤

tCYCP<180 MHz 16tCYCP*4 - 16tCYCP*4 - ns 1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. 2: The maximum tHDDAT must not extend beyond the low period (tLOW) of the device’s SCL signal. 3: Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. 4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see 8.Block Diagram in this data sheet. When using Standard-mode, the peripheral bus clock must be set more than 2 MHz. When using Fast-mode, the peripheral bus clock must be set more than 8 MHz. 5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency.

Document Number: 001-98941 Rev.*B Page 139 of 160 S6E2H4 Series Fast Mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Fast Mode Plus (Fm+)*6 Unit Remarks Min Max SCL clock frequency fSCL CL = 30 pF, R = (Vp/IOL)*1 0 1000 kHz (Repeated) Start condition hold time SDA ↓ → SCL ↓ tHDSTA 0.26 - μs SCL clock L width tLOW 0.5 - μs SCL clock H width tHIGH 0.26 - μs (Repeated) Start condition setup time SCL ↑ → SDA ↓ tSUSTA 0.26 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 0.45*2, *3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 50 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 0.26 - μs Bus free time between Stop condition and Start condition tBUF 0.5 - μs Noise filter tSP tCYCP<80 MHz 6 tCYCP*4 - ns tCYCP<100 MHz 8 tCYCP*4 - ns tCYCP<120 MHz 10 tCYCP*4 - ns tCYCP<140 MHz 12 tCYCP*4 - ns tCYCP<160 MHz 14 tCYCP*4 - ns tCYCP<180 MHz 16 tCYCP*4 - ns 1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. 2: The maximum tHDDAT must not extend beyond the low period (tLOW) of the device’s SCL signal. 3: The Fast mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. 4: tCYCP is the APB bus clock cycle time. For more information about the APB bus number to which the I2C is connected, see 8.Block Diagram in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. 5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to the APB bus clock frequency. 6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See Chapter 12: I/O Port in FM4 Family Peripheral Manual Main Part (MN709-00001) for the details.

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12.4.15 ETM Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Data hold tETMH TRACECLK, TRACED[3:0] VCC ≥ 4.5 V 2 9 ns VCC < 4.5 V 2 15 TRACECLK frequency 1/ tTRACE TRACECLK VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz TRACECLK clock cycle tTRACE VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 31.25 - ns Note: − When the external load capacitance CL= 30 pF. HCLK TRACECLK TRACED[3:0]

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12.4.16 JTAG Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V - 25 ns VCC < 4.5 V - 45 Note: − When the external load capacitance CL= 30 pF. TCK TMS/TDI TDO

Document Number: 001-98941 Rev.*B Page 143 of 160 S6E2H4 Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - - ±4.5 LSB AVRH = 2.7 V to 5.5 V Offset calibration when used Differential Nonlinearity - - - - ±2.5 LSB Zero transition voltage VZT ANxx - ±2 ±7 LSB Full-scale transition voltage VFST ANxx - AVRH±2 AVRH±7 LSB Total error - - - ±3 ±8 LSB Conversion time - - 0.5*1 - - μs AVCC ≥ 4.5 V Sampling time *2 tS - 0.15 - 10 μs AVCC ≥ 4.5 V 0.3 - AVCC < 4.5 V Compare clock cycle*3 tCCK - 25 - 1000 ns AVCC ≥ 4.5 V 50 - 1000 AVCC < 4.5 V State transition time to operation permission tSTT - - - 1.0 μs Power supply current (analog + digital) - AVCC - 0.69 0.92 mA A/D 1unit operation - 1.0 18 μA When A/D stop Reference power supply current (AVRH) - AVRH - 1.1 1.97 mA A/D 1unit operation AVRH=5.5 V 0.3 6.3 μA When A/D stop Analog input capacity CAIN - - - 12.05 pF Analog input resistance RAIN - - - 1.2 kΩ AVCC ≥ 4.5 V 1.8 AVCC < 4.5 V Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 5 μA Analog input voltage - ANxx AVSS - AVRH V Reference voltage - AVRH 4.5 - AVCC V Tcck ＜50 ns 2.7 - AVCC Tcck ≥ 50 ns - AVRL AVSS - AVSS V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is when the value of sampling time: 150ns, the value of compare time: 350ns (AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK). For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM4 Family Peripheral Manual Analog macro part(MN709-00001). The register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at Base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2).

Document Number: 001-98941 Rev.*B Page 144 of 160 S6E2H4 Series (Equation 1) tS ≥ (RAIN + Rext ) × CAIN × 9 tS: Sampling time RAIN: Input resistance of A/D = 1.2 kΩ at 4.5 V < AVCC < 5.5 V Input resistance of A/D = 1.8 kΩ at 2.7 V < AVCC < 4.5 V CAIN: Input capacity of A/D = 12.05 pF at 2.7 V < AVCC < 5.5 V Rext: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Rext RAIN CAIN Analog signal source ANxx Analog input pin Comparator

Document Number: 001-98941 Rev.*B Page 145 of 160 S6E2H4 Series Definition of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVss AVRH AVss AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

Document Number: 001-98941 Rev.*B Page 146 of 160 S6E2H4 Series  Total error: A difference between actual value and theoretical value. The overall error includes zero-transition voltage, full-scale transition voltage and linearity error. VFST’=1.5LSB’ Actual conversion characteristics {1LSB’ x (N-1) + 0.5 LSB’} Ideal characterisics VZT’=0.5LSB’ 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF Total error Digital output AVRL AVRHAnalog input VNT (Actually-measured value) Actual conversion characteristics Total error of digital output N = VNT – {1 LSB’ X (N-1) + 0.5 LSB’}

1 LSB’ [LSB]

1 LSB’ (ideal value) = AVRH – AVRL

4096 [V] VZT’ (ideal value) = AVRL + 0.5 LSB’ [V] VFST’ (ideal value) = AVRH - 1.5 LSB’ VNT’: A voltage for causing transition of digital output from (N-1) to N [V]

Document Number: 001-98941 Rev.*B Page 147 of 160 S6E2H4 Series 12.6 12-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7Vto5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - DAx - - 12 bit Conversion time tc20 0.56 0.69 0.81 μs Load 20 pF tc100 2.79 3.42 4.06 μs Load 100 pF Integral Nonlinearity* INL - 16 - + 16 LSB Differential Nonlinearity* DNL - 0.98 - + 1.5 LSB Output voltage offset VOFF - - 10.0 mV When setting 0x000 - 20.0 - + 1.4 mV When setting 0xFFF Analog output impedance RO 3.10 3.80 4.50 kΩ D/A operation 2.0 - - MΩ When D/A stop Power supply current* IDDA AVCC 260 330 410 μA D/A 1unit operation AVCC=3.3 V 400 510 620 μA D/A 1unit operation AVCC=5.0 V IDSA - - 14 μA When D/A stop *: During no load

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12.7 Low-Voltage Detection Characteristics

12.7.1 Low-Voltage Detection Reset

Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL - 2.25 2.45 2.65 V When voltage drops Released voltage VDH - 2.30 2.50 2.70 V When voltage rises

12.7.2 Interrupt of Low-Voltage Detection

Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00111 2.58 2.8 3.02 V When voltage drops Released voltage VDH 2.67 2.9 3.13 V When voltage rises Detected voltage VDL SVHI = 00100 2.76 3.0 3.24 V When voltage drops Released voltage VDH 2.85 3.1 3.34 V When voltage rises Detected voltage VDL SVHI = 01100 2.94 3.2 3.45 V When voltage drops Released voltage VDH 3.04 3.3 3.56 V When voltage rises Detected voltage VDL SVHI = 01111 3.31 3.6 3.88 V When voltage drops Released voltage VDH 3.40 3.7 3.99 V When voltage rises Detected voltage VDL SVHI = 01110 3.40 3.7 3.99 V When voltage drops Released voltage VDH 3.50 3.8 4.10 V When voltage rises Detected voltage VDL SVHI = 01001 3.68 4.0 4.32 V When voltage drops Released voltage VDH 3.77 4.1 4.42 V When voltage rises Detected voltage VDL SVHI = 01000 3.77 4.1 4.42 V When voltage drops Released voltage VDH 3.86 4.2 4.53 V When voltage rises Detected voltage VDL SVHI = 11000 3.86 4.2 4.53 V When voltage drops Released voltage VDH 3.96 4.3 4.64 V When voltage rises LVD stabilization wait time tLVDW - - - 4480× tCYCP* μs *: tCYCP indicates the APB2 bus clock cycle time.

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12.8 MainFlash Memory Write/Erase Characteristics

(VCC = 2.7V to 5.5V) Parameter Value Unit Remarks Min Typ Max Sector erase time Large Sector - 0.7 3.7 s Includes write time prior to internal erase Small Sector 0.3 1.1 Half word (16-bit) write time Write cycles < 100 times - 12 100 μs Not including system-level overhead time Write cycles > 100 times 200 Chip erase time - 13.6 68 s Includes write time prior to internal erase Write cycles and data hold time Erase/Write cycles (cycle) Data hold time (year) 1,000 20 * 10,000 10 * 100,000 5 * *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C) .

12.9 WorkFlash Memory Write/Erase Characteristics

(VCC = 2.7V to 5.5V) Parameter Value Unit Remarks Min Typ Max Sector erase time - 0.3 1.5 s Includes write time prior to internal erase Half word (16-bit) write time - 20 200 μs Not including system-level overhead time Chip erase time - 1.2 6 s Includes write time prior to internal erase Write cycles and data hold time Erase/Write cycles (cycle) Data hold time (year) 1,000 20 * 10,000 10 * 100,000 5 * *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85°C) .

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12.10 Standby Recovery Time

12.10.1 Recovery Cause: Interrupt/WKUP

The time from recovery cause reception of the internal circuit to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tICNT HCLK×1 μs High-speed CR Timer mode Main Timer mode PLL Timer mode 40 80 μs Low-speed CR timer mode 450 900 μs Sub timer mode 896 1136 μs RTC mode stop mode (High-speed CR /Main/PLL run mode return) 316 581 μs RTC mode stop mode (Low-speed CR/sub run mode return) 270 540 Deep standby RTC mode with RAM retention Deep standby stop mode with RAM retention 365 667 μs without RAM retention 365 667 μs with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in External Interrupt Recovery*) Ext.INT tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

Document Number: 001-98941 Rev.*B Page 151 of 160 S6E2H4 Series Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*) Internal Resource INT tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main part(MN709-00001). − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main part(MN709-00001).

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12.10.2 Recovery Cause: Reset

The time from reset release to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tRCNT 155 266 μs High-speed CR timer mode Main timer mode PLL timer mode 155 266 μs Low-speed CR timer mode 315 567 μs Sub timer mode 315 567 μs RTC mode Stop mode 315 567 μs Deep standby RTC mode with RAM retention Deep standby stop mode with RAM retention 336 667 μs without RAM retention μs with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in INITX Recovery) INITX tRCNT Internal RST CPU Operation Start RST Active Release

Document Number: 001-98941 Rev.*B Page 153 of 160 S6E2H4 Series Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*) Internal Resource RST tRCNT Internal RST CPU Operation Start RST Active Release *: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main part(MN709-00001). − The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See (6) Power-on Reset Timing in 12.4 AC Characteristics in 12. Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 001-98941 Rev.*B Page 154 of 160 S6E2H4 Series 13. Ordering Information Part Number Package S6E2H46G0A GV20000 Plastic LQFP (0.5-mm pitch), 120 pin (LQM120) S6E2H44G0A GV20000 S6E2H46F0A GV20000 Plastic LQFP (0.5-mm pitch), 100 pin (LQI100) S6E2H44F0A GV20000 S6E2H46E0A GV20000 Plastic LQFP (0.5-mm pitch), 80 pin (LQH080) S6E2H44E0A GV20000 S6E2H46G0A GB30000 Plastic FBGA (0.5-mm pitch), 121 pin (FDI121) S6E2H44G0A GB30000

Document Number: 001-98941 Rev.*B Page 155 of 160 S6E2H4 Series 14. Package Dimensions Package Type Package Code LQFP 120 LQM120

Document Number: 001-98941 Rev.*B Page 156 of 160 S6E2H4 Series Package Type Package Code LQFP 100 LQI100

Document Number: 001-98941 Rev.*B Page 157 of 160 S6E2H4 Series Package Type Package Code LQFP 80 LQH080

Document Number: 001-98941 Rev.*B Page 158 of 160 S6E2H4 Series Package Type Package Code FBGA 121 FDI121

Document Number: 001-98941 Rev.*B Page 159 of 160 S6E2H4 Series Document History Document Title: S6E2H4 Series 32-bit ARM® Cortex®-M4F, FM4 Microcontroller Document Number: 001-98941 Revision ECN Orig. of Change Submission Date Description of Change ** 4869576 YUIA 08/18/2015 New Spec. *A 4932844 YUIA 10/02/2015 Changed status from Preliminary to Final. Updated 12.2 Recommended Operating Conditions: Added the "Smoothing capacitor (CS)”. Added the “Current Value” in “Maximum leak current at operating”. Updated 12.3.1 Current Rating: Updated Table 12-1 ~ 12-9: Added the “MAX” value. Updated Table 12-11: Added voltage and temperature information. Updated 12.10.1 Recovery Cause: Interrupt/WKUP: Updated Recovery Count Time. Updated 12.10.2 Recovery Cause: Reset: Updated Recovery Count Time. *B YUIA 11/26/2015 Updated 2 Packages: Changed FBGA to“Supported” from “Under development”. Updated 4 Pin Description: Added “Note” about TAP pins. Updated 12.5 12-bit A/D Converter: Updated “Zero transition” and “Full-scale transition” value. Added “Total error”. 5027946

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