WLSIP-WL3D AMKOR | Alldatasheet
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Technical content
Embedded Wafer Level System Integration Amkor Technology was among the first in the world to offer Wafer Level Fan- Out (WLFO) packaging, enabling a wide range of embedded heterogeneous system integration package solutions. These include: Wafer Level System-in- Package (WLSiP) a single or multiple die, with or without passives or sensors integration and 3D package stacking solutions (WL3D), including wafer level Package-on-Package (PoP) and face-to-face package assembly. Tailoring the best solutions requires a deep understanding of customer needs. Amkor’s package solutions are collaboratively developed, which often involves cooperation from the earliest stage of the chip-package-board co- design. Amkor is recognized for its proficiency in advanced packaging, and is known for a portfolio of innovative solutions manufactured in volume. These include the largest reliable WLCSP to date. By relying on an experienced in-house R&D team to design and develop innovative package and system solutions for a wide range of applications, we enable products from concept to market. As a leader in wafer-level packaging, Amkor offers world-class, turnkey solutions on state-of-the-art 300 mm wafer-processing equipment. In addition, we consistently deliver the best results in key metrics such as time to market, cost efficiency and yield. Reliability: Board Level Tests With a wide range of different WLSiP and WL3D package constructions and configurations possible, customer requirements are implemented in each product developed and reliability results are realized based on technical capabilities. WLSiP & WL3D DATA SHEET | WAFER LEVEL PRODUCTS Test Specification Criteria Lower Complexity WLSiP Temperature Cycling on Board (TCoB) IPC-9701 Condition TC3 -40°C/+125°C, 1 Cy/Hr 1000x Drop Test (DT) JEDEC JESD-22-B111 100 Drops Higher Complexity WL3D Temperature Cycling on Board (TCoB) IPC-9701 Condition TC3 -40°C/+125°C, 1 Cy/Hr 1000x Drop Test (DT) JEDEC JESD-22-B111 30 Drops Temperature Humidity Bias (THB) JEDEC JESD-22-A101 85°C/85% RH/Vcc, 1000 Hours ADVANCED PACKAGING SOLUTIONS f WLSiP side-by-side multi-chip modules f WLSiP with passives and leadless package integration f Portfolio of WLSiP configurations range from 2 x 3 mm2 (2 components) to 33 x 28 mm2 (10 components) f WL3D Package-on-Package (PoP) achieved by stacking WLSiP and other package types using Through Package Vias (TPV) f 3D integration realized by F2F assembly of flip chip to WLFO package
APPLICATIONS
f Mobile and consumer products, baseband, RF/wireless, analog, power management f ASIC, MEMS, sensors, system solutions for medical, security, encryption, DC/DC converter, radar and automotive f Electro-optical WLSiP, solutions for M2M communication and Internet of Things (IoT) f Extension of the technology platform to a wider field of application areas is ongoing
With respect to the information in this document, Amkor makes no guarantee or warranty of its accuracy or that the use of such information will not infringe upon the intellectual rights of third parties. Amkor shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it and no patent or other license is implied hereby. This document does not in any way extend or modify Amkor’s warranty on any product beyond that set forth in its standard terms and conditions of sale. Amkor reserves the right to make changes in its product and specifications at any time and without notice. The Amkor name and logo are registered trademarks of Amkor Technology, Inc. All other trademarks mentioned are property of their respective companies. © 2019 Amkor Technology, Incorporated. All Rights Reserved. DS703B-EN Rev Date: 08/19 Visit amkor.com or email sales@amkor.com for more information. Design Features f Package size: 2 x 3 mm2 - 33 x 28 mm2 f Package thickness: 0.275 mm (WLSiP – Multi-chip module) to 1.900 mm (WL3D) f WLSiP with up to 10 active dies and 50 passives qualified f Minimum through package via pitch: 0.350 mm f BGA pitch: down to 0.350 µm f Minimum die-to-die distance: 0.100 mm f Minimum passive-to-die and passive-to-passive distance: 0.150 mm f Minimum die TPV pad pitch: 0.050 mm and opening 0.045 mm f Bottom side Cu-RDL minimum line/space: 0.010 mm/0.010 mm, multi-layer RDL f Top side Cu-RDL minimum line/space: 0.020 mm/0.020 mm, single-layer RDL WLSiP & WL3D Differentiation f High integration density through small die-to-die distance f Multi-layer RDL and double-sided RDL (WLFO bottom and top side) f 3D stacking enabled by TPV concept f Small form factor (optimization based on customer needs in footprint or z-height) f BGA ball attach and flip chip with underfill assembly on same WLFO bottom side f Heterogeneous integration of multiple different active dies (Si, GaAs, SiGe), already packaged dies, passives, optical elements, sensors and MEMS Cross Sections WLFO-Based Embedded Wafer Level System Integration Portfolio WLSiP passives integration WLSiP multi-chip module WL3D face-to-face WL3D RDL on both sides through package vias WLSiP multi-chip module WL3D Package-on-Package, face-to-face, through package vias Dual die package pick & place WLSiP before molding WLSiP after molding Cross section through package vias