W40S01-04 CYPRESS | Alldatasheet
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Technical content
Features
- Eighteen skew controlled CMOS outputs (SDRAM0:17) Supports four SDRAM DIMMs Ideal for high-performance systems designed around Intel®’s 440BX chip set 2C serial configuration interface Output skew between any two outputs is less than 250 ps 1 to 5 ns propagation delay DC to 133-MHz operation Single 3.3V supply voltage Low power CMOS design packaged in a 48-pin SSOP (Small Shrink Outline Package) Overview The Cypress W40S01-04 is a low-voltage, eighteen-output signal buffer. Output buffer impedance is approximately 15Ω which is ideal for driving SDRAM DIMMs. Key Specifications DDQ3 + 0.5V
1.5 V/ns
Intel is a registered trademark of Intel Corporation. Pin Configuration SSOP Block Diagram SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM16 SDRAM17 SDRAM13 SDRAM14 SDRAM15 SDRAM0 Serial PortSCLOCK SDA T A Device Control BUF_IN OE NC NC VDDQ3 SDRAM0 SDRAM1 GND VDDQ3 SDRAM2 SDRAM3 GND BUF_IN VDDQ3 SDRAM4 SDRAM5 GND VDDQ3 SDRAM6 SDRAM7 GND VDDQ3 SDRAM16 GND VDDQ3 SDA TA NC NC VDDQ3 SDRAM15 SDRAM14 GND VDDQ3 SDRAM13 SDRAM12 GND OE VDDQ3 SDRAM11 SDRAM10 GND VDDQ3 SDRAM9 SDRAM8 GND VDDQ3 SDRAM17 GND GND SCLOCK [1] Note: 1. Internal pull-up resistor of 250K on SDA TA, SCLOCK, and OE inputs (not CMOS level). [1][1]
No. Pin Type Pin Description SDRAM0:17 4, 5, 8, 9, 13, 14, 17, 18, 21, 28, 31, 32, 35, 36, 40, 41, 44, 45 O SDRAM Outputs: Provides buffered copy of BUF_IN. The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns. All outputs are skew controlled to within ± 250 ps of each other. BUF_IN 11 I Clock Input: This clock input has an input threshold voltage of 1.5V (typ). SDA T A 24 I/O I 2C Data Input: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-kΩ pull-up resistor. SCLOCK 25 I I2C clock Input: The I2C data clock should be presented to this input as described in the I2C section of this data sheet. Internal 250-kΩ pull-up resistor. VDDQ3 3, 7, 12, 16, 20, 23, 29, 33, 37, 42, P Power Connection: Power supply for core logic and output buffers. Connected to 3.3V supply. GND 6, 10, 15, 19, 22, 26, 27, 30, 34, 39, 43 G Ground Connection: Connect all ground pins to the common system ground plane. OE 38 I Output Enable: Internal 250-kΩ pull-up resistor. Three-states outputs when LOW. NC 1, 2, 47, 48 - No Connect: Do not connect.
Outputs three-stated when OE = 0, and toggle when OE = 1. to 5 ns. Outputs can also be controlled via the I2C interface. level compatible. Nominal output buffer impedance is 15 ohms. each. Bytes are written in the order shown in Ta b l e 1. Table 1. Byte Writing Sequence
1 Slave Address 11010010 Commands the W40S01-04 to accept the bits in Data Bytes 0-6 for inter-
Address is not correct (or is for an alternate slave receiver).
2 Command
Don ’t Care Unused by the W40S01-04, therefore bit values are ignored (don’t care). dressed slave receiver on the serial data bus. 3 Byte Count Don ’t Care Unused by the W40S01-04, therefore bit values are ignored (don’t care). slave receiver on the serial data bus. functions, refer to Ta ble 2, Data Byte Serial Configuration Map.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3 Don ’t Care Refer to Cypress clock drivers.
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
Each bit in the data bytes control a particular device function. Bits are written MSB (most significant bit) first, which is bit 7.
- At power-up all SDRAM outputs are enabled and active. Program Reserved bits to 0.
Table 2. Data Bytes 0–2 Serial Configuration Map[2]
5 N/A Reserved (Reserved) -- --
4 N/A Reserved (Reserved) -- --
3 N/A Reserved (Reserved) -- --
2 N/A Reserved (Reserved) -- --
1 N/A Reserved (Reserved) -- --
0 N/A Reserved (Reserved) -- --
Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only . Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability Parameter Description Rating Unit V DD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TA Operating T emperature 0 to +70 °C TB Ambient T emperature under Bias –55 to +125 °C Parameter Description Test Condition/ Comments Min Typ Max Unit IDD 3.3V Supply Current BUF_IN = 100 MHz 320 mA IDD T ristate 3.3V Supply Current in Three-state BUF_IN = 100 MHz 5 mA Logic Inputs (BUF_IN, OE, SCLOCK, SDATA) VIL Input Low Voltage GND –0.3 0.8 V VIH Input High Voltage 2.0 V DDQ3 +0.5 V IILEAK Input Leakage Current, BUF_IN –5+ 5 µ A IILEAK Input Leakage Current[3] –20 +5 µA Logic Outputs (SDRAM0:17)[4] VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 70 110 185 mA IOH Output High Current V OH = 1.5V 65 100 160 mA Pin Capacitance/Inductance C IN Input Pin Capacitance (Except BUF_IN) 5p F C OUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7n H Notes: 3. OE, SCLOCK, and SDA TA logic pins have a 250-kΩ internal pull-up resistor (not CMOS level). 4. Outputs loaded by 6" 60Ω transmission lines with 20-pF capacitors.
Document #: 38-00811 Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency 0 133 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.5 4.0 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.5 4.0 V/ns tSR Output Skew, Rising Edges 250 ps tSF Output Skew, Falling Edges 250 ps tEN Output Enable Time 1.0 8.0 ns tDIS Output Disable Time 1.0 8.0 ns tPR Rising Edge Propagation Delay 1.0 5.0 ns tPF Falling Edge Propagation Delay 1.0 5.0 ns tD Duty Cycle Measured at 1.5V 45 55 % Zo AC Output Impedance 15 Ω TSPP Part to Part Skew 700 ps
Ordering Information
Freq. Mask Code Package Name Package Type W40S01 04 H 48-pin SSOP (300 mils)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 48-Pin Shrink Small Outline Package (SSOP, 0.300 inch)