W311

W311 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

• Maximized EMI Suppression using Cypress’s Spread Spectrum Technology  System frequency synthesizer for VIA Pro-2000  Programmable clock output frequency with less than

1 MHz increment

 Integrated fail-safe Watchdog Timer for system recovery  Automatically switch to HW selected or SW programmed clock frequency when Watchdog Timer time-out  Capable of generate system RESET after a Watchdog Timer time-out occurs or a change in output frequency via SMBus interface  Support SMBus byte read/write and block read/ write operations to simplify system BIOS development  Vendor ID and Revision ID support  Programmable drive strength for CPU and PCI output clocks  Programmable output skew between CPU, AGP and PCI  Supports Intel® Celeron® and Pentium® III class pro- cessor  Three copies of CPU output  Nine copies of PCI output  One 48-MHz output for USB  One 24-MHz or 48-MHz output for SIO  Two buffered reference outputs  Three copies of APIC output  Supports frequencies up to 200 MHz  SMBus interface for programming  Power management control inputs  Available in 48-pin SSOP Key Specifications Intel, Pentium, and Celeron are registered trademarks of Intel Corporation. Block Diagram Pin Configuration Note: 1. Signals marked with ‘*’ have internal pull-up resistors. [1] VDD_REF REF0 XTAL PLL Ref Freq PLL 1 X1 REF1/FS4 VDD_PCI Stop ClockControl PCI1:8 48MHz/FS3 24_48MHz/FS2 PLL2 ÷6, ÷8, OSC PWR_DWN# VDD_48 MHz SMBusSDATA LogicSCLK CPU1:3 RST# VDD_REF GND_REF VDD_48 MHz FS3*/48 MHz FS2*/24_48 MHz GND_48 MHz PCI_F PCI1 PCI2 GND_PCI PCI3 PCI4 VDD_PCI PCI5 PCI6 PCI7 GND_PCI PCI8 *FS1 *FS0 AGP0 VDD_AGP W311 REF0 REF1/FS4* VDD_APIC APIC0 APIC1 GND_APIC APIC2 VDD_CPU GND_CPU CPU1 CPU2 VDD_CPU GND_CPU CPU3 CPU_STOP#* PCI_STOP#* RST# VDD_CORE GND_CORE SDATA SCLK AGP2 AGP1 GND_AGP Stop ClockControl PCI_STOP# PCI_F DIV APIC0:1 AGP0:2DIV FS0:1 CPU_STOP# VDD_CPU VDD_AGP VDD_APIC ÷10, ÷12

Pin Name Pin No. Pin Type Pin Description RST# 32 O (open- drain) System Reset Output: Open-drain system reset output. CPU1:3 39, 38, 35 O CPU Clock Output: Frequency is set by the FS0:4 input or through serial input interface. The CPU1:3 outputs are gated by the CLK_STOP# input. CPU_STOP# 34 I CPU Output Control: 3.3V LVTTL-compatible input that stop CPU1:3. PCI1:8 10, 11, 13, 14, 16, 17, 18, 20 O PCI Clock Outputs 1 through 8: Frequency is set by FS0:4 inputs or through serial input interface; see Ta bl e 5 for details. PCI1:8 outputs are gated by the PCI_STOP# input. PCI_STOP# 33 O PCI_STOP# Input: 3.3V LVTTL-compatible input that stops PCI1:8. PCI_F 9 O Free-Running PCI Clock Output: Frequency is set by FS0:4 inputs or through serial input interface; see Ta bl e 5 for details. APIC0:2 45, 44, 42 O APIC Clock Output: APIC clock outputs. 48MHz/FS3 6 I/O 48-MHz Output/Frequency Select 3: 48 MHz is provided in normal operation. In stan- dard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power-on strap option to determine device operating frequency as described in Ta bl e 5. 24_48MHz/ FS2

7 I/O 24_48-MHz Output/Frequency Select 2: In standard PC systems, this output can be

used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz. This pin also serves as a power-on strap option to determine device operating frequency as described in Ta bl e 5. REF1/FS4 47 I/O Reference Clock Output 1/Frequency Select 4: 3.3V 14.318-MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Ta bl e 5. REF0 48 O Reference Clock Output 0: 3.3V 14.318-MHz output clock. SCLK 28 I Clock pin for SMBus circuitry. SDA T A 29 I/O Data pin for SMBus circuitry. X1 3 I Crystal Connection or External Reference Frequency Input: This pin has dual func- tions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 4 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDD_REF , VDD_48MHz, VDD_PCI, VDD_AGP , VDD_CORE 1, 5,15, 24, P Power Connection: Power supply for core logic, PLL circuitry, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output, connect to 3.3V supply. VDD_CPU, VDD_APIC 41, 46, 37 P Power Connection: Power supply for APIC and CPU output buffers, connect to 2.5V . GND_REF , GND_48MHz, GND_PCI, GND_AGP , GND_CORE, GND_CPU, GND_APIC 2, 8, 12, 19, 25, 30, 36, 40, 43 G Ground Connections: Connect all ground pins to the common system ground plane.

the ability to stop after any complete byte has been transferred. dexed byte is encoded in the command code. Table 1. Command Code Definition need to be set at ‘0000000’. Table 2. Block Read and Block Write Protocol

1 Start 1 Start

9 Write 9 Write

10 Acknowledge from slave 10 Acknowledge from slave

19 Acknowledge from slave 19 Acknowledge from slave

28 Acknowledge from slave 21:27 Slave address - 7 bits

37 Acknowledge from slave 29 Acknowledge from slave

46 Acknowledge from slave 38 Acknowledge

Table 3. Word Read and Word Write Protocol

38 Stop 30:37 Data byte low from slave - 8 bits

38 Acknowledge

47 NOT acknowledge

48 Stop

Table 4. Byte Read and Byte Write Protocol

29 Stop 28 Read

29 Acknowledge from slave

38 Not Acknowledge

39 Stop

W311 Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 2. All unused register bits (reserved and N/A) should be writ- ten to a “0” level. 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Byte 0: Control Register 0 Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - SEL2 0 See Ta bl e 5 Bit 5 - SEL1 0 See Ta bl e 5 Bit 4 - SEL0 0 See Ta bl e 5 Bit 3 - FS_Override 0 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings Bit 2 - SEL4 1 See Ta bl e 5 Bit 1 - SEL3 0 See Ta bl e 5 Bit 0 - Reserved 0 Reserved Byte 1: Control Register 1 Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Spread Select2 0 ‘000’ = Normal (spread off) ‘001’ = T est Mode ‘010’ = Reserved ‘011’ = Three-Stated ‘100’ = –0.5% ‘101’ = ± 0.5% ‘110’ = ± 0.25% ‘111’ = ± 0.38% Bit 5 - Spread Select1 0 Bit 4 - Spread Select0 0 Bit 3 35 CPU3 1 (Active/Inactive) Bit 2 38 CPU2 1 (Active/Inactive) Bit 1 39 CPU1 1 (Active/Inactive) Bit 0 42 APIC2 1 (Active/Inactive) Byte 2: Control Register 2 Bit Pin# Name Default Description Bit 7 20 PCI8 1 (Active/Inactive) Bit 6 18 PCI7 1 (Active/Inactive) Bit 5 17 PCI6 1 (Active/Inactive) Bit 4 16 PCI5 1 (Active/Inactive) Bit 3 14 PCI4 1 (Active/Inactive) Bit 2 13 PCI3 1 (Active/Inactive) Bit 1 11 PCI2 1 (Active/Inactive)

Bit 0 10 PCI1 1 (Active/Inactive) Byte 2: Control Register 2 Bit Pin# Name Default Description Byte 3: Control Register 3 Bit Pin# Name Default Description Bit 7 -- Reserved 0 Reserved Bit 6 7 SEL_48MHz 0 0 = Select 24 MHz as output 1 = Select 48 MHz as output (default). Bit 5 6 48MHz 1 (Active/Inactive) Bit 4 7 24_48MHz 1 (Active/Inactive) Bit 3 9 PCI_F 1 (Active/Inactive) Bit 2 27 AGP2 1 (Active/Inactive) Bit 1 26 AGP1 1 (Active/Inactive) Bit 0 23 AGP0 1 (Active/Inactive) Byte 4: Control Register 4 Bit Pin# Name Default Description Bit 7 - PCI_Skew1 0 PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps Bit 6 - PCI_Skew0 0 Bit 5 - WD_TIMER4 1 These bits store the time-out value of the Watchdog Timer. The scale of the timer is determine by the pre- scaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scalar is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0,” it will set the WD_TO_ST A TUS bit and generate Reset if RST_EN_WD is enabled. Bit 4 - WD_TIMER3 1 Bit 3 - WD_TIMER2 1 Bit 2 - WD_TIMER1 1 Bit 1 - WD_TIMER0 1 Bit 0 - WD_PRE_SCAL ER 0 0 = 150 ms 1 = 2.5 sec Byte 5: Control Register 5 Bit Pin# Name Default Description Bit 7 6 48Mhz_DRV 1 0 = Norm, 1 = High Drive Bit 6 7 24_48MHz_DRV 1 0 = Norm, 1 = High Drive Bit 5 44 APIC1 1 (Active/Inactive) Bit 4 45 APIC0 1 (Active/Inactive) Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 47 REF1 1 (Active/Inactive) Bit 0 48 REF0 1 (Active/Inactive)

Byte 6: Reserved Register Bit Pin# Name Default Pin Description Bit 7 - Reserved 1 Reserved Bit 6 - Reserved 1 Reserved Bit 5 - Reserved 1 Reserved Bit 4 - Reserved 1 Reserved Bit 3 - Reserved 1 Reserved Bit 2 - Reserved 1 Reserved Bit 1 - Reserved 1 Reserved Bit 0 - Reserved 1 Reserved Byte 7: Reserved Register Bit Pin# Name Default Pin Description Bit 7 - Reserved 1 Reserved Bit 6 - Reserved 1 Reserved Bit 5 - Reserved 1 Reserved Bit 4 - Reserved 1 Reserved Bit 3 - Reserved 1 Reserved Bit 2 - Reserved 1 Reserved Bit 1 - Reserved 1 Reserved Bit 0 - Reserved 1 Reserved Byte 8: Vendor & Revision ID Register (Read Only) Bit Name Default Pin Description Bit 7 Revision_ID3 0 Revision ID bit[3] Bit 6 Revision_ID2 0 Revision ID bit[2] Bit 5 Revision_ID1 0 Revision ID bit[1] Bit 4 Revision_ID0 0 Revision ID bit[0] Bit 3 Vendor_ID3 1 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 2 Vendor_ID2 0 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 1 Vendor _ID1 0 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 0 Vendor _ID0 0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.

Byte 9: System RESET and Watchdog Timer Register Bit Name Default Pin Description Bit 7 Reserved 0 Reserved Bit 6 PCI_DRV 0 PCI clock output drive strength 0 = Normal 1 = High Drive Bit 5 Reserved 0 Reserved Bit 4 RST_EN_WD 0 This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled Bit 3 RST_EN_FC 0 This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Bit 2 WD_TO_ST A TUS 0 Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_ST A TUS (WRITE) Bit 1 WD_EN 0 0 = Stop and re-load Watchdog Timer 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs. Note: W311 will generate system reset, reload a recovery frequency, and lock itself into a recovery frequency mode after a watchdog timer time-out occurs. Under recovery frequency mode, W311 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock W311 from its recovery frequency mode by clearing the WD_EN bit. Bit 0 Reserved 0 Reserved Byte 10: Skew Control Register Bit Name Default Description Bit 7 CPU_Skew2 0 CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Bit 6 CPU_Skew1 0 Bit 5 CPU_Skew0 0 Bit 4 Reserved 0 Reserved Bit 3 Reserved 0 Reserved Bit 2 Reserved 0 Reserved Bit 1 AGP_Skew1 0 AGP skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps Bit 0 AGP_Skew0 0

Byte 11: Recovery Frequency N-Value Register Bit Name Default Pin Description Bit 7 ROCV_FREQ_N7 0 If ROCV_FREQ_SEL is set, W311 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog Timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same fre- quency ratio stated in the Latched FS[4:0] register. When it is set, W311will use the frequency ratio stated in the SEL[4:0] register. W312 supports programmable CPU frequency ranging from 50MHz to 248MHz. W311 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommend- ed to use Word or Block write to update both registers within the same SMBus bus operation. Bit 6 ROCV_FREQ_N6 0 Bit 5 ROCV_FREQ_N5 0 Bit 4 ROCV_FREQ_N4 0 Bit 3 ROCV_FREQ_N3 0 Bit 2 ROCV_FREQ_N2 0 Bit 1 ROCV_FREQ_N1 0 Bit 0 ROCV_FREQ_N0 0 Byte 12: Recovery Frequency M-Value Register Bit Name Default Pin Description Bit 7 ROCV_FREQ_SEL 0 ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] Bit 6 ROCV_FREQ_M6 0 If ROCV_FREQ_SEL is set, W311 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog Timer time-out occurs.The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio stated in the SEL[4:0] register. W311 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W311 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommend- ed to use Word or Block write to update both registers within the same SMBus bus operation. Bit 5 ROCV_FREQ_M5 0 Bit 4 ROCV_FREQ_M4 0 Bit 3 ROCV_FREQ_M3 0 Bit 2 ROCV_FREQ_M2 0 Bit 1 ROCV_FREQ_M1 0 Bit 0 ROCV_FREQ_M0 0 Byte 13: Programmable Frequency Select N-Value Register Bit Name Default Pin Description Bit 7 CPU_FSEL_N7 0 If Prog_Freq_EN is set, W311 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output fre- quency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio stated in the SEL[4:0] register. W311 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 6 CPU_FSEL_N6 0 Bit 5 CPU_FSEL_N5 0 Bit 4 CPU_FSEL_N4 0 Bit 3 CPU_FSEL_N3 0 Bit 2 CPU_FSEL_N2 0 Bit 1 CPU_FSEL_N1 0 Bit 0 CPU_FSEL_N0 0

Byte 14: Programmable Frequency Select M-Value Register Bit Name Default Description Bit 7 Pro_Freq_EN 0 Programmable output frequencies enabled 0 = disabled 1 = enabled Bit 6 CPU_FSEL_M6 0 If Prog_Freq_EN is set, W311 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output fre- quency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W311 will use the same fre- quency ratio stated in the Latched FS[4:0] register. When it is set, W311 will use the frequency ratio stated in the SEL[4:0] register. W311 supports programmable CPU frequency ranging from 50MHz to 248MHz. Bit 5 CPU_FSEL_M5 0 Bit 4 CPU_FSEL_M4 0 Bit 3 CPU_FSEL_M3 0 Bit 2 CPU_FSEL_M2 0 Bit 1 CPU_FSEL_M1 0 Bit 0 CPU_FSEL_M0 0 Byte 15: Reserved Register Bit Pin# Name Default Description Bit 7 47 Latched FS4 input X Latched FS[4:0] inputs. These bits are read only. Bit 6 6 Latched FS3 input X Bit 5 7 Latched FS2 input X Bit 4 21 Latched FS1 input X Bit 3 22 Latched FS0 input X Bit 2 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 1 - Vendor test mode 1 Reserved. Write with ‘1’ Bit 0 - Vendor test mode 1 Reserved. Write with ‘1’ Byte 16: Reserved Register Bit Pin# Name Default Description Bit 7 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 6 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 5 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 4 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 3 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 2 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 1 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 0 - Vendor test mode 0 Reserved. Write with ‘0’. Byte 17: Reserved Register Bit Pin# Name Default Description Bit 7 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 6 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 5 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 4 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 3 - Vendor test mode 0 Reserved. Write with ‘0’.

Bit 2 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 1 - Vendor test mode 0 Reserved. Write with ‘0’. Bit 0 - Vendor test mode 0 Reserved. Write with ‘0’. Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

erated and a recovery frequency will be activated. All the related registers are summarized Tabl e 6. Table 6. Register Summary will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. CPU and other frequency outputs. mended to use Word or Block write to update both registers within the same SMBus bus operation. FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. within the same SMBus bus operation. 1 = Enable Watchdog Timer. It will start counting down after a frequency change occurs.

changing the value of the N-Value Register. Table 7. Examples of N and M Value for Different CPU Frequent Range is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog Timer reaches “0.” it will set the WD_TO_ST A TUS bit. RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog Timer time-out occurs. RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs.

Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit V DD , VIN Voltage on Any Pin with Respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TB Ambient T emperature under Bias –55 to +125 °C TA Operating T emperature 0 to +70 °C ESD PROT Input ESD Protection 2 (min.) kV Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Cu rrent CPU1:3 = 133 MHz [2] 150 mA IDD 2.5V Supply Cu rrent 50 mA Logic Inputs V IL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[3] –25 µA IIH Input High Current[3] 10 µA Clock Outputs V OL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V VOH Output High Voltage CPU1:3, APIC0:2 IOH = –1 mA 2.2 V IOL Output Low Current CPU1:3 V OL = 1.25V 27 57 97 mA PCI_F , PCI1:8 VOL = 1.5V 20.5 53 139 mA AGP0:2 V OL = 1.25V 40 85 140 mA APIC0:2 V OL = 1.25V 40 85 140 mA REF0:1 V OL = 1.5V 25 37 76 mA 48-MHz V OL = 1.5V 25 37 76 mA 24-MHz V OL = 1.5V 25 37 76 mA IOH Output High Current CPU1:3 V OH = 1.25V 25 55 97 mA PCI_F , PCI1:8 VOH = 1.5V 31 55 139 mA AGP0:2 V OL = 1.25V 40 85 140 mA APIC0:1 V OH = 1.5V 27 44 94 mA 48-MHz V OH = 1.5V 27 44 94 mA 24-MHz V OH = 1.5V 25 37 76 mA Notes: 2. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors. 3. Inputs have internal pull-up resistors.

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. Notes: 4. X1 input threshold voltage (typical) is 3.3V/2. 5. The W311 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. T otal load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Crystal Oscillator VTH X1 Input Threshold Voltage[4] VDDQ3 = 3.3V 1.65 V C LOAD Load Capacitance, Imposed on External Crystal[5] 18 pF C IN,X1 X1 Input Capacitance[6] Pin X2 unconnected 28 pF Pin Capacitance/Inductance C IN Input Pin Capacitance Except X1 and X2 5 pF C OUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7n H CPU Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/ Comments CPU = 66.6 MHz CPU = 100 MHz CPU = 133 MHz tP Period Measured on rising edge at 1.25 15 15.5 10 10.5 7.5 8.0 ns tH High Time Duration of clock cycle above 2.0V 5.2 3.0 1.87 ns tL Low Time Duration of clock cycle be- low 0.4V 5.0 2.8 1.67 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 14 14 14 V / n s t F Output Fall Edge Rate Measured from 2.0V to 0.4V 14 14 14 V / n s t D Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V . Maximum differ- ence of cycle time be- tween two adjacent cycles. 250 250 250 ps t SK Output Skew Measured on rising edge at 1.25V 175 175 175 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply volt- age reached within 1 ms from power-up. Short cy- cles exist prior to frequen- cy stabilization. 333 m s Z o AC Output Impedance Average value during switching transition. Used for determining series ter- mination value. 20 20 20 Ω Parameter Description Test Condition Min. Typ. Max. Unit

APIC Clock Output (Lump Capacitance Test Load = 20 pF) PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V . Maximum difference of cycle time between two adjacent cycles. 500 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V . CPU leads PCI output. 1.5 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 30 Ω AGP Clock Outputs, (Lump Capacitance test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 15 ns tH High Time Duration of clock cycle above 2.4V 5.25 ns tL Low Time Duration of clock cycle below 0.4V 5.05 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V . Maximum difference of cycle time between two adjacent cycles. 500 ps tSK Output Skew Measured on rising edge at 1.5V 250 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 30 Ω Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Frequency generated from PCI divided by 2 PCI/2 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 Ω

Document Control# 38-01095-** REF Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Ω 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Ω 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 24.004 MHz fD Deviation from 24 MHz (24.004 – 24)/24 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/34 = 24.004 MHz) 57/34 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Ω

Ordering Information

Ordering Code Package Name Package Type W311 H 48-pin SSOP (300 mils)

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 48-Pin Small Shrink Outline Package (SSOP , 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102