W305B

W305B CYPRESS | Alldatasheet

Document overview

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• PDF pages: 21

Technical content

Features

• Single chip FTG solution for Intel Solano/810E/810
• Programmable clock output frequency with less than

1 MHz increment

• Integrated fail-safe Watchdog timer for system recovery
• Automatically switch to HW selected or SW programmed clock frequency when Watchdog timer time-out
• Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SMBus interface
• Support SMBus byte read/write and block read/write operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for SDRAM and PCI output clocks
• Programmable output skew between CPU, AGP, PCI and SDRAM
• Maximized EMI suppression using Cypress’s Spread Spectrum Technology
• Low jitter and tightly controlled clock skew
• Two copies of CPU clock
• Thirteen copies of SDRAM clock
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Three copies of 66-MHz outputs
• Three copies of 48-MHz outputs
• One copy of double strength 14.31818-MHz reference clock
• One RESET output for system recovery
• SMBus interface for turning off unused clocks Key Specifications APIC, 48-MHz, 3V66, PCI Outputs 1. Internal 100K pull-up and 100K pull-down resistors present on i nputs marked with * and ^ respectively. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH or LOW. Block Diagram Pin Configuration[1] VDDQ3 VDDQ2 PCI1/FS1 XTAL PLL REF FREQ PLL 1 X1 REF2X/FS3 PCI3:7 48MHz/FS4 24_48MHz/SEL24_48MHz# PLL2 OSC VDDQ3 SMBusSDATA LogicSCLK 3V66_0:2 CPU0:1 APIC Divider, Delay, and Phase Control Logic VDDQ3 SDRAM0:12 RST# PCI0/FS0 PCI2/FS2 (FS0:4) 48MHz GND VDDQ3 REF2X/FS3^ VDDQ3 3V66_0 3V66_1 3V66_2 GND PCI0/FS0^ PCI1/FS1^ PCI2/FS2^ GND PCI3 PCI4 VDDQ3 PCI5 PCI6 PCI7 GND 48MHz 48MHz/FS4^ 24_48MHz/SEL24_48MHz#* W305B VDDQ2 APIC GND VDDQ2 CPU0 CPU1 GND SDRAM0 SDRAM1 SDRAM2 VDDQ3 GND SDRAM3 SDRAM4 SDRAM5 SDRAM6 VDDQ3 GND SDRAM7 SDRAM8 SDRAM9 SDRAM10 VDDQ3 GND VDDQ3 SDATA GND VDDQ3 SDRAM11 SDRAM12 RST# SCLK

Document #: 38-07262 Rev. *B Page 2 of 21 Pin Definitions Pin Name Pin No. Pin Type Pin Description REF2X/FS3 3 I/O Reference Clock with 2x Drive/Frequency Select 3. 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determines device operating frequency as described in Table 5. X1 4 I Crystal Input. This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 O Crystal Output. An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI0/FS0 11 I/O PCI Clock 0/Frequency Selection 0. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. PCI1/FS1 12 I/O PCI Clock 1/Frequency Selection 1. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. PCI2/FS2 13 I/O PCI Clock 2/Frequency Selection 2. 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 5. PCI3:7 15, 16, 18, 19, 20 O PCI Clock 3 through 7. 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individ- ually turned off via SMBus interface. 3V66_0:2 7, 8, 9 O 66-MHz Clock Output. 3.3V output clocks. The operating frequency is controlled by FS0:4 (see Table 5). 48MHz 22 O 48MHz. 3.3V 48-MHz non-spread spectrum output. 48MHz/FS4 23 I/O 48-MHz Output/Frequency Selection 4. 3.3V 48-MHz non-spread spectrum output. This pin also serves as the select strap to determine device operating frequency as described in Table 5. 24_48MHz/SEL24 _48MHz# 24 I/O 24- or 48-MHz Output/Select 24 or 48MHz. 3.3V 24 or 48-MHz non-spread spectrum output. This pin also serves as the select strap to determine the output frequency for 24_48MHz output. RST# 30 O (open-d rain) Reset#. Open-drain RESET# output. CPU0:1 52, 51 O CPU Clock Outputs. Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:4. Voltage swing is set by VDDQ2. SDRAM0:12, 49, 48, 47, 44, 43, 42, 41, 38, 37, 36, 35, 32, 31 O SDRAM Clock Outputs. 3.3V outputs for SDRAM and chipset. The operating frequency is controlled by FS0:4 (see Table 5). APIC 55 O Synchronous APIC Clock Outputs. Clock outputs running synchronous with the PCI clock outputs. Voltage swing set by VDDQ2. SDATA 26 I/O Data pin for SMBus circuitry. SCLK 29 I Clock pin for SMBus circuitry. VDDQ3 2, 6, 17, 25, 28, 34, 40, 46 P 3.3V Power Connection. Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. VDDQ2 53, 56 P 2.5V Power Connection. Power supply for APIC and CPU output buffers. Connect to 2.5V. GND 1, 10, 14, 21, 27, 33, 39, 45, 50, 54 G Ground Connections. Connect all ground pins to the common system ground plane.

particular device functions. indexed byte is encoded in the command code. The definition for the command code is given in Table 1. Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM) Table 1. Command Code Definition need to be set at ‘0000000’. Table 2. Block Read and Block Write Protocol

10 Acknowledge from slave 10 Acknowledge from slave

19 Acknowledge from slave 19 Acknowledge from slave

28 Acknowledge from slave 21:27 Slave address – 7 bits

37 Acknowledge from slave 29 Acknowledge from slave

46 Acknowledge from slave 38 Acknowledge

Table 2. Block Read and Block Write Protocol (continued)

1 Start 1 Start

38 Stop 30:37 Data byte low from slave – 8 bits

38 Acknowledge

47 NOT acknowledge

48 Stop

Table 4. Byte Read and Byte Write Protocol

29 Stop 28 Read

29 Acknowledge from slave

38 Not Acknowledge

39 Stop

Table 4. Byte Read and Byte Write Protocol (continued) Bit 7 23 Latched FS4 input X Latched FS[4:0] inputs. These bits are read only.

Document #: 38-07262 Rev. *B Page 8 of 21 Bit 3 15 PCI3 1 (Active/Inactive) Bit 2 13 PCI2 1 (Active/Inactive) Bit 1 12 PCI1 1 (Active/Inactive) Bit 0 11 PCI0 1 (Active/Inactive) Byte 3: Control Register 3 Bit Pin# Name Default Description Bit 7 9 3V66_2 1 (Active/Inactive) Bit 6 8 3V66_1 1 (Active/Inactive) Bit 5 7 3V66_0 1 (Active/Inactive) Bit 4 55 APIC 1 (Active/Inactive) Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 51 CPU1 1 (Active/Inactive) Bit 0 52 CPU0 1 (Active/Inactive) Byte 2: Control Register 2 (continued) Bit Pin# Name Default Description Byte 4: Control Register 4 Bit Pin# Name Default Description Bit 7 38 SDRAM7 1 (Active/Inactive) Bit 6 41 SDRAM6 1 (Active/Inactive) Bit 5 42 SDRAM5 1 (Active/Inactive) Bit 4 43 SDRAM4 1 (Active/Inactive) Bit 3 44 SDRAM3 1 (Active/Inactive) Bit 2 47 SDRAM2 1 (Active/Inactive) Bit 1 48 SDRAM1 1 (Active/Inactive) Bit 0 49 SDRAM0 1 (Active/Inactive) Byte 5: Control Register 5 Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 31 SDRAM12 1 (Active/Inactive) Bit 3 32 SDRAM11 1 (Active/Inactive) Bit 2 35 SDRAM10 1 (Active/Inactive) Bit 1 36 SDRAM9 1 (Active/Inactive) Bit 0 37 SDRAM8 1 (Active/Inactive)

Document #: 38-07262 Rev. *B Page 9 of 21 Byte 6: Vendor ID & Revision ID Register (Read Only) Bit Name Default Pin Description Bit 7 Revision_ID3 0 Revision ID bit[3] Bit 6 Revision_ID2 0 Revision ID bit[2] Bit 5 Revision_ID1 0 Revision ID bit[1] Bit 4 Revision_ID0 0 Revision ID bit[0] Bit 3 Vendor_ID3 1 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 2 Vendor_ID2 0 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 1 Vendor _ID1 0 Bit[1] of Cypress Semicon ductor’s Vendor ID. This bit is read only. Bit 0 Vendor _ID0 0 Bit[0] of Cypress Semicon ductor’s Vendor ID. This bit is read only. Byte 7: Control Register 7 Bit Pin# Name Default Pin Description Bit 7 - Reserved 0 Reserved Bit 6 24 24_48MHz_DRV 1 0 = Norm, 1 = High Drive Bit 5 23 48MHz_DRV 1 0 = Norm, 1 = High Drive Bit 4 22 48MHz_DRV 1 0 = Norm, 1 = High Drive Bit 3 24 24_48MHz 1 (Active/Inactive) Bit 2 23 48 MHz 1 (Active/Inactive) Bit 1 22 48 MHz 1 (Active/Inactive) Bit 0 -- Reserved 0 Reserved Byte 8: Watchdog Timer Register Bit Name Default Pin Description Bit 7 PCI_Skew1 0 PCI skew control 00 = Normal 01 = –500ps 10 = Reserved 11 = +500ps Bit 6 PCI_Skew0 0 Bit 5 WD_TIMER4 1 These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the pre-scaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5 sec. to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. Bit 4 WD_TIMER3 1 Bit 3 WD_TIMER2 1 Bit 2 WD_TIMER1 1 Bit 1 WD_TIMER0 1 Bit 0 WD_PRE_SCALER 0 0 = 150 ms 1 = 2.5 sec Byte 9: System RESET and Watchdog Timer Register Bit Name Default Pin Description Bit 7 SDRAM_DRV 0 SDRAM clock output drive strength 0 = Normal 1 = High Drive Bit 6 PCI_DRV 0 PCI clock output drive strength 0 = Normal 1 = High Drive Bit 5 FS_Override 0 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings

Document #: 38-07262 Rev. *B Page 10 of 21 Bit 4 RST_EN_WD 0 This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled Bit 3 RST_EN_FC 0 This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Bit 2 WD_TO_STATUS 0 Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) Bit 1 WD_EN 0 0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode. 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Note: W305B will generate system reset, re-load a recovery frequency, and lock itself into a recovery frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, W305B will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock W305B from its recovery frequency mode by clearing the WD_EN bit. Bit 0 Reserved 0 Reserved Byte 10: Skew Control Register Bit Name Default Description Bit 7 CPU_Skew2 0 CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Bit 6 CPU_Skew1 0 Bit 5 CPU_Skew0 0 Bit 4 SDRAM_Skew2 0 SDRAM skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Bit 3 SDRAM_Skew1 0 Bit 2 SDRAM_Skew0 0 Bit 1 AGP_Skew1 0 AGP skew control 00 = Normal 01 = –150ps 10 = +150ps 11 = +300ps Bit 0 AGP_Skew0 0 Byte 9: System RESET and Watchdog Timer Register (continued) Bit Name Default Pin Description

Document #: 38-07262 Rev. *B Page 11 of 21 Byte 11: Recovery Frequency N-Value Register Bit Name Default Pin Description Bit 7 ROCV_FREQ_N7 0 If ROCV_FRE Q_SEL is set, W305B will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305b will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W305Bwill change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom- mended to use Word or Block write to update both registers within the same SMBus bus operation. Bit 6 ROCV_FREQ_N6 0 Bit 5 ROCV_FREQ_N5 0 Bit 4 ROCV_FREQ_N4 0 Bit 3 ROCV_FREQ_N3 0 Bit 2 ROCV_FREQ_N2 0 Bit 1 ROCV_FREQ_N1 0 Bit 0 ROCV_FREQ_N0 0 Byte 12: Recovery Frequency M-Value Register Bit Name Default Pin Description Bit 7 ROCV_FREQ_SEL 0 ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] Bit 6 ROCV_FREQ_M6 0 If ROCV_FREQ_SEL is set, W305B will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305b will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W305B will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom- mended to use Word or Block write to update both registers within the same SMBus bus operation. Bit 5 ROCV_FREQ_M5 0 Bit 4 ROCV_FREQ_M4 0 Bit 3 ROCV_FREQ_M3 0 Bit 2 ROCV_FREQ_M2 0 Bit 1 ROCV_FREQ_M1 0 Bit 0 ROCV_FREQ_M0 0 Byte 13: Programmable Frequency Select N-Value Register Bit Name Default Pin Description Bit 7 CPU_FSEL_N7 0 If Prog_Freq_EN is set, W305B will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 6 CPU_FSEL_N6 0 Bit 5 CPU_FSEL_N5 0 Bit 4 CPU_FSEL_N4 0 Bit 3 CPU_FSEL_N3 0 Bit 2 CPU_FSEL_N2 0 Bit 1 CPU_FSEL_N1 0 Bit 0 CPU_FSEL_N0 0

Document #: 38-07262 Rev. *B Page 12 of 21 Byte 14: Programmable Frequency Select M-Value Register Bit Name Default Description Bit 7 Pro_Freq_EN 0 Programmable output frequencies enabled 0 = disabled 1 = enabled Bit 6 CPU_FSEL_M6 0 If Prog_Freq_EN is set, W305B will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B will use the frequency ratio stated in the SEL[4:0] register. W305B supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 5 CPU_FSEL_M5 0 Bit 4 CPU_FSEL_M4 0 Bit 3 CPU_FSEL_M3 0 Bit 2 CPU_FSEL_M2 0 Bit 1 CPU_FSEL_M1 0 Bit 0 CPU_FSEL_M0 0 Byte 15: Reserved Register Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 - Reserved 1 Reserved. Write with ‘1’ Bit 0 - Reserved 1 Reserved. Write with ‘1’ Byte 16: Reserved Register Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 - Reserved 0 Reserved Byte 17: Reserved Register Bit Pin# Name Default Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 - Reserved 0 Reserved

Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes

generated and a recovery frequency will be activated. All the related registers are summarized in the following table. Table 6. Register Summary will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. mended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. bits in SMBus control bytes. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. within the same SMBus bus operation.

WD_EN 0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode. 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. can unlock W305B from its recovery frequency mode by clearing the WD_EN bit. is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. RST_EN_WD This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. Table 6. Register Summary (continued) Table 7. Recommended CPU Frequency Range for Different PLL Gear Ratio

Document #: 38-07262 Rev. *B Page 16 of 21 DC parameters must be sustainable under steady state (DC) conditions. Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT req 3. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Absolute Maximum DC Power Supply Parameter Description Min. Max. Unit VDDQ3 3.3V Core Supply Voltage –0.5 4.6 V VDDQ2 2.5V I/O Supply Voltage –0.5 3.6 V TS Storage Temperature –65 150 °C Absolute Maximum DC I/O Parameter Descrip tion Min. Max. Unit Vi/o3 3.3V Core Supply Voltage –0.5 4.6 V Vi/o3 2.5V I/O Supply Voltage –0.5 3.6 V ESD prot. Input ESD Protection 2000 V DC Operating Requirements Parameter Description Condition Min. Max. Unit VDD3 3.3V Core Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ3 3.3V I/O Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ2 2.5V I/O Supply Voltage 2.5V±5% 2.375 2.625 V VDD3 = 3.3V±5% Vih3 3.3V Input High Voltage V DD3 2.0 V DD + 0.3 V Vil3 3.3V Input Low Voltage V SS – 0.3 0.8 V Iil Input Leakage Current[3] 0<Vin<VDD3 –5 +5 µA VDDQ2 = 2.5V±5% Voh2 2.5V Output High Voltage I oh=(–1 mA) 2.0 V Vol2 2.5V Output Low Voltage I ol=(1 mA) 0.4 V VDDQ3 = 3.3V±5% Voh3 3.3V Output High Voltage I oh=(–1 mA) 2.4 V Vol3 3.3V Output Low Voltage I ol=(1 mA) 0.4 V VDDQ3 = 3.3V±5% Vpoh3 PCI Bus Output High Voltage I oh=(–1 mA) 2.4 V Vpol3 PCI Bus Output Low Voltage I ol=(1 mA) 0.55 V Cin Input Pin Capacitance 5 pF Cxtal Xtal Pin Capacitance 13.5 22.5 pF Cout Output Pin Capacitance 6 pF Lpin Pin Inductance 0 7 nH Ta Ambient Temperature No Airflow 0 70 °C

Document #: 38-07262 Rev. *B Page 17 of 21 Notes: 5. The time specified is measured from when V DDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 6. T RISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification. 7. T LOW is measured at 0.4V for all outputs. Parameter Description 66.6-MHz Host 100-MHz Host 133-MHz Host THIGH Host/CPUCLK High Time 5.2 N/A 3.0 N/A 1.87 N/A ns 4,7 TLOW Host/CPUCLK Low Time 5.0 N/A 2.8 N/A 1.67 N/A ns 5 THIGH SDRAM CLK High Time 3.0 N/A 3.0 N/A 3.0 N/A ns 4 TLOW SDRAM CLK Low Time 2.8 N/A 2.8 N/A 2.8 N/A ns 5 THIGH APIC CLK High Time 25.5 N/A 25.5 N/A 25.5 N/A ns 4 TLOW APIC CLK Low Time 25.3 N/A 25.30 N/A 25.30 N/A ns 5 THIGH 3V66 CLK High Time 5.25 N/A 5.25 N/A 5.25 N/A ns 4 TLOW 3V66 CLK Low Time 5.05 N/A 5.05 N/A 5.05 N/A ns 5 TPeriod PCI CLK Period 30.0 N/A 30.0 N/A 30.0 N/A ns 4, 7 THIGH PCI CLK High Time 12.0 N/A 12.0 N/A 12.0 N/A ns 4 TLOW PCI CLK Low Time 12.0 N/A 12.0 N/A 12.0 N/A ns 5 tpLZ, tpZH Output Disable Delay (All outputs) tstable All Clock Stabilization from Power-Up 33 3 m s

Document #: 38-07262 Rev. *B Page 18 of 21 Group Skew and Jitter Limits Output Group Pin-Pin Skew Max. Cycle-Cycle Jitter Duty Cycle Nom Vdd Skew, Jitter Measure Point CPU 175 ps 250 ps 45/55 2.5V 1.25V SDRAM 250 ps 250 ps 45/55 3.3V 1.5V APIC 250 ps 500 ps 45/55 2.5V 1.25V 48MHz 250 ps 500 ps 45/55 3.3V 1.5V 3V66 175 ps 500 ps 45/55 3.3V 1.5V PCI 500 ps 500 ps 45/55 3.3V 1.5V REF N/A 1000 ps 45/55 3.3V 1.5V Clock Output Wave 2.5V Clocking 3.3V Clocking Test Point Test Load TPERIOD Duty Cycle THIGH 2.0 1.25 0.4 TLOW TRISE TFALL TLOW TRISE TFALL TPERIOD Duty Cycle THIGH 2.4 1.5 0.4 Output Buffer Interface Interface Figure 6. Output Buffer

Ordering Information

Ordering Code Package Type Operating Range W305BH 56-pin SSOP (300 mils) Commercial W305BHH 56-pin SSOP (300 mils) – Tape and Reel Commercial Lead Free CYW305OXC 56-pin SSOP (300 mils) Commercial CYW305OXCT 56-pin SSOP (300 mils) – Tape and Reel Commercial

Document #: 38-07262 Rev. *B Page 19 of 21 Layout Example G = VIA to GND plane layer V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors G +2.5V Supply 3918 G V FB +3.3V Supply Cermaic Cap C1, C3 & C5 = 10 - 22 µF C2 & C4 = .005 µF 10 mF FB C1 C2 .005 mf FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB 2012L-120 10 mF.005 mF G G G G VDDQ2VDDQ3 C6 = 0.1 µF G G 5 Ω +3.3V C5 C6 GV 0.1 µF10 µF G V GV GV GV GV W305B G G G G G G G G G G G G G G G G G G G V G V

Document #: 38-07262 Rev. *B Page 20 of 21 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Package Drawing Dimension All product and company names mentioned in this document are trademarks of their respective holders. 0.095 0.025 0.008 SEATING PLANE 0.420 0.088 .020 0.292 0.299 0.395 0.092 BSC 0.110 0.016 0.720 0.008 0.0135 0.730 DIMENSIONS IN INCHES MIN. MAX. 0.040 0.024 0°-8° GAUGE PLANE .010 128 5629 0.110 0.005 0.010 51-85062-*C 56-Lead Shrunk Small Outline Package O56

Document #: 38-07262 Rev. *B Page 21 of 21 Document History Page Document Title: W305B Frequency Controller with System Recovery for Intel Integrated Core Logic Document Number: 38-07262 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110527 12/02/01 SZV Change from Spec number: 38-01099 to 38-07262 *A 122861 12/22/02 RBI Added power up requirements to Recommended Operating Conditions *B 260010 See ECN RGL Added Lead Free Devices