W209C

W209CH CYPRESS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• Maximized EMI suppression using Cypress’s Spread Spectrum technology  Low jitter and tightly controlled clock skew  Highly integrated device providing clocks required for CPU, core logic, and SDRAM  Two copies of CPU clock  Nine copies of SDRAM clock  Eight copies of PCI clock  One copy of synchronous APIC clock  Two copies of 66-MHz outputs  Two copies of 48-MHz outputs  One copy of selectable 24- or 48-MHz clock  One copy of double strength 14.31818-MHz reference clock  Power-down control  SMBus interface for turning off unused clocks Key Specifications APIC, 48-MHz, 3V66, PCI Outputs

Table 1. Frequency Selections

1. Internal pull-down or pull-up resistors present on inputs marked with

or pull-down resistor to set I/O pins HIGH or LOW respectively.

Document #: 38-07171 Rev. *A Page 2 of 16 I Pin Definitions Pin Name Pin No. Pin Type Pin Description REF2x/FS3 1 I/O Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock out- put. This pin also serves as the select strap to determine device operating frequency as described in Table 1. X1 3 I Crystal Input: This pin has dual functions. It can be used as an external 14.318- MHz crystal connection or as an external reference frequency input. X2 4 I Crystal Output: An input connection for an external 14.318-MHz crystal connec- tion. If using an external reference, this pin must be left unconnected. FS0*/PCI0 10 I/O PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. FS1*/PCI1 11 I/O PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. FS2*/PCI2 12 I/O PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI3:7 14, 15, 17, 18, O PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually turned off via SMBus interface. 3V66_0:1 7,8 O 66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled by FS0:4 (see Table 1). 48MHz_0 21 O 48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output. FS4*/ 48MHz_1 22 I/O 48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread spectrum clock output. This pin also serves as the select strap to determine device operating frequency as described in Table 1. SIO/ 24_48#MHz* 23 I/O Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device. During power up, it also serves as a selection strap. If it is sampled HIGH, the output frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz. PWRDWN# 29 I Power Down Control: LVTTL-compatible input that places the device in power- down mode when held LOW. CPU0:1 45, 44 O CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:4. Voltage swing is set by VDDQ2. SDRAM0:7, DCLK 41, 40, 39, 37, 36, 35, 33, 32, O SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The operating fre- quency is controlled by FS0:4 (see Table 1). APIC 47 O Synchronous APIC Clock Outputs: Clock outputs running synchronous with the PCI clock outputs. Voltage swing set by VDDQ2. SDATA 25 I/O Data pin for SMBus circuitry. SCLK 28 I Clock pin for SMBus circuitry. VDDQ3 2, 6, 16, 24, 27, 34, 42 P 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. VDDQ2 46, 48 P 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con- nect to 2.5V or 3.3V. GND 5, 9, 13, 20, 26, 30, 38, 43, G Ground Connections: Connect all ground pins to the common system ground plane.

A block write begins with a slave address and a write condition. example of a possible byte count value. mand code and byte count bytes are ignored by the W209C. quence to maintain proper byte allocation.

1. The acknowledgment bit is returned by the slave/receiver (W209C).
2. Bytes 6 and 7 are not defined for W209C.

Figure 7. An Example of a Block Write[6] Table 2. Example of Possible Byte Count Value Table 3. Serial Data Interface Control Functions Summary Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. No user application. Register bit must be written as 0.

Document #: 38-07171 Rev. *A Page 7 of 16 W209C Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 2. All unused register bits (reserved and N/A) should be writ- ten to a “0” level. 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Failure to do so may result in high- er than normal operating current. The controller will read back the written value. Note: 8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. Byte 0: Control Register (1 = Enable, 0 = Disable)[8] Bit Pin# Name Default Pin Function Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 23 24/48 MHz 1 (Active/Inactive) Bit 1 21, 22 48 MHz 1 (Active/Inactive) Bit 0 - Reserved 0 Reserved Byte 1: Control Register (1 = Enable, 0 = Disable) [8] Bit Pin# Name Default Pin Description Bit 7 32 SDRAM7 1 (Active/Inactive) Bit 6 33 SDRAM6 1 (Active/Inactive) Bit 5 35 SDRAM5 1 (Active/Inactive) Bit 4 36 SDRAM4 1 (Active/Inactive) Bit 3 37 SDRAM3 1 (Active/Inactive) Bit 2 39 SDRAM2 1 (Active/Inactive) Bit 1 40 SDRAM1 1 (Active/Inactive) Bit 0 41 SDRAM0 1 (Active/Inactive) Byte 2: Control Register (1 = Enable, 0 = Disable) [8] Bit Pin# Name Default Pin Description Bit 7 19 PCI7 1 (Active/Inactive) Bit 6 18 PCI6 1 (Active/Inactive) Bit 5 17 PCI5 1 (Active/Inactive) Bit 4 15 PCI4 1 (Active/Inactive) Bit 3 14 PCI3 1 (Active/Inactive) Bit 2 12 PCI2 1 (Active/Inactive) Bit 1 11 PCI1 1 (Active/Inactive) Bit 0 10 PCI0 1 (Active/Inactive)

Document #: 38-07171 Rev. *A Page 8 of 16 Byte 3: Reserved Register (1 = Enable, 0 = Disable) Bit Pin# Name Default Pin Description Bit 7 31 DCLK 1 (Active/Inactive) Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 47 APIC 1 (Active/Inactive) Bit 2 - Reserved 0 Reserved Bit 1 - Reserved 1 Reserved Bit 0 - Reserved 0 Reserved Byte 4: Reserved Register (1 = Enable, 0 = Disable) Bit Pin# Name Default Pin Function Bit 7 - SEL3 0 See Table 4 Bit 6 - SEL2 0 See Table 4 Bit 5 - SEL1 0 See Table 4 Bit 4 - SEL0 0 See Table 4 Bit 3 - FS(0:4) Override 0 0 = Select operating frequency by FS(0:4) strapping 1 = Select operating frequency by SEL(0:4) bit settings Bit 2 - SEL4 0 See Table 4 Bit 1 - Reserved 1 Reserved Bit 0 - Test Mode 0 0 = Normal 1 = Three-stated Byte 5: Reserved Register (1 = Enable, 0 = Disable) Bit Pin# Name Default Pin Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 0 Reserved Bit 1 - Reserved 0 Reserved Bit 0 - Reserved 0 Reserved Byte 6: Reserved Register (1 = Enable, 0 = Disable) Bit Pin# Name Default Pin Description Bit 7 - Reserved 0 Reserved Bit 6 - Reserved 0 Reserved Bit 5 - Reserved 0 Reserved Bit 4 - Reserved 0 Reserved Bit 3 - Reserved 0 Reserved Bit 2 - Reserved 1 Reserved Bit 1 - Reserved 1 Reserved Bit 0 - Reserved 0 Reserved

Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes

Document #: 38-07171 Rev. *A Page 10 of 16 DC parameters must be sustainable under steady state (DC) conditions. Absolute Maximum DC Power Supply Parameter Description Min. Max. Unit VDDQ3 3.3V Core Supply Voltage –0.5 4.6 V VDDQ2 2.5V I/O Supply Voltage –0.5 3.6 V TS Storage Temperature –65 150 °C Absolute Maximum DC I/O Parameter Description Min. Max. Unit Vi/o3 3.3V Core Supply Voltage –0.5 4.6 V Vi/o3 2.5V I/O Supply Voltage –0.5 3.6 V ESD prot. Input ESD Protection 2000 V Note: 9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

Document #: 38-07171 Rev. *A Page 11 of 16 Note: 10. Input Leakage Current does not include inputs with pull-up or pull-down resistors. DC Operating Requirements Parameter Description Condition Min. Typ. Max. Unit VDD3 3.3V Core Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ3 3.3V I/O Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ2 2.5V I/O Supply Voltage 2.5V±5% 2.375 2.625 V VDD3 = 3.3V±5% Vih3 3.3V Input High Voltage V DD3 2.0 V DD + 0.3 V Vil3 3.3V Input Low Voltage V SS – 0.3 0.8 V Iil Input Leakage Current[10] 0<Vin<VDD3 –5+ 5 µ A VDDQ2 = 2.5V±5% Voh2 2.5V Output High Voltage I oh=(–1 mA) 2.0 V Vol2 2.5V Output Low Voltage I ol=(1 mA) 0.4 V VDDQ3 = 3.3V±5% Voh3 3.3V Output High Voltage I oh=(–1 mA) 2.4 V Vol3 3.3V Output Low Voltage I ol=(1 mA) 0.4 V VDDQ3 = 3.3V±5% Vpoh3 PCI Bus Output High Voltage I oh=(–1 mA) 2.4 V Vpol3 PCI Bus Output Low Voltage I ol=(1 mA) 0.55 V C in Input Pin Capacitance 5 pF C xtal Xtal Pin Capacitance 13.5 22.5 pF C out Output Pin Capacitance 6 pF Lpin Pin Inductance 0 7 nH Ta Ambient Temperature No Airflow 0 70 °C IOL Output Low Current PCI0:7 V OL = 1.5V 20 40 90 mA REF2X/FS3 V OL = 1.5V 20 40 90 mA 48 MHz V OL = 1.5V 20 40 90 mA 24 MHz V OL = 1.5V 20 40 90 mA SDRAM0:12 V OL = 1.5V 60 100 160 mA CPU0:1 V OL = 1.25V 25 50 95 mA IOH Output High Current PCI0:7 V OH = 1.5V 20 40 90 mA REF2X/FS3 V OH = 1.5V 20 40 90 mA 48 MHz V OH = 1.5V 20 40 90 mA 24 MHz V OH = 1.5V 20 40 90 mA SDRAM0:12 V OH = 1.5V 60 100 160 mA CPU0:1 V OH = 1.25V 25 50 95 mA

Document #: 38-07171 Rev. *A Page 12 of 16 TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% fXTL = 14.31818 MHz Notes: 13. TLOW is measured at 0.4V for all outputs. 14. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 15. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification. Parameter Description 66.6-MHz Host 100-MHz Host 133-MHz Host THIGH Host/CPUCLK High Time 5.2 N/A 3.0 N/A 1.87 N/A ns 14 TLOW Host/CPUCLK Low Time 5.0 N/A 2.8 N/A 1.67 N/A ns 15 THIGH SDRAM CLK High Time 3.0 N/A 3.0 N/A 3.0 N/A ns 14 TLOW SDRAM CLK Low Time 2.8 N/A 2.8 N/A 2.8 N/A ns 15 TPeriod APIC 33-MHz CLK Period 30.0 N/A 30.0 N/A 30.0 N/A ns 11 THIGH APIC 33-MHz CLK High Time 12.0 N/A 12.0 N/A 12.0 N/A ns 14 TLOW APIC 33-MHz CLK Low Time 12.0 N/A 12.0 N/A 12.0 N/A ns 15 THIGH 3V66 CLK High Time 5.25 N/A 5.25 N/A 5.25 N/A ns 14 TLOW 3V66 CLK Low Time 5.05 N/A 5.05 N/A 5.05 N/A ns 15 TPeriod PCI CLK Period 30.0 N/A 30.0 N/A 30.0 N/A ns 11, 12 THIGH PCI CLK High Time 12.0 N/A 12.0 N/A 12.0 N/A ns 14 TLOW PCI CLK Low Time 12.0 N/A 12.0 N/A 12.0 N/A ns 15 tpLZ, tpZH Output Disable Delay (All outputs) tstable All Clock Stabilization from Power-Up 33 3 m s

Document #: 38-07171 Rev. *A Page 13 of 16 Intel is a registered trademark of Intel Corporation. Group Skew and Jitter Limits Output Group Pin-Pin Skew Max. Cycle-Cycle Jitter Duty Cycle Nom Vdd Skew, Jitter Measure Point Typical Output Impedance CPU 175 ps 250 ps 45/55 2.5V 1.25V 21 Ω SDRAM 250 ps 250 ps 45/55 3.3V 1.5V 14 Ω APIC 250 ps 500 ps 45/55 2.5V 1.25V 16 Ω 48MHz 250 ps 500 ps 45/55 3.3V 1.5V 21 Ω 3V66 175 ps 500 ps 45/55 3.3V 1.5V 14 Ω PCI 500 ps 500 ps 45/55 3.3V 1.5V 14 Ω REF N/A 1000 ps 45/55 3.3V 1.5V 11 Ω Clock Output Wave 2.5V Clocking 3.3V Clocking Test Point Test Load TPERIOD Duty Cycle THIGH 2.0 1.25 0.4 TLOW TRISE TFALL TLOW TRISE TFALL TPERIOD Duty Cycle THIGH 2.4 1.5 0.4 Output Buffer Interface Interface Figure 8. Output Buffer

Ordering Information

Ordering Code Package Name Package Type W209C H 48-pin SSOP (300 mils)

Document #: 38-07171 Rev. *A Page 14 of 16 Layout Diagram G = VIA to GND plane layer V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors G +2.5V Supply C1 C2 FB +3.3V Supply C1 & C3 = 10–22 µF C2 & C4 = 0.005µF 10 µF FB C1 C2 µ 0.005 µf FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) 10 µF0.005 µF G G G G VDDQ2VDDQ3 C6 = 0.1 µF G G VDDQ3 C5 C6 GV G V G V G V GV GV GV GV VDDQ3 Core W209C G G G G G G G G G G G G G G G G G G G G C5 = 47 µF

Document #: 38-07171 Rev. *A Page 15 of 16 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 48-Pin Shrink Small Outline Package (SSOP , 300 mils)

Document #: 38-07171 Rev. *A Page 16 of 16 Document Title: W209C Frequency Generator for Integrated Core Logic with 133-MHz FSB Document Number: 38-07171 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110281 11/05/01 SZV Change from Spec number: 38-00845 to 38-07171 *A 122812 12/21/02 RBI Add Power up Requirements to Electrical Characteristics Information