W196_02 CYPRESS | Alldatasheet
Document overview
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Technical content
Features
- Maximized EMI suppression using Cypress’s Spread Spectrum Technology System frequency synthesizer for 440BX, 440ZX, and VIA Apollo Pro-133 I2C programmable to 155 MHz (32 selectable frequencies) Two skew-controlled copies of CPU output Seven copies of PCI output (synchronous w/CPU out- put) One copy of 14.31818-MHz IOAPIC output One copy of 48-MHz USB output Selectable 24-/48-MHz clock is determined by resistor straps on power up One high-drive output buffer that produces a copy of the 14.318-MHz reference Isolated core VDD pin for noise reduction Key Specifications VDDQ2 = 2.5V±5% Note: Internal pull-up or pull-down resistors should not be re- lied upon for setting I/O pins HIGH or LOW.
Table 1. Pin Selectable Frequency
Document #: 38-07170 Rev. *A Page 2 of 12 Pin Definitions Pin Name Pin No. Pin Type Pin Description CPU0:1 22, 21 O CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by FS0:1 or the serial data interface. See Table 1 and Table 5. Output voltage swing is set by the voltage applied to VDDQ2. PCI1:6 PCI_F 5, 6, 7, 8, 10, 11, 4 O PCI Bus Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run synchronously to the CPU clock. Voltage swing is set by the power connection to VDDQ3. IOAPIC 24 O I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set by the power connection to VDDQ2. 48MHz 13 O 48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by voltage applied to VDDQ3. 24_48MHz/FS1 14 I/O 24-MHz or 48-MHz Output/Frequency Select 1 Input: Frequency is set by the state of pin 27 on power-up. This pin doubles as the select strap to determine device operating frequency as described in Table 1. REF2X/SEL48# 27 I/O I/O Dual-Function REF2X and SEL48# Pin: Upon power-up, the state of SEL48# is latched. The initial state is set by either a 10K resistor to GND or to VDD . A 10K resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD , pin 14 will output 2 4MHz. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. FS0 16 I Frequency Selection 0 Input: Selects CPU clock frequency as shown in Table 1 on page 1. SDATA 18 I/O I 2C Data Pin: Data should be presented to this input as described in the I2C section of this data sheet. Internal 250-kΩ pull-up resistor. SCLOCK 17 I I2C Clock Pin: The I2C Data clock should be presented to this input as described in the I2C section of this data sheet. X1 1 I Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or other reference signal. X2 2 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDDQ3 9, 12, 20, 26 P Power Connection: Power supply for core logic and PLL circuitry, PCI, 48/24MHz, and Reference output buffers. Connect to 3.3V supply. VDDQ2 23, 25 P Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V supply. GND 3, 15, 19, 28 G Ground Connections: Connect all ground pins to the common system ground plane.
Data is written to the W196 in ten bytes of eight bits each. Bytes are written in the order shown in Table 3. Table 2. Serial Data Interface Control Functions Summary Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. the selections that are provided by the FS0:1 pins. Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing. ternal PLL is bypassed. Refer to Table 4. Table 3. Byte Writing Sequence
1 Slave Address 11010010 Commands the W196 to accept the bits in Data Bytes 3 –6 for internal
- Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2 Command
slave receiver on the serial data bus. receiver on the serial data bus. 4 Data Byte 0 Don ’t Care Refer to Cypress SDRAM drivers.
5 Data Byte 1
6 Data Byte 2
functions, refer to Table 4, Data Byte Serial Configuration Map.
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
- Bits are written MSB (most significant bit) first, which is bit
- Table 4 gives the bit formats for registers located in Data
able through the serial data interface. Table 6 details the select functions for Byte 3, bits 1 and 0.
- Bits 0 and 1 of Data Byte 6 in Table 4 must be programmed as the same value.
Table 4. Data Bytes 3–6 Serial Configuration Map
- CPU and PCI frequency selections are listed in Table 1 and Table 5.
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes Table 6. Select Function for Data Byte 3, Bits 0:1
Document #: 38-07170 Rev. *A Page 7 of 12 Absolute Maximum Ratings[3] Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit V DD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C ESD PROT Input ESD Protection 2 (min.) kV Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDDQ3 Combined 3.3V Supply Current CPU0:1 =100 MHz Outputs Loaded[4] 85 mA IDDQ3 Combined 2.5V Supply Current CPU0:1 =100 MHz Outputs Loaded[4] 30 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[5] –25 µA IIH Input High Current[5] 10 µA Clock Outputs VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V VOH Output High Voltage CPU0:1/IOAPIC IOH = –1 mA 2.2 V IOL Output Low Current CPU0:1 V OL = 1.25V 45 60 80 mA PCI_F, PCI1:6 V OL = 1.5V 85 110 140 mA IOAPIC V OL = 1.25V 65 90 140 mA REF2X V OL = 1.5V 110 140 170 mA 48MHz, 24MHz V OL = 1.5V 50 70 90 mA IOH Output High Current CPU0:1 V OL = 1.25V 35 50 80 mA PCI_F, PCI1:6 V OL = 1.5V 60 95 130 mA IOAPIC V OL = 1.25V 45 87 140 mA REF2X V OL = 1.5V 100 130 150 mA 48MHz, 24MHz V OL = 1.5V 50 70 90 mA Crystal Oscillator V TH X1 Input Threshold Voltage[6] VDDQ3 = 3.3V 1.65 V C LOAD Load Capacitance, as seen by External Crystal[7] 14 pF C IN,X1 X1 Input Capacitance[8] Pin X2 unconnected 28 pF Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required 4. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section. 5. W196 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level). 6. X1 input threshold voltage (typical) is VDD /2. 7. The W196 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07170 Rev. *A Page 8 of 12 TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. Pin Capacitance/Inductance C IN Input Pin Capacitance Except X1 and X2 5 pF C OUT Output Pin Capacitance 6p F LIN Input Pin Inductance 7n H Parameter Description Test Condition Min. Typ. Max. Unit CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 15 15.5 10 10.5 ns tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max- imum difference of cycle time between two adjacent cycles. 200 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Z o AC Output Impedance Average value during switching transi- tion. Used for determining series termi- nation value. 20 20 Ω
Document #: 38-07170 Rev. *A Page 9 of 12 PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments CPU = 66.8/100 MHz UnitMin. Typ. Max. tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 14 n s fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 Ω IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8/100 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.31818 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω REF2X Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8/100 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω
Document #: 38-07170 Rev. *A Page 10 of 12 48-MHZ and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 24.004 MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17, 57/34 t R Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 Ω
Ordering Information
W196 G 28-pin SOIC (300 mils)
Document #: 38-07170 Rev. *A Page 11 of 12 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 28-Pin Small Outline Integrated Circuit (SOIC, 300 mils)
Document #: 38-07170 Rev. *A Page 12 of 12 Document Title: W196 Spread Spectrum FTG for 440BX And VIA Apollo Pro-133 Document Number: 38-07170 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110280 11/05/01 SZV Change from Spec number: 38-00842 to 38-07170 *A 122811 12/15/02 RBI Add Power up Requirements to Maximum Ratings Information