W194

W194 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

• Two outputs  Configuration options allow various multiplications of the reference frequency—refer to Table 1 to determine the specific option which meets your multiplication needs  Available in 8-pin SOIC package Key Specifications Propagation delay is affected by input rise time.

Table 1. Configuration Options

imum flexibility when implementing the Zero Delay feature. pendent problems experienced by users of the older device. IN 2 I Reference Input: The output signals will be synchronized to this signal. signals received at the destinations will be synchronized to the REF signal input (IN). signal connected to FBIN, and the FS0:1 inputs (see Table 1). GND 3 P Ground Connection: Connect all grounds to the common system ground plane. FS0:1 4, 5 I Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1. Figure 1. Schematic/Suggested Layout

External feedback is the trait that allows for this compensation. feedback and the FBIN input to the PLL. traces to the devices being clocked. time the Reference clock provided to the ZDB goes HIGH. Figure 2. 6 Output Buffer in the Feedback Path

Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient T emperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W Parameter Description Test Condition Min Typ Max Unit IDD Supply Current Unloaded, 100 MHz 17 35 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 12 mA IOL = 8 mA 0.4 V VOH Output High Voltage I OL = 12 mA IOL = 8 mA 2.4 V IIL Input Low Current V IN = 0V 5 µA IIH Input High Current V IN = VDD 5 µA Parameter Description Test Condition Min Typ Max Unit IDD Supply Current Unloaded, 100 MHz 17 35 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 12 mA IOL = 8 mA 0.4 V VOH Output High Voltage I OL = 12 mA IOL = 8 mA 2.4 V IIL Input Low Current V IN = 0V 5 µA IIH Input High Current V IN = VDD 5 µA

Document #: 38-00794-A Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency[1] OUT2 = REF MHz fOUT Output Frequency OUT1 15-pF load [6] 10 133 MHz tR Output Rise Time 2.0V to 0.8V , 15-pF load 3.5 ns tF Output Fall Time 2.0V to 0.8V , 15-pF load 2.5 ns tICLKR Input Clock Rise Time[2] 10 ns tICLKF Input Clock Fall Time[2] 10 ns tPD FBIN to REF Skew[3, 4] Measured at VDD /2 –20 . 6 2 n s tD Duty Cycle 15-pF load [5] 40 50 60 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle 300 ps Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency[1] OUT2 = REF MHz fOUT Output Frequency OUT1 15-pF load [6] 10 133 MHz tR Output Rise Time 2.0V to 0.8V , 15-pF load 2.5 ns tF Output Fall Time 2.0V to 0.8V , 15-pF load 1.5 ns tICLKR Input Clock Rise Time[2] 10 ns tICLKF Input Clock Fall Time[2] 10 ns tPD FBIN to REF Skew[3, 4] Measured at VDD /2 –20 . 6 2 n s tD Duty Cycle 15-pF load [5, 7] 40 50 60 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle 200 ps Notes: 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V . 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V . 6. For the higher drive -11, the load is 20 pF . 7. Duty Cycle measured at 120 MHz. For 133 MHz, degrades to 35/65 worst case.

Ordering Information

W194 -70 G 8-pin SOIC (150-mil)

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 8-Pin Small Outlined Integrated Circuit (SOIC, 150-mil)