W181-01GT CYPRESS | Alldatasheet

Document overview

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  • PDF pages: 9

Technical content

Features

  • Cypress PREMIS™ family offering
  • Generates an EMI optimized clocking signal at the output
  • Selectable input to output frequency
  • Single 1.25% or 3.75% down or center spread output
  • Integrated loop filter components
  • Operates with a 3.3V or 5V supply
  • Low-power CMOS design
  • Available in 8-pin small outline integrated circuit (SOIC) or 14-pin thin shrink small outline package (TSSOP select options only) Simplified Block Diagram Pin Configurations W181-02/038 CLKIN or X1 NC or X2 GND SS% SSON# FS1 VDD CLKOUT W181-01/51 CLKIN or X1 NC or X2 GND SS% FS2 FS1 VDD CLKOUT SOIC Spread Spectrum W181 (EMI suppressed) 3.3 or 5.0V Oscillator or Spread SpectrumW181 (EMI suppressed) 3.3 or 5.0V XTAL Reference Input Input Output Output

40 MHz

Max. W181-011 NC or X2 GND SS% NC FS1 VDD CLKOUT 14FS2 NC NC NC NC NC TSSOP W181-52/53 CLKIN or X1

testing without resorting to costly shielding or redesign. but also in all signals which are synchronized to the clock. modulating waveform is superimposed at the input to the VCO. predetermined frequency band. unmodulated input clock (SSON# asserted). to an external reference clock. VDD 6 10 P Power Connection: Connected to 3.3V or 5V power supply. Table 1. Modulation Width Selection Table 2. Frequency Range Selection

Document #: 38-07152 Rev. *D Page 5 of 9 Absolute Maximum Conditions[2] Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W Parameter Description Test Condition Min. Typ. Max. Unit IDD Supply Current – 18 32 mA tON Power-Up Time First locked clock cycle after Power Good ––5 m s VIL Input Low Voltage – – 0.8 V VIH Input High Voltage 2.4 – – V VOL Output Low Voltage – – 0.4 V VOH Output High Voltage 2.4 – – V IIL Input Low Current Note 3 – – –100 µA IIH Input High Current Note 3 – – 10 µA IOL Output Low Current @ 0.4V, V DD = 3.3V – 15 – mA IOH Output High Current @ 2.4V, V DD = 3.3V – 15 – mA CI Input Capacitance All pins except CLKIN – v 7 pF CI Input Capacitance CLKIN pin only – 6 10 pF RP Input Pull-Up Resistor[3] –5 0 0– k Ω ZOUT Clock Output Impedance – 25 – Ω Parameter Description Test Condition Min. Typ. Max. Unit IDD Supply Current 30 50 mA tON Power-Up Time First locked clock cycle after Power Good 5m s VIL Input Low Voltage 0.15V DD V VIH Input High Voltage 0.7V DD V VOL Output Low Voltage 0.4 V VOH Output High Voltage 2.4 V IIL Input Low Current Note 3 –100 µA IIH Input High Current Note 3 10 µA IOL Output Low Current @ 0.4V, V DD = 5V 24 mA IOH Output High Current @ 2.4V, V DD = 5V 24 mA CI Input Capacitance All pins except CLKIN 7 pF CI Input Capacitance CLKIN pin only 6 10 pF RP Input Pull-Up Resistor 500 k Ω Notes: 1. Stresses greater than those listed in this table may cause per manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability 2. Single Power Supply: The voltage on any input or I/ O pin cannot exceed the power pin during power-up. 3. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor.

Document #: 38-07152 Rev. *D Page 7 of 9

Ordering Information

Ordering Code Package Type Product Flow W181-01G 8-pin Plastic SOIC (150-mil) Commercial, 0° to 70°C W181-01GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-02G 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C W181-02GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-03G 8 pin Plastic SOIC (150-mil Commercial, 0° to 70°C W181-03GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-51G 8-pin Plastic SOIC (150-mil) Commercial, 0° to 70°C W181-51GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-52G 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C W181-52GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-53G 8 pin Plastic SOIC (150-mil Commercial, 0° to 70°C W181-53GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-01X 14-pin Plastic TSSOP Commercial, 0° to 70°C W181-01XT 14-pin Plastic TSSOP – Tape and Reel Commercial, 0° to 70°C Lead-free Devices CYW181-01SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-01SXT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-02SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-02SXT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-03SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-03SXT 8 pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-51SX 8 pin Plastic SOIC (150-mil)) Commercial, 0° to 70°C CYW181-51SXT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-52SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-52SXT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-53SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-53SXT 8 pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C Figure 5. Recommended Board Layout (2-Layer Board) capacitor (0.1-µF recommended).

Document #: 38-07152 Rev. *D Page 8 of 9 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PREMIS is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trade- marks of their respective holders. Package Drawing and Dimension P I N1I D SEATING PLANE BSC. BSC 0°-8° PLANE GAUGE 4.90[0.193] 1.10[0.043] MAX. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] 14-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z14 51-85117-*A DIMENSIONS IN MM(INCHES) SEATING PLANE P I N1I D 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 0°~8° 0.016[0.406] 0.010[0.254] X 45° 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.004[0.102]

8 Lead (150 Mil) SOIC - S08

  1. REFERENCE JEDEC MS-012 PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 4. PACKAGE WEIGHT 0.07gms 51-85066-*C 8-lead (150-Mil) SOIC S8

Document #: 38-07152 Rev. *D Page 9 of 9 Document History Page Document Title: W181 Peak Reducing EMI Solution Document Number: 38-07152 REV. ECN No. Issue Date Orig. of Change Description of Change ** 110262 12/15/01 SZV Change from Spec number: 38-00790 to 38-07152 *A 122687 12/27/02 RBI Added power up requirements to maximum ratings information. *B 127906 07/07/03 IJA Changed Modulation Width Selection values in Table 1 Added CLKOUT Frequency Offset Table Created Cypress approved drawings to replace old ones Updated Ordering Information to clarify and match ordering codes to Dev Master *C 131492 01/22/04 RGL Added Lead-free for all t he SOIC packages in the ordering information *D 241879 See ECN RGL Corrected the Lead Free Coding in the Ordering Information table