W180

W180 CYPRESS | Alldatasheet

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Features

 Cypress PREMIS™ family offering  Generates an EMI optimized clocking signal at the output  Selectable output frequency range  Single 1.25% or 3.75% down or center spread output  Integrated loop filter components  Operates with a 3.3V or 5V supply  Low power CMOS design  Available in 8-pin SOIC (Small Outline Integrated Circuit) Key Specifications or VDD = 5V±10% Table 1. Modulation Width Selection Table 2. Frequency Range Selection PREMIS is a trademark of Cypress Semiconductor Corporation.

Pin Name Pin No. Pin Type Pin Description CLKOUT 5 O Output Modulated Frequency: Frequency modulated copy of the unmodu- lated input clock (SSON# asserted). CLKIN or X1 1 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. NC or X2 2 I Crystal Connection: Input connection for an external crystal. If using an ex- ternal reference, this pin must be left unconnected. SSON# 8 (-02, -03 52, 53) I Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. FS1:2 7, 8 (-01, 51) I Frequency Selection Bit(s) 1 and 2: These pins select the frequency range of operation. Refer to Ta ble 2. These pins have internal pull-up resistors. SS% 4 I Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. Internal pull-up resistor. VDD 6 P Power Connection: Connected to 3.3V or 5V power supply. GND 3 G Ground Connection: This should be connected to the common ground plane.

without resorting to costly shielding or redesign. but also in all signals which are synchronized to the clock. reference signal is divided by Q and fed to the phase detector. modulating waveform is superimposed at the input to the VCO. cess has little impact on system performance. frequency , the modulation percentage may be varied. spreading percentages options are provided. Figure 1. Functional Block Diagram

Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only . Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability . Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TA Operating T emperature 0 to +70 °C TB Ambient T emperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W Parameter Description Test Condition Min. Typ. Max. Unit IDD Supply Current 18 32 mA tON Power Up Time First locked clock cycle after Power Good 5m s VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.4 V VOL Output Low Voltage 0.4 V VOH Output High Voltage 2.4 V IIL Input Low Current Note 1 –50 µA IIH Input High Current Note 1 50 µA IOL Output Low Current @ 0.4V , V DD = 3.3V 15 mA IOH Output High Current @ 2.4V , V DD = 3.3V 15 mA C I Input Capacitance 7p F R P Input Pull-Up Resistor 500 k Ω ZOUT Clock Output Impedance 25 Ω Note: 1. Inputs FS2:1& SS% have a pull-up resistor; Input SSON# has a pull-down resistor.

Parameter Description Test Condition Min. Typ. Max. Unit IDD Supply Current 30 50 mA tON Power Up Time First locked clock cycle after Power Good 5m s VIL Input Low Voltage 0.15V DD V VIH Input High Voltage 0.7V DD V VOL Output Low Voltage 0.4 V VOH Output High Voltage 2.4 V IIL Input Low Current Note 2 –50 µA IIH Input High Current Note 2 50 µA IOL Output Low Current @ 0.4V , V DD = 5V 24 mA IOH Output High Current @ 2.4V , V DD = 5V 24 mA C I Input Capacitance 7p F R P Input Pull-Up Resistor 500 k Ω ZOUT Clock Output Impedance 25 Ω Symbol Parameter Test Condition Min. Typ. Max. Unit. fIN Input Frequency (-01) Input Clock, Note 3 8 28 MHz fOUT Output Frequency (-01) Spread O ff, Note 3 8 28 MHz tR Output Rise Time 15-pF load 0.8V –2.4V 2 5 ns tF Output Fall Time 15-pF load 2.4 –0.8V 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 250 300 ps Harmonic Reduction f out = 20 MHz, third harmonic measured, reference board, 15-pF load 8d B Notes: 2. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor. 3. Frequency range listed for -01 version. See Table 2 for frequency range of -02 and -03 versions.

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 8-Pin Small Outline Integrated Circuit (SOIC, 150 mils)