W170

W170-01 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

• Spread Aware™—designed to work with SSFTG reference signals  Two outputs  Configuration options allow various multiplication of the reference frequency, refer to Table 1 to determine the specific option which meets your multiplication needs  Available in 8-pin SOIC package Key Specifications Propagation delay is affected by input rise time.

Table 1. Configuration Options Spread Aware is a trademark of Cypress Semiconductor Corporation.

The W170-01 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing max- imum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this data sheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.” The W170-01 is a pin-compatible upgrade of the Cypress W42C70-01. The W170-01 addresses some application de- pendent problems experienced by users of the older device. Most importantly, it addresses the tracking skew problem in- duced by a reference which has Spread Spectrum Timing en- abled on it. Spread Aware Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we de- signed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, “EMI Suppres- sion T echniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.” Pin Definitions Pin Name Pin No. Pin Type Pin Description IN 2 I Reference Input: The output signals will be synchronized to this signal. FBIN 1 I Feedback Input: This input must be fed by one of the outputs (OUT1 or OUT2) to ensure proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal desti- nations, then the signals received at the destinations will be synchronized to the REF signal input (IN). OUT1 6 O Output 1: The frequency of the signal provided by this pin is determined by the feed- back signal connected to FBIN, and the FS0:1 inputs (see Table 1). OUT2 8 O Output 2: The frequency of the signal provided by this pin is one-half of the frequency of OUT1. See Ta ble 1. VDD 7 P Power Connections: Connect to 3.3V or 5V . This pin should be bypassed with a 0.1-µF decoupling capacitor. Use ferrite beads to help reduce noise for optimal jitter performance. GND 3 P Ground Connection: Connect all grounds to the common system ground plane. FS0:1 4, 5 I Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per Table 1.

Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient T emperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W Parameter Description Test Condition Min Typ Max Unit IDD Supply Current Unloaded, 133 MHz 17 35 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 8 mA 0.4 V VOH Output High Voltage I OH = 8 mA 2.4 V IIL Input Low Current V IN = 0V 5 µA IIH Input High Current V IN = VDD 5 µA Parameter Description Test Condition Min Typ Max Unit IDD Supply Current Unloaded, 133 MHz 31 50 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 8 mA 0.4 V VOH Output High Voltage I OH = 8 mA 2.4 V IIL Input Low Current V IN = 0V 5 µA IIH Input High Current V IN = VDD 5 µA

Document #: 38-00795 Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency[1] OUT2 = REF MHz fOUT Output Frequency OUT1 20 133 MHz tR Output Rise Time 0.8V to 2.0V , 15-pF load 3.5 ns tF Output Fall Time 2.0V to 0.8V , 15-pF load 2.5 ns tICLKR Input Clock Rise Time[2] 10 ns tICLKF Input Clock Fall Time[2] 10 ns tPD FBIN to IN (Reference Input) Skew[3, 4] Note 4 300 ps tD D u t y C y c l e N o t e 5 4 05 06 0% tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle Note 6 200 ps Parameter Description Test Condition Min Typ Max Unit fIN Input Frequency[1] OUT2 = REF MHz fOUT Output Frequency OUT1 20 133 MHz tR Output Rise Time 0.8V to 2.0V , 15-pF load 3.5 ns tF Output Fall Time 2.0V to 0.8V , 15-pF load 2.5 ns tICLKR Input Clock Rise Time[2] 10 ns tICLKF Input Clock Fall Time[2] 10 ns tPD FBIN to IN (Reference Input) Skew[3, 4] Note 4 300 ps tD Duty Cycle Note 7, 8 40 50 60 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle Note 6 200 ps Notes: 1. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). 2. Longer input rise and fall time will degrade skew and jitter performance. 3. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V . 4. Skew is measured at 1.4V on rising edges. 5. Duty cycle is measured at 1.4V . 6. Jitter is measured on 133-MHz signal at 1.4V. 7. Duty cycle is measured at 1.4V , 120 MHz. 8. Duty cycle at 133 MHz is 35/65 worst case.

Ordering Information

W170 -01 G 8-pin SOIC (150 mil)

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 8-Pin Small Outlined Integrated Circuit (SOIC, 150 mil)