W161 CYPRESS | Alldatasheet
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Technical content
Features
- Maximized EMI Suppression using Cypress’s Spread Spectrum Technology Three copies of CPU outputs at 100 or 133 MHz Three copies of 66-MHz output at 3.3V Ten copies of PCI clocks at 33 MHz, 3.3V Two copies of 14.318-MHz reference output at 3.3V One copy of 48-MHz USB clock One copy of CPU-divide-by-2 output as reference input to Direct Rambus™ Clock Generator (Cypress W134) Available in 48-pin SSOP (300 mils) Key Specifications VDDQ3 = 3.3V±5% Pentium is a registered trademark of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Table 1. Pin Selectable Frequency
- Internal 250-kΩ pull-up resistors present on inputs marked with *.
The W161, a motherboard clock synthesizer, provides 2.5V CPU clock outputs for advanced CPU and a CPU-divide-by-2 reference frequency for Direct Rambus Clock Generator (such Cypress W134) interface. Fixed output frequencies are provid- ed for other system functions. CPU Frequency Selection CPU frequency is selected with input pins 25, 29, and 30 (SEL133/100#, SEL0, and SEL1, respectively). Refer to Ta ble 1 for details. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The W161 outputs are CMOS-type, which provide rail-to-rail output swing. Crystal Oscillator The W161 requires one input reference clock to synthesize all output frequencies. The reference clock can be either an ex- ternally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The W161 incor- porates the necessary feedback resistor and crystal load ca- pacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 18 pF . For opti- mum frequency accuracy without the addition of external ca- pacitors, a parallel-resonant mode crystal specifying a load of 18 pF should be used. This will typically yield reference fre- quency accuracies within ±100 ppm. Pin Definitions Pin Name Pin No. Pin Type Pin Description CPU0:2 36, 37, 40 O CPU Clock Outputs 0 through 2: CPU clock outputs. Their output voltage swing is controlled by voltage applied to VDDQ2. PCI0:9 7, 8, 10, 11, 12, 13, 15, 16, 18, O PCI Clock Outputs 0 through 9: Output voltage swing is controlled by voltage applied to VDDQ3. CPUdiv2 43 O CPU-Divide-By-2 Output: This serves as a reference input signal for Direct Rambus Clock Generator (Cypress W134). The output voltage is determined by VDDQ2. 3V66_0:2 21, 22, 23 O 66-MHz Clock Outputs 0 through 2: Output voltage swing is controlled by voltage applied to VDDQ3. IOAPIC 46 O I/O APIC Clock Output: Provides an output synchronous to CPU clock. See Table 1 for their relation to other system clock outputs. 48 MHz 27 O 48-MHz Output: Fixed clock output at 48 MHz. SPREAD# 31 I Spread Spectrum Enable: This input enables spread spectrum modulation on the PLL1 generated frequency outputs of the W161. Modulation range is –0.5%. PWRDWN# 32 I Power Down Control REF0:1 1, 2 I Fixed 14.318-MHz Output 0 and 1: Output voltage swing is controlled by voltage applied to VDDQ3. SEL0:1 29, 30 I Mode Select Input 0 through 1: 3.3V LVTTL-compatible input for selecting clock output modes. As shown in Ta ble 1. SEL133/100# 25 I Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output frequency as shown in Table 1. X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDDQ2 38, 41, 44, 47 P Power Connection: Connected to 2.5V power supply. VDDQ3 3, 9, 17, 24, 28, P Power Connection: Connected to 3.3V power supply. GND 6, 14, 20, 26, 33, 35, 39, 42, 45, 48 G Ground Connection: Connect all ground pins to the common system ground plane.
Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient T emperature under Bias –55 to +125 °C ESD PROT Input ESD Protection 2 (min.) kV Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD-3.3V Combined 3.3V Supply Current CPU0:3 =133 MHz [2] 160 mA IDD-2.5 Combined 2.5V Supply Current CPU0:3 =133 MHz [2] 90 mA Logic Inputs (All referenced to VDDQ3 = 3.3V) VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[3] –25 µA IIH Input High Current[3] 10 µA IIL Input Low Current, SEL133/100#[3] –5µ A IIH Input High Current, SEL133/100#[3] 5µ A Clock Outputs CPU, CPUdiv2, IOAPIC (Referenced to VDDQ2 ) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 2.2 V IOL Output Low Current V OL = 1.25V 45 65 100 mA IOH Output High Current V OH = 1.25V 45 65 100 mA 48MHz, REF (Referenced to VDDQ3 ) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 45 65 100 mA IOH Output High Current V OH = 1.5V 45 65 100 mA PCI, 3V66 (Referenced to VDDQ3 ) Test Condition Min. Typ. Max. Unit VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IOL Output Low Current V OL = 1.5V 70 100 145 mA IOH Output High Current V OH = 1.5V 65 95 135 mA Notes: 2. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors. 3. W161 logic inputs have internal pull-up devices, except SEL133/100# (pull-ups not CMOS level).
3.3V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[7] Notes: 4. X1 input threshold voltage (typical) is VDD /2. 5. The W161 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 7. Period, jitter, offset, and skew measured on rising edge at 1.5V. 8. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz. Crystal Oscillator VTH X1 Input threshold Voltage[4] 1.65 V C LOAD Load Capacitance, Imposed on External Crystal[5] 18 pF C IN,X1 X1 Input Capacitance[6] Pin X2 unconnected 28 pF Pin Capacitance/Inductance C IN Input Pin Capacitance Except X1 and X2 5 pF C OUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7n H Parameter Description Test Condition Min. Typ. Max. Unit 3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency Note 8 66.6 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω
Note: 9. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz. PCI Clock Outputs, PCI0:9 (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V [9] 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V . Maximum difference of cycle time between two adjacent cycles. 500 ps tSK Output Skew Measured on rising edge at 1.5V . 500 ps tO 3V66 to PCI Clock Skew Covers all 3V66/PCI outputs. Measured on rising edge at 1.5V . 3V66 leads PCI output. 1.5 3 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Frequency generated by crystal oscillator 14.318 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 Ω 48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 Ω
2.5V AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[10] Note: 10. Period, Jitter, offset. and skew measured on rising edge at 1.25V. CPU Clock Outputs, CPU0:2 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 133 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 7.5 7.65 10 10.2 ns tH High Time Duration of clock cycle above 2.0V 1.87 3.0 ns tL Low Time Duration of clock cycle below 0.4V 1.67 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V . Max- imum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s CPUdiv2 Clock Outputs, CPUdiv2 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 133 MHz CPU = 100 MHz t P Period Measured on rising edge at 1.25V 15 15.3 20 20.4 ns tH High Time Duration of clock cycle above 2.0V 5.25 7.5 ns tL Low Time Duration of clock cycle below 0.4V 5.05 7.3 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V . Max- imum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Zo AC Output Impedance Average value during switching transi- tion. Used for determining series termi- nation value. 20 20 Ω
Note: 11. IOAPIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz. Document #: 38-00817 IOAPIC Clock Output, IOAPIC (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min Typ Max Unit f Frequency Note 11 16.67 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 Ω
Ordering Information
W161 H 48-pin SSOP (300 mils)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 48-Pin Small Shrink Outline Package (SSOP , 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102