W152 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

  • Spread Aware™—designed to work with SSFTG reference signals  Two banks of four outputs each  Configuration options to halve, double, or quadruple the reference frequency refer to Table 1 to determine the specific option which meets your multiplication needs  Outputs may be three-stated  Available in 16-pin SOIC package  Extra strength output drive available (-11/-12 versions)  Contact factory for availability information on 16-pin TSSOP Key Specifications Cycle-to-Cycle Jitter: Frequency Range Output to Output Skew: Within Banks

Table 1. Configuration Options

  1. W152-11 has stronger output drive than the W152-1.
  2. W152-12 has stronger output drive than the W152-2.

Spread Aware is a trademark of Cypress Semiconductor Corporation.

cause problems in systems requiring synchronization. are three-stated and the PLL is turned off. this signal unless the device is programmed to bypass the PLL. the destinations will be synchronized to the REF signal input. GND 5, 12 G Ground Connections: Connect all grounds to the common system ground plane. Table 2. Input Logic

Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient T emperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W Parameter Description Test Condition Min. Typ. Max. Unit IDD Supply Current Unloaded, 100 MHz 40 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 12 mA (-11, -12) 0.4 V VOH Output High Voltage I OH = 12 mA (-11, -12) 2.4 V IIL Input Low Current V IN = 0V 50 µA IIH Input High Current V IN = VDD 50 µA Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency Note 3 15 140 MHz fOUT Output Frequency 15-pF load [8] 15 140 MHz tR Output Rise Time (-1, -2, -3, -4) 0.8V to 0.8V, 15-pF load 2 2.5 ns Output Rise Time (-11, -12) 0.8V to 0.8V, 15-pF load 1.5 ns tF Output Fall Time (-1, -2, -3, -4) 2.0V to 0.8V, 15-pF load 2 2.5 ns Output Rise Time (-11, -12) 2.0V to 0.8V, 20-pF load 1.5 ns tICLKR Input Clock Rise Time[4] 4.5 ns tICLKF Input Clock Fall Time[4] 4.5 ns tPD FBIN to REF Skew[5, 6] 350 ps tSK Output to Output Skew All outputs loaded equally [10] 215 ps tD Duty Cycle 15-pF load [7, 8] 45 50 55 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle Note 9 225 ps Notes: 3. Input frequency is limited by output frequency range and input to output frequency multiplication factor (which is determined by circuit configuration). See Table 1. 4. Longer input rise and fall time will degrade skew and jitter performance. 5. All AC specifications are measured with a 50Ω transmission line. 6. Skew is measured at V DD /2 on rising edges. 7. Duty cycle is measured at VDD /2. 8. For the higher drive -11 and -12, the load is 20 pF . 9. For frequencies above 25 MHz CY - CY = 125 ps. 10. Measured across all outputs. Maximum skew between outputs in the same bank is 100 ps.

16-Pin Small Outline Integrated Circuit (SOIC, 150 mils)

© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagrams (continued) 16-Pin Thin Shrink Small Outline Package (TSSOP, 4.4 mm)