W150 CYPRESS | Alldatasheet
Document overview
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Technical content
Features
- Maximized EMI suppression using Cypress’s Spread Spectrum Technology Single chip system frequency synthesizer for Intel® 440BX AGPset Three copies of CPU output Seven copies of PCI output One 48-MHz output for USB / One 24-MHz for SIO Two buffered reference outputs Two IOAPIC outputs 17 SDRAM outputs provide support for 4 DIMMs Supports frequencies up to 150 MHz 2C™ interface for programming Power management control inputs Key Specifications V
Table 1. Mode Input Table Table 2. Pin Selectable Frequency Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
- Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Unlike other I/O pins, input FS3 has an internal pull-down resistor.
Pin Name Pin No. Pin Type Pin Description CPU1:2 51, 49 O CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input interface, see Ta ble s 2 and 6. These outputs are affected by the CLK_STOP# input. CPU_F 52 O Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input interface, see Ta ble s 2 and 6. This output is not affected by the CLK_STOP# input. PCI1:5 11, 12, 13, 14, O PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input interface, see Ta ble s 2 and 6. These outputs are affected by the PCI_STOP# input. PCI0/FS3 9 I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is affected by the PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and PCI outputs. PCI_F/MODE 8 I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. When an input, selects function of pin 3 as described in Table 1. CLK_STOP# 47 I CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after com- pleting a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected outputs start beginning with a full clock cycle (2–3 CPU clock latency). IOAPIC_F 54 O Free-running IOAPIC Output: This output is a buffered version of the reference input which is not affected by the CPU_STOP# logic input. It’s swing is set by voltage applied to VDDQ2. IOAPIC0 55 I/O IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set by voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW. 48MHz/FS1 29 I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power up, FS1 input will be latched, setting output frequencies as described in Table 2. 24MHz/FS0 30 I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input will be latched, setting output frequencies as described in Table 2. REF1/FS2 2 I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2 input will be latched, setting output frequencies as described in Table 2. REF0 (PCI_STOP#) 3I / O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin. The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F . Its effects take place on the next PCI_F clock cycle. As an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins (14.318 MHz). SDRAMIN 17 I Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs (SDRAM0:15, SDRAM_F). SDRAM0:15 44, 43, 41, 40, 39, 38, 36, 35, 22, 21, 19, 18, 33, 32, 25, 24 O Buffered Outputs: These sixteen dedicated outputs provide copies of the signal pro- vided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when CLK_STOP# input is set LOW. SDRAM_F 46 O Free-Running Buffered Output: This output provides a single copy of the SDRAMIN input. The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input. SCLK 28 I Clock pin for I 2C circuitry. SDA TA 27 I/O Data pin for I 2C circuitry. X1 5 I Crystal Connection or External Reference Frequency Input: This pin has dual func- tions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input. X2 6 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDDQ3 1, 7, 15, 20, 31, 37, 45 P Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers, PCI output buffers, reference output buffers, and 48-MHz/24-MHz output buffers. Con- nect to 3.3V .
Data is written to the W150 in eleven bytes of eight bits each. Bytes are written in the order shown in Ta ble 4. Table 3. Serial Data Interface Control Functions Summary Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. outputs to unused PCI slots. under normal system operation. Enables or disables spread spectrum clocking. For EMI reduction. Output Three-state Puts clock output into a high-impedance state. Production PCB testing. ternal PLL is bypassed. Refer to Table 5. Table 4. Byte Writing Sequence
1 Slave Address 11010010 Commands the W150 to accept the bits in Data Bytes 0 –7 for internal
- Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver). 2 Command Code Don ’t Care Unused by the W150, therefore bit values are ignored (“don’t care”). er addressed slave receiver on the serial data bus. 3 Byte Count Don ’t Care Unused by the W150, therefore bit values are ignored (“don’t care”). er addressed slave receiver on the serial data bus.
4 Data Byte 0 Refer to Table 5 The data bits in Data Bytes 0–5 set internal W150 registers that control
control functions, refer to Ta ble 5, Data Byte Serial Configuration Map.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6 Don ’t Care Unused by the W150, therefore bit values are ignored (don’t care).
11 Data Byte 7
- Bits are written MSB (most significant bit) first, which is bit 7.
able through the serial data interface. Table 7 details the select functions for Byte 0, bits 1 and 0. Table 5. Data Bytes 0–5 Serial Configuration Map
Table 5. Data Bytes 0–5 Serial Configuration Map (continued)
- CPU and PCI frequency selections are listed in Table 2 and Table 6.
Table 6. Frequency Selections through Serial Data Interface Data Bytes Table 7. Select Function for Data Byte 0, Bits 0:1
Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TB Ambient T emperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESD PROT Input ESD Protection 2 (min) kV Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Current CPU_F , 1:2= 100 MHz Outputs Loaded[3] 320 mA IDD 2.5V Supply Current CPU_F , 1:2= 100 MHz Outputs Loaded[3] 40 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[4] –25 µA IIH Input High Current[4] 10 µA IIL Input Low Current (SEL100/66#) –5µ A IIH Input High Current (SEL100/66#) +5 µA Clock Outputs VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = 1 mA 3.1 V VOH Output High Voltage CPU_F , 1:2, IOAPIC IOH = –1 mA 2.2 V IOL Output Low Current CPU_F , 1:2 V OL = 1.25V 60 73 85 mA PCI_F, PCI1:5 V OL = 1.5V 96 110 130 mA IOAPIC0, IOAPIC_F VOL = 1.25V 72 92 110 mA REF0:1 V OL = 1.5V 61 71 80 mA 48-MHz V OL = 1.5V 60 70 80 mA 24-MHz V OL = 1.5V 60 70 80 mA SDRAM0:15, _F V OL = 1.5V 95 110 130 IOH Output High Current CPU_F , 1:2 V OH = 1.25V 43 60 80 mA PCI_F, PCI1:5 V OH = 1.5V 76 96 120 mA IOAPIC V OH = 1.25V 60 90 130 mA REF0:1 V OH = 1.5V 50 60 72 mA 48-MHz V OH = 1.5V 50 60 72 mA 24-MHz V OH = 1.5V 50 60 72 mA SDRAM0:15, _F V OH = 1.5V 75 95 120 Notes: 3. All clock outputs loaded with 6" 60Ω traces with 22-pF capacitors. 4. W150 logic inputs have internal pull-up devices (not to full CMOS level). Logic input FS3 has an internal pull-down device.
TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. Crystal Oscillator VTH X1 Input threshold Voltage[5] VDDQ3 = 3.3V 1.65 V C LOAD Load Capacitance, Imposed on External Crystal[6] 14 pF C IN,X1 X1 Input Capacitance[7] Pin X2 unconnected 28 pF Pin Capacitance/Inductance C IN Input Pin Capacitance Except X1 and X2 5 pF C OUT Output Pin Capacitance 6p F LIN Input Pin Inductance 7n H Notes: 5. X1 input threshold voltage (typical) is VDDQ3 /2. 6. The W150 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Parameter Description Test Condition Min. Typ. Max. Unit CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25 15 15.5 10 10.5 ns tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max- imum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Z o AC Output Impedance Average value during switching transi- tion. Used for determining series termi- nation value. 20 20 Ω
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12.0 ns tL Low Time Duration of clock cycle below 0.4V 12.0 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum difference of cycle time between two adja- cent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V . CPU leads PCI output. 1.5 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist pri- or to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.31818 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabili- zation. 3m s Zo AC Output Impedance Average value during switching transition. Used for de- termining series termination value. 25 Ω
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 22 pF) Parameter Description Test Condition/Comments CPU = 66.8 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.5V 15 15.5 10 10.5 ns tH High Time Duration of clock cycle above 2.4V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.0 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 45 55 % tSK Output Skew Measured on rising and falling edge at 1.5V 250 250 ps tPD Propagation Delay Measured from SDRAMIN 3.7 3.7 ns Zo AC Output Impedance Average value during switching transi- tion. Used for determining series termi- nation value. 15 15 Ω 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.8/100 MHz UnitMin. Typ. Max. f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabiliza- tion. 3m s Zo AC Output Impedance Average value during switching transition. Used for de- termining series termination value. 25 Ω
Document #: 38-00857-A 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz Parameter Description Test Condition/Comments CPU = 66.8/100 MHz UnitMin. Typ. Max. f Frequency, Actual Determined by PLL divider ratio (see m/n below) 24.004 MHz fD Deviation from 24 MHz (24.004 – 24)/24 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/34 = 24.004 MHz) 57/34 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabili- zation. 3m s Zo AC Output Impedance Average value during switching transition. Used for de- termining series termination value. 25 Ω
Ordering Information
W150 H 56-Pin SSOP (300-mil)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 56-Pin Shrink Small Outline Package (SSOP , 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102