W149 CYPRESS | Alldatasheet
Document overview
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Technical content
Features
- Maximized EMI suppression using Cypress’s Spread Spectrum Technology Single chip system frequency synthesizer for Intel® 440BX AGPset Two copies of CPU output Six copies of PCI output One 48-MHz output for USB One 24-MHz output for SIO Two buffered reference outputs One IOAPIC output Thirteen SDRAM outputs provide support for 3 DIMMs Spread Spectrum feature always enabled 2C™ interface for programming Power management control inputs Smooth CPU frequency switching from 66.8–124 MHz Key Specifications
Table 1. Mode Input Table[1]
0 PCI_STOP#
1 REF0
Table 2. Pin Selectable Frequency Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
- Mode input latched at power-up.
- Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Pin Name Pin No. Pin Type Pin Description CPU0:1 44, 43 O CPU Clock Outputs: See Ta ble s 2 and 6 for detailed frequency information. Output voltage swing is controlled by voltage applied to VDDQ2. PCI1:5 8, 10, 11, 12, O PCI Clock Outputs 1 through 5: These five PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. PCI_F/MODE 7 I/O Fixed PCI Clock Output: Frequency is set by the FS0:1 inputs or through serial input interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. Upon power-up the mode input will be latched, which will determine the func- tion of pin 2, REF0/(PCI_STOP#). See T able 1. OE 41 I Output Enable Input: When brought LOW, all outputs are placed in a high-imped- ance state. When brought HIGH, all clock outputs activate. IOAPIC 47 O IOAPIC Clock Output: Provides 14.318-MHz fixed frequency . The output voltage swing is controlled by VDDQ2. 48MHz/FS0 26 I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this output can be used as the reference for the Universal Serial Bus. Upon power-up, FS0 input will be latched, which will set clock frequencies as described in Table 2. This output does not have the Spread Spectrum feature. 24MHz/FS1 25 I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this output can be used as the clock input for a Super I/O chip. Upon power-up FS1 input will be latched, which will set clock frequencies as described in Ta ble 2. This output does not have the Spread Spectrum feature. REF1/FS2 46 I/O I/O Dual-Function REF1 and FS2 pin: Upon power-up, FS2 input will be latched which will set clock frequencies as described in Ta b l e 2. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. REF0/ (PCI_STOP#) 2I / O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function is determined by the MODE input. When set as an input, the PCI_STOP# input enables the PCI 1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F . Its effects take place on the next PCI_F clock cycle. When an output, this pin provides a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins. SDRAMIN 15 I Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:12). SDRAM0:12 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40 O Buffered Outputs: These thirteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deacti- vated when CLK_STOP# input is set LOW. SCLK 24 I Clock pin for I 2C circuitry. SDA TA 23 I/O Data pin for I 2C circuitry. X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDDQ3 1, 6, 14, 19, 27, 30, 36 P Power Connection: Power supply for core logic, PLL circuitry , SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24-MHz output. Connect to 3.3V supply . VDDQ2 42, 48 P Power Connection: Power supply for IOAPIC and CPU0:1 output buffers. Connect to 2.5V , or 3.3V . GND 3, 9, 16, 22, 33, 39, 45 G Ground Connections: Connect all ground pins to the common system ground plane.
Data is written to the W149 in eleven bytes of eight bits each. Bytes are written in the order shown in Ta b l e 4. Table 3. Serial Data Interface Control Functions Summary Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. outputs to unused PCI slots. under normal system operation. Output Three-state Puts clock output into a high-impedance state. Production PCB testing. Table 4. Byte Writing Sequence
1 Slave Address 11010010 Commands the W149 to accept the bits in Data Bytes 0 –6 for internal
- Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver). 2 Command Code Don ’t Care Unused by the W149, therefore bit values are ignored (“Don ’t Care”). er addressed slave receiver on the serial data bus. 3 Byte Count Don ’t Care Unused by the W149, therefore bit values are ignored (“Don ’t Care”). dressed slave receiver on the serial data bus.
4 Data Byte 0 Refer to Ta ble 5The data bits in Data Bytes 0–7 set internal W149 registers that control
control functions, refer to Table 5, Data Byte Serial Configuration Map.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
11 Data Byte 7
- Bits are written MSB (most significant bit) first, which is bit 7.
able through the serial data interface. Ta ble 7 details the select functions for Byte 0, bits 1 and 0. Table 5. Data Bytes 0–7 Serial Configuration Map
Table 5. Data Bytes 0–7 Serial Configuration Map (continued)
Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes[3] Table 7. Select Function for Data Byte 0, Bits 0:1
- CPU and PCI frequency selections are listed in Tabl e 2 and Table 6.
Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only . Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability . Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TB Ambient T emperature under Bias –55 to +125 °C TA Operating T emperature 0 to +70 °C ESD PROT Input ESD Protection 2 (min) kV Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Current CPU0:1 = 100 MHz Outputs Loaded[4] 260 mA IDD 2.5V Supply Current CPU0:1 = 100 MHz Outputs Loaded[4] 25 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[5] –25 µA IIH Input High Current[5] 10 µA Clock Outputs VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = 1 mA 3.1 V VOH Output High Voltage CPU0:1, IOAPIC IOH = –1 mA 2.2 V IOL Output Low Current CPU0:1 V OL = 1.25V 27 57 97 mA PCI_F , PCI1:5 VOL = 1.5V 20.5 53 139 mA IOAPIC V OL = 1.25V 40 85 140 mA REF0:1 V OL = 1.5V 25 37 76 mA 48MHz V OL = 1.5V 25 37 76 mA 24MHz V OL = 1.5V 25 37 76 mA IOH Output High Current CPU0:1 V OH = 1.25V 25 55 97 mA IOH Output High Current PCI_F , PCI1:5 VOH = 1.5V 31 55 139 mA IOAPIC V OH = 1.25V 40 87 155 mA REF0:1 V OH = 1.5V 27 44 94 mA 48MHz V OH = 1.5V 27 44 94 mA 24MHz V OH = 1.5V 25 37 76 mA Notes: 4. All clock outputs loaded with 6" 60Ω traces with 22-pF capacitors. 5. W149 logic inputs have internal pull-up devices (pull-ups not full CMOS level).
TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. Crystal Oscillator VTH X1 Input threshold Voltage[6] VDDQ3 = 3.3V 1.65 V C LOAD Load Capacitance, Imposed on External Crystal[7] 14 pF C IN,X1 X1 Input Capacitance[8] Pin X2 unconnected 28 pF Pin Capacitance/Inductance C IN Input Pin Capacitance Except X1 and X2 5 pF C OUT Output Pin Capacitance 6p F LIN Input Pin Inductance 7n H Notes: 6. X1 input threshold voltage (typical) is VDDQ3 /2. 7. The W149 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Parameter Description Test Condition Min. Typ. Max. Unit CPU Clock Outputs, CPU_F , CPU1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 15 15.5 10 10.5 ns tH High Time Duration of clock cycle above 2.4V , at min. edge rate (1.5 V/ns) 5.6 3.3 ns tL Low Time Duration of clock cycle below 0.4V , at min. edge rate (1.5 V/ns) 5.3 3.1 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.5 4 1.5 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.5 4 1.5 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V , at min. edge rate (1.5 V/ns) 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V . Max- imum difference of cycle time between two adjacent cycles. 200 200 ps tSK Output Skew Measured on rising edge at 1.5V 250 250 ps fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Z o AC Output Impedance Average value during switching transi- tion. Used for determining series termi- nation value. 20 20 Ω
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments CPU = 66.6 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.5V 30 30 ns tH High Time Duration of clock cycle above 2.4V , at min. sdge rate (1.5 V/ns) 5.6 3.3 ns tL Low Time Duration of clock cycle below 0.4V , at min. sdge rate (1.5 V/ns) 5.3 3.1 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1.5 4 1.5 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1.5 4 1.5 4 V/ns tPLH Prop Delay LH Input edge rate faster than 1 V/ns 1 5 1 5 ns tPHL Prop Delay HL Input edge rate faster than 1 V/ns 1 5 1 5 ns tD Duty Cycle Measured on rising and falling edge at 1.5V , at min. sdge rate (1.5 V/ns) 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V . Maximum difference of cycle time between two adjacent cycles. 250 250 ps tSK Output Skew Measured on rising edge at 1.5V 250 250 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Mea- sured on rising edge at 1.5V . CPU leads PCI output. 1.5 4 1.5 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 30 30 Ω
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12.0 ns tL Low Time Duration of clock cycle below 0.4V 12.0 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V . Maximum difference of cycle time between two adja- cent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V . CPU leads PCI output. 1.5 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist pri- or to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 30 Ω IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.31818 MHz t R Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency , Actual Frequency generated by crystal oscillator 14.318 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V . 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabili- zation. 3m s Zo AC Output Impedance Average value during switching transition. Used for de- termining series termination value. 40 Ω
Document #: 38-00856-A 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency , Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabili- zation. 3m s Zo AC Output Impedance Average value during switching transition. Used for de- termining series termination value. 40 Ω 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF= 66.6/100 MHz Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency , Actual Determined by PLL divider ratio (see m/n below) 24.004 MHz fD Deviation from 24 MHz (24.004 – 24)/24 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/34 = 24.004 MHz) 57/34 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabili- zation. 3m s Zo AC Output Impedance Average value during switching transition. Used for de- termining series termination value. 40 Ω
Ordering Information
W149 H 48-Pin SSOP (300-mil)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 48-Pin Shrink Small Outline Package (SSOP , 300 mils)