W147G CYPRESS | Alldatasheet
Document overview
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Technical content
Features
- Maximized EMI suppression using Cypress’s Spread Spectrum Technology Low jitter and tightly controlled clock skew Highly integrated device providing clocks required for CPU, core logic, and SDRAM Three copies of CPU clock at 66/100 MHz Nine copies of 100-MHz SDRAM clocks Eight copies of PCI clock Two copies of synchronous APIC clock Two copies of 48-MHz clock (non-spread spectrum) op- timized for USB reference input and video dot clock Two copies of 66-MHz fixed clock One copy of 14.31818-MHz reference clock Power-down control 2C interface for turning off unused clocks Key Specifications APIC, 48MHz, 3V66, PCI Outputs
Table 1. Pin Selectable Functions
01 T e s t
Pin Name Pin No. Pin Type Pin Description REF/APICDIV 1 I/O Reference Clock: 3.3V 14.318-MHz clock output. This pin doubles as the select strap for APIC clock frequency . If strapped LOW during power up, APIC clock runs at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed. X1 3 I Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection as an external reference frequency input. X2 4 I Crystal Output: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PCI0_ICH, PCI1:7 11, 12, 13, 15, 16, 18, 19. 20 O PCI Clock 0 through 7: 3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually turned off via I2C interface. 3V66_0:1 7, 8 O 66-MHz Clock Output: 3.3V fixed 66-MHz clock. USB 25 O USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock outputs. DOT 26 O Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal. SEL0:1 28, 29 I Clock Function Selection pins: LVTTL-compatible input to select device func- tions. See Table 1 for detailed descriptions. PWRDWN# 32 I Power Down Control: LVTTL-compatible asynchronous input that places the de- vice in power-down mode when held LOW. CPU2_ITP , CPU0:1 49, 52, 50 O CPU Clock Outputs: Clock outputs for the host bus interface and integrated test port. Output frequencies run at 66 MHz or 100 MHz depending on the configuration of SEL0:1. Voltage swing set by V DDQ2 . SDRAM0:7, DCLK 46, 45, 43, 42, 40, 39, 37, 36, O SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:7 can be individually turned off via I2C interface. APIC0:1 55, 54 O Sychronous APIC Clock Outputs: Clock outputs running divide synchronous with the PCI clock outputs. Output frequency is controlled by the strap option on REF . Voltage swing set by VDDQ2 . SDATA 30 I/O Data pin for I 2C circuitry. SCLK 31 I Clock pin for I 2C circuitry. VDDQ3 2, 9, 10, 21, 27, 33, 38, 44 P 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V . VDD3 22 P 3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V . VDDQ2 51, 53 P 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con- nect to 2.5V or 3.3V . GND 5, 6, 14, 17, 23, 24, 35, 41, 47, 48, 56 G Ground Connections: Connect all ground pins to the common system ground plane.
ture platform using graphics integrated core logic. strapping resistor connections. quency of the processor and configure itself accordingly.
- APIC clock frequency determined by the strap option on the REF/APICDIV input pin.
- Provided for board level “bed of nails” testing.
- “Normal” mode of operation.
- TCLK is a test clock overdriven on the XTAL_IN input during test mode.
- Required for DC output impedance verification.
- Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Figure 1. Input Logic Selection Through Resistor Load Option Table 2. CK Whitney Truth Table
all clock outputs are driven LOW.
- Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW
- PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W147G.
- The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.
- Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Table 3. W147G Maximum Allowed Current Figure 4. W147G PWRDWN# Timing Diagram [8, 9, 10, 11]
A block write begins with a slave address and a write condition. example of a possible byte count value. mand code and byte count bytes are ignored by the W147G. quence to maintain proper byte allocation.
- The acknowledgment bit is returned by the slave/receiver (W147G).
- Data Bytes 3 to 7 are reserved.
Figure 7. An Example of a Block Write[12] Table 4. Example of Possible Byte Count Value 0000 0000 Not allowed. Must have at least one byte. Table 5. Serial Data Interface Control Functions Summary Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Enables or disables spread spectrum clocking. For EMI reduction. No user application. Register bit must be written as 0.
W147G Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 2. All unused register bits (reserved and N/A) should be writ- ten to a “0” level. 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Failure to do so may result in high- er than normal operating current. 4. Only Byte 0, 1 and 2 are defined in W147G Byte 3 to Byte 7 are reserved and must be written to “zero.” Note: 14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. Byte 0: Control Register (1 = Enable, 0= Disable)[14] Bit Pin# Name Pin Description Bit 7 - Reserved (Active/Inactive) Bit 6 - Reserved (Active/Inactive) Bit 5 - Reserved (Active/Inactive) Bit 4 - Reserved (Active/Inactive) Bit 3 - Spread Spectrum (1=On/0=Off) (Active/Inactive) Bit 2 26 DOT (Active/Inactive) Bit 1 25 USB (Active/Inactive) Bit 0 49 CPU2_ITP (Active/Inactive) Byte 1: Control Register (1 = Enable, 0= Disable)[14] Bit Pin# Name Pin Description Bit 7 36 SDRAM7 (Active/Inactive) Bit 6 37 SDRAM6 (Active/Inactive) Bit 5 39 SDRAM5 (Active/Inactive) Bit 4 40 SDRAM4 (Active/Inactive) Bit 3 42 SDRAM3 (Active/Inactive) Bit 2 43 SDRAM2 (Active/Inactive) Bit 1 45 SDRAM1 (Active/Inactive) Bit 0 46 SDRAM0 (Active/Inactive) Byte 2: Control Register (1 = Enable, 0= Disable)[14] Bit Pin# Name Pin Description Bit 7 20 PCI7 (Active/Inactive) Bit 6 19 PCI6 (Active/Inactive) Bit 5 18 PCI5 (Active/Inactive) Bit 4 16 PCI4 (Active/Inactive) Bit 3 15 PCI3 (Active/Inactive) Bit 2 13 PCI2 (Active/Inactive) Bit 1 12 PCI1 (Active/Inactive) Bit 0 - Reserved (Active/Inactive)
DC parameters must be sustainable under steady state (DC) conditions. Note: 15. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Absolute Maximum DC Power Supply Parameter Description Min. Max. Unit VDD3 3.3V Core Supply Voltage –0.5 4.6 V VDDQ2 2.5V I/O Supply Voltage –0.5 3.6 V VDDQ3 3.3V Supply Voltage –0.5 4.6 V TS Storage Temperature –65 150 °C Absolute Maximum DC I/O Parameter Description Min. Max. Unit Vih3 3.3V Input High Voltage –0.5 4.6 V Vil3 3.3V Input Low Voltage –0.5 V ESD prot. Input ESD Protection 2000 V DC Operating Requirements Parameter Description Condition Min. Max. Unit VDD3 3.3V Core Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ3 3.3V I/O Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ2 2.5V I/O Supply Voltage 2.5V±5% 2.375 2.625 V VDD3 = 3.3V±5% Vih3 3.3V Input High Voltage V DD3 2.0 V DD +0.3 V Vil3 3.3V Input Low Voltage V SS –0.3 0.8 V Iil Input Leakage Current[15] 0<V in<V DDQ3 –5+ 5 µ A VDDQ2 = 2.5V±5% Voh2 2.5V Output High Voltage I oh=(–1 mA) 2.0 V Vol2 2.5V Output Low Voltage I ol=(1 mA) 0.4 V VDDQ3 = 3.3V±5% Voh3 3.3V Output High Voltage I oh=(–1 mA) 2.4 V Vol3 3.3V Output Low Voltage I ol=(1 mA) 0.4 V VDDQ3 = 3.3V±5% Vpoh3 PCI Bus Output High Voltage I oh=(–1 mA) 2.4 V Vpol3 PCI Bus Output Low Voltage I ol=(1 mA) 0.55 V C in Input Pin Capacitance 5 pF C xtal Xtal Pin Capacitance 13.5 22.5 pF C out Output Pin Capacitance 6 pF Lpin Pin Inductance 0 7 nH Ta Ambient Temperature No Airflow 0 70 °C
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[16] Notes: 18. TLOW is measured at 0.4V for all outputs. 19. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 20. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification. Parameter Description 66.6-MHz Host 100-MHz Host Unit NotesMin. Max. Min. Max. TPeriod Host/CPUCLK Period 15.0 15.5 10.0 10.5 ns 16 THIGH Host/CPUCLK High Time 5.2 N/A 3.0 N/A ns 19 TLOW Host/CPUCLK Low Time 5.0 N/A 2.8 N/A ns 20 TRISE Host/CPUCLK Rise Time 0.4 1.6 0.4 1.6 ns TFALL Host/CPUCLK Fall Time 0.4 1.6 0.4 1.6 ns TPeriod SDRAM CLK Period 10.0 10.5 10.0 10.5 ns 16 THIGH SDRAM CLK High Time 3.0 N/A 3.0 N/A ns 19 TLOW SDRAM CLK Low Time 2.8 N/A 2.8 N/A ns 20 TRISE SDRAM CLK Rise Time 0.4 1.6 0.4 1.6 ns TFALL SDRAM CLK Fall Time 0.4 1.6 0.4 1.6 ns TPeriod APIC CLK Period 60.0 64.0 60.0 64.0 ns 16 THIGH APIC CLK High Time 25.5 N/A 25.5 N/A ns 19 TLOW APIC CLK Low Time 25.3 N/A 25.3 N/A ns 20 TRISE APIC CLK Rise Time 0.4 1.6 0.4 1.6 ns TFALL APIC CLK Fall Time 0.4 1.6 0.4 1.6 ns TPeriod 3V66 CLK Period 15.0 16.0 15.0 16.0 ns 16, 18 THIGH 3V66 CLK High Time 5.25 N/A 5.25 N/A ns 19 TLOW 3V66 CLK Low Time 5.05 N/A 5.05 N/A ns 20 TRISE 3V66 CLK Rise Time 0.5 2.0 0.5 2.0 ns TFALL 3V66 CLK Fall Time 0.5 2.0 0.5 2.0 ns TPeriod PCI CLK Period 30.0 N/A 30.0 N/A ns 16, 17 THIGH PCI CLK High Time 12.0 N/A 12.0 N/A ns 19 TLOW PCI CLK Low Time 12.0 N/A 12.0 N/A ns 20 TRISE PCI CLK Rise Time 0.5 2.0 0.5 2.0 ns TFALL PCI CLK Fall Time 0.5 2.0 0.5 2.0 ns tpZL, tpZH Output Enable Delay (All outputs) 1.0 10.0 1.0 10.0 ns tpLZ, tpZH Output Disable Delay (All outputs) 1.0 10.0 1.0 10.0 ns tstable All Clock Stabilization from Power-Up 3 3 ms
Intel is a registered trademark of Intel Corporation. Document #: 38-00820 Group Skew and Jitter Limits Output Group Pin-Pin Skew Max Cycle-Cycle Jitter Duty Cycle Nom Vdd Skew, Jitter Measure Point CPU 175 ps 250 ps 45/55 2.5V 1.25V SDRAM 250 ps 250 ps 45/55 3.3V 1.5V APIC 250 ps 500 ps 45/55 2.5V 1.25V 48MHz 250 ps 500 ps 45/55 3.3V 1.5V 3V66 175 ps 500 ps 45/55 3.3V 1.5V PCI 500 ps 500 ps 45/55 3.3V 1.5V REF N/A 1000 ps 45/55 3.3V 1.5V Clock Output Wave 2.5V Clocking 3.3V Clocking Test Point Test Load TPERIOD Duty Cycle THIGH 2.0 1.25 0.4 TLOW TRISE TFALL TLOW TRISE TFALL TPERIOD Duty Cycle THIGH 2.4 1.5 0.4 Output Buffer Interface Interface Figure 8. Output Buffer
Ordering Information
W147G H 56-pin SSOP (300 mils)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 56-Pin Shrink Small Outline Package (SSOP , 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102