W137

W137 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

• Maximized EMI suppression using Cypress’s Spread Spectrum Technology  Two copies of CPU output  Six copies of PCI output (Synchronous w/CPU output)  One 48-MHz output for USB support  One selectable 24-/48-MHz output  Two Buffered copies of 14.318-MHz input reference signal  Supports 100-MHz or 66-MHz CPU operation  Power management control input pins  Available in 28-pin SSOP (209 mils)  SS function can be disabled  See W40S11-02 for 2 SDRAM DIMM support Key Specifications VDDQ2 = 2.5V±5%

1 V/ns

CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#, PWR_DWN# all have a 250-kΩ pull-up resistor. Table 1. Pin Selectable Frequency Table 2. Spread Spectrum Feature

No. Pin Type Pin Description CPU0:1 24, 23 O CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. Frequency is selected per Table 1. O PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1. PCI_F 4 O Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1. CPU_STOP# 18 I CPU_STOP# Input: When brought LOW, clock outputs CPU0:1 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency). PCI_STOP# 20 I PCI_STOP# Input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched on the rising edge of PCI_F . Its effect takes place on the next PCI_F clock cycle. REF0/SEL48# 27 I/O I/O Dual-Function REF0 and SEL48# Pin: Upon power-up, the state of SEL48# is latched. The state is set by either a 10K resistor to GND or to V DD . A 10K resistor to GND causes pin 14 to provide a 48-MHz clock. If the pin is strapped to VDD , pin 14 will provide a 24-MHz clock. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. REF1/SPREAD# 26 I/O I/O Dual-Function REF1 and SPREAD# Pin: Upon power-up, the state of SPREAD# is latched. The state is set by either a 10K resistor to GND or to VDD . A 10K resistor to GND enables Spread Spectrum function. If the pin is strapped to VDD , Spread Spectrum is disabled. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. 24/48MHz/OE 14 I/O I/O Dual-Function 24-MHz or 48-MHz Output and Output Enable Input: Upon power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to GND or to VDD . A 10K resistor to GND latches OE LOW, and all outputs are three- stated. If the pin is strapped to VDD , OE is latched HIGH and all outputs are active. After 2 ms, the pin becomes an output whose frequency is set by the state of pin 27 on power-up. 48MHz 13 O 48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage applied to VDDQ3. SEL100/66# 16 I Frequency Selection Input: Select power-up default CPU clock frequency as shown in Ta ble 1. X1 2 I Crystal Connection or External Reference Frequency Input: This pin can either be used as a connection to a crystal or to a reference signal. X2 3 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PWR_DWN# 17 I Power Down Control: When this input is LOW, device goes into a low-power standby condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock cycle latency). When brought HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). VDDQ3 8, 12, 19, 28 P Power Connection: Connected to 3.3V . VDDQ2 25 P Power Connection: Power supply for CPU0:1 output buffers. Connected to 2.5V. GND 1, 7, 15, 21, G Ground Connection: Connect all ground pins to the common system ground plane.

Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient T emperature under Bias –55 to +125 °C ESD PROT Input ESD Protection 2 (min.) kV TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; CPU0:1 = 66.6/100 MHz Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD3PD 3.3V Supply Current in Power-down mode PWR_DWN# = 0 1 5 mA IDD3 3.3V Supply Current Outputs Loaded [1] 80 100 mA IDD2 2.5V Supply Current Outputs Loaded [1] 30 45 mA IDD2PD 2.5V Supply Current in Power-down mode PWR_DWN# = 0 0.2 µA 1 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[2] –25 µA IIH Input High Current[2] 10 µA IIL Input Low Current (SEL100/66#) –5µ A IIH Input High Current (SEL100/66#) +5 µA Clock Outputs VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage PCI_F , PCI1:5, REF0:1 IOH = –1 mA 3.1 V VOH Output High Voltage CPU0:1 I OH = –1 mA 2.2 V IOL Output Low Current: CPU0:1 V OL = 1.25V 80 120 180 mA PCI_F , PCI1:5 V OL = 1.5V 70 110 140 mA REF0:1 V OL = 1.5V 50 70 90 mA IOH Output High Current CPU0:1 V OH = 1.25V 80 120 180 mA PCI_F , PCI1:5 V OH = 1.5V 70 110 140 mA REF0:1 V OH = 1.5V 50 70 90 mA Crystal Oscillator VTH X1 Input Threshold Voltage[3] VDDQ3 = 3.3V 1.65 V C LOAD Load Capacitance, As Seen by External Crystal[4] 14 pF C IN,X1 X1 Input Capacitance[5] Pin X2 unconnected 28 pF Notes: 1. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors. 2. CPU_STOP#, PCI_STOP#, PWR_DWN#, SPREAD#, and SEL48# logic inputs have internal pull-up resistors (not CMOS level). 3. X1 input threshold voltage (typical) is VDD /2. 4. The W137 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. Pin Capacitance/Inductance C IN Input Pin Capacitance Except X1 and X2 5 pF C OUT Output Pin Capacitance 6p F LIN Input Pin Inductance 7n H CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 15 15.5 10 10.5 ns tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max- imum difference of cycle time between two adjacent cycles. 200 200 ps t SK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Zo AC Output Impedance Average value during switching transi- tion. Used for determining series termi- nation value. 13.5 13.5 Ω TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; CPU0:1 = 66.6/100 MHz Parameter Description Test Condition Min. Typ. Max. Unit

PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12.0 ns tL Low Time Duration of clock cycle below 0.4V 12.0 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V . Maximum differ- ence of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Offset Covers all CPU/PCI outputs. Measured on rising edge at 1.5V . CPU leads PCI output. 1.5 4.0 ns fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 20 Ω REF0:1 Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency, Actual Determined by crystal oscillator frequency 14.318 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 Ω

Intel is a registered trademark of Intel Corporation. Document #: 38-00821 48-MHz and 24-MHz Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency, Actual Determined by PLL divider ratio (see n/m below) 48.008 24.004 MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17, 57/34 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 25 Ω

Ordering Information

W137 H 28-pin SSOP (209 mils) X 28-pin TSSOP (173 mils)

28-Pin Thin Small Shrink Outline Package (TSSOP , 173 mils)

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagrams (continued) 28-Pin Small Shrink Outline Package (SSOP , 209 mils)