W134S CYPRESS | Alldatasheet
Document overview
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Technical content
Features
- Differential clock source for Direct Rambus™ memory subsystem for up to 800-MHz data transfer rate
- Provide synchronization flexibility: the Rambus® Channel can optionally be synchronous to an external system or processor clock
- Power-managed output allows Rambus Channel clock to be turned off to minimize power consumption for mobile applications
- Works with Cypress CY2210, W133, W158, W159, W161, and W167 to support Intel® architecture platforms
- Low-power CMOS design packaged in a 24- pin QSOP (150-mil SSOP) package
Description
The Cypress W134M/W134S provides the differential clock signals for a Direct Rambus me mory subsystem. It includes signals to synchronize the Direct Rambus Channel clock to an external system clock but can also be used in systems that do not require synchronization of the Rambus clock. Block Diagram Pin Configuration PLL Phase PCLKM MULT0:1 REFCLK SYNCLKN Output Logic Logic Test Alignment STOPB S0:1 CLK CLKB VDD GND CLK NC CLKB GND VDD MULT0 MULT1 GND VDDIR REFCLK VDD GND GND PCLKM SYNCLKN GND VDD VDDIPD STOPB PWRDNB
Logic is not used, this pin would be connected to Ground. Logic is not used, this pin would be connected to Ground. ential Rambus Channel clocks and places the W134M/W134S in power-down mode. determine the multiply ratio for the PLL for the input REFCLK. CLK, CLKB 20, 18 O Complementary Output Clock. Differential Rambus Channel clock outputs. S0, S1 24, 23 I Mode Control Input. These inputs control the operating mode of the W134M/W134S. VDDIR 1 RefV Reference for REFCLK. Voltage reference for input reference clock. VDDIPD 10 RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB. G Ground Connection. Connect all ground pins to the common system ground plane.
4 DLL
Figure 1. DDLL System Architecture
Synclk at the RMC/RAC boundary. by a fixed divide-by-4 that generates Synclk. frequencies of greatest interest, organized by Gear Ratio. Figure 2. Gear Ratio Timing Diagram Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio
67 MHz 267 MHz
100 MHz 300 MHz 400 MHz
133 MHz 267 MHz 356 MHz 400 MHz
150 MHz 400 MHz
200 MHz 400 MHz
including the DRCG output enable and bypass modes. time given in the State Transition Section. when the rising edges are aligned. are not used, those inputs must be grounded. testing and for board-level testing. Figure 3. DDLL Including Details of DRCG Table 2. PLL Divider Selection Table 3. Clock Stop Mode Selection
high-impedance state during the Clk Stop mode. ps of the phase before CLK/CLKB was disabled. F Normal Clk Stop t CLKOFF 5 ns Time from StopB to Clk/ClkB output disabled. output has resettled (excluding tDISTLOCK). output has resettled (excluding tDISTLOCK). B,D Normal or Clk Stop Power-down t POWERDN 1 ms Time from PwrDnB to the device in Power-down. Table 8. State Transition Latency Specifications (continued) Table 9. Distributed Loop Lock Time Specification PclkM falls within the tERR,PD spec in Table .
Document #: 38-07426 Rev. *B Page 8 of 12 Notes: 1. Represents stress ratings only, and functional operation at the maximums is not guaranteed. 2. Gives the nominal values of the external components and their maximum acceptable tolerance, assuming Z CH = 28Ω. 3. Do not populate C F. Leave pads for future use. 4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. Refclk jitter measured at V DDIR (nom)/2. 6. If input modulation is used: input modulation is allowed but not required. 7. Capacitance measured at Freq=1 MHz, DC bias = 0.9V and V AC < 100 mV. 8. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%. Absolute Maximum Conditions[1] Parameter Description Min. Max. Unit VDD, ABS Max. voltage on VDD with respect to ground –0.5 4.0 V VI, ABS Max. voltage on any pin with respect ground –0.5 V DD+0.5 V External Component Values[2] Parameter Description Min. Max. Unit RS Serial Resistor 39 ±5% Ω RP Parallel Resistor 51 ±5% Ω CF Edge Rate Filter Capacitor 4 – 15 [3] ±10% pF CMID AC Ground Capacitor 470 pF 0.1 µF± 2 0 % Operating Conditions[4] Parameter Description Min. Max. Unit VDD Supply Voltage 3.135 3.465 V TA Ambient Operating Temperature 0 70 °C tCYCLE,IN Refclk Input Cycle Time 10 40 ns tJ,IN Input Cycle-to-Cycle Jitter[5] –2 5 0 p s DCIN Input Duty Cycle over 10,000 Cycles 40 60 %t CYCLE FMIN Input Frequency of Modulation 30 33 kHz PMIN [6] Modulation Index for Triangular Modulation – 0.6 % Modulation Index for Non-Triangular Modulation – 0.5 [8] % tCYCLE,PD Phase Detector Input Cycle Time at PclkM & SynclkN 30 100 ns tERR,INIT Initial Phase error at Phase Detector Inputs –0.5 0.5 t CYCLE,PD DCIN,PD Phase Detector Input Duty Cycle over 10,000 Cycles 25 75 t CYCLE,PD tI,SR Input Slew Rate (measured at 20%-80% of input voltage) for PclkM, SynclkN, and Refclk
14 V / n s
CIN,PD Input Capacitance at PclkM, SynclkN, and Refclk[7] –7 p F DCIN,PD Input Capacitance matching at PclkM and SynclkN[7] –0 . 5 p F CIN,CMOS Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and Refclk)[7] –1 0 p F VIL Input (CMOS) Signal Low Voltage – 0.3 VDD VIH Input (CMOS) Signal High Voltage 0.7 – VDD VIL,R Refclk input Low Voltage – 0.3 V DDIR VIH,R Refclk input High Voltage 0.7 – V DDIR VIL,PD Input Signal Low Voltage for PD Inputs and StopB – 0.3 V DDIPD VIH,PD Input Signal High Voltage for PD Inputs and StopB 0.7 – V DDIPD VDDIR Input Supply Reference for Refclk 1.235 3.465 V VDDIPD Input Supply Reference for PD Inputs 1.235 2.625 V
Document #: 38-07426 Rev. *B Page 9 of 12 Notes: 9. Output Jitter spec measured at t CYCLE = 2.5 ns. 10. Output Jitter Spec measured at tCYCLE = 3.75 ns. 11. VCOS = VOH–VOL. 12. rOUT = DVO/ D IO. This is defined at the output pins. Device Characteristics Parameter Description Min. Max. Unit tCYCLE Clock Cycle Time 2.5 3.75 ns tJ Cycle-to-Cycle Jitter at Clk/ClkB[9] –6 0 p s Total Jitter over 2, 3, or 4 Clock Cycles[9] –1 0 0 p s 266-MHz Cycle-to-Cycle Jitter[10] –1 0 0 p s 266-MHz Total Jitter over 2, 3, or 4 Clock Cycles[10] –1 6 0 p s tSTEP Phase Aligner Phase Step Size (at Clk/ClkB) 1 – ps tERR,PD Phase Detector Phase Error for Distributed Loop Measured at PclkM-SynclkN (rising edges) (does not include clock jitter) –100 100 ps tERR,SSC PLL Output Phase Error when Tracking SSC –100 100 ps VX,STOP Output Voltage during Clk Stop (StopB=0) 1.1 2.0 V VX Differential Output Crossing-Point Voltage 1.3 1.8 V VCOS Output Voltage Swing (p-p single-ended)[11] 0.4 0.6 V VOH Output High Voltage – 2.0 V VOL Output Low voltage 1.0 – V rOUT Output Dynamic Resistance (at pins)[12] 12 50 Ω IOZ Output Current during Hi-Z (S0 = 0, S1 = 1) – 50 µA IOZ,STOP Output Current during Clk Stop (StopB = 0) – 500 µA DC Output Duty Cycle over 10,000 Cycles 40 60 %t CYCLE tDC,ERR Output Cycle-to-Cycle Duty Cycle Error – 50 ps tR,tF Output Rise and Fall Times (measured at 20%–80% of output voltage) 250 500 ps tCR,CF Difference between Output Rise and Fall Times on the Same Pin of a Single Device (20%–80%) –1 0 0 p s
Document #: 38-07426 Rev. *B Page 10 of 12 Layout Example G VDDIR G VDDIPD 22 G3 G G Internal Power Supply Plane 46 G G FB +3.3V Supply 10 µF0.005 µF G G G GG GG GG GG GG G = VIA to GND plane layer FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) All Bypass cap = 0.1 Ceramic XR7
Ordering Information
Ordering Code Package Type W134M/W134SH 24-pin QSOP (150 mils, SSOP) W134M/W134SHT 24-pin QSOP (150 mils, SSOP) – Tape and Reel W134M/W134SSQC 24-pin QSOP (150 mils, SSOP) – (Lead-free) W134M/W134SSQCT 24-pin QSOP (150 mils, SSOP) – Tape and Reel – (Lead-free) W134SH 24-pin QSOP (150 mils, SSOP) W134SHT 24-pin QSOP (150 mils, SSOP) – Tape and Reel
Document #: 38-07426 Rev. *B Page 11 of 12 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc. Intel is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. 24-Lead Quarter Size Outline Q13 51-85055-*B
Document #: 38-07426 Rev. *B Page 12 of 12 Document History Page Document Title: W134M/W134S Direct Rambus™ Clock Generator Document Number: 38-07426 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 115531 05/10/02 DSG Change from Spec number: 38-00822 to 38-07246 *A 122927 12/14/02 RBI Add power-up requ irements to operating information *B 131671 12/15/03 RGL Added Lead-free to the W134 M device in the ordering information table