W132

W132 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

• Spread Aware™—designed to work with SSFTG refer- ence signals  Well suited to both 100- and 133-MHz designs  Ten (-09B) or Eleven (-10B) LVCMOS/LVTTL outputs  Single output enable pin for -10 version, dual pins on -09 devices allow shutting down a portion of the out- puts.  3.3V power supply  On board 25Ω damping resistors  Available in 24-pin TSSOP package Key Specifications Spread Aware is a trademark of Cypress Semiconductor Corporation. Block Diagram Pin Configurations PLL OE0:4 FBOUT OE OE5:8 configuration of these blocks dependent upon specific option being used FBIN CLK CLK AVDD VDD GND GND VDD FBIN AGND VDD GND GND VDD OE FBOUT W132-10B CLK AVDD VDD GND GND VDD OE5:8 FBIN AGND VDD GND GND VDD OE0:4 FBOUT W132-09B

Document #: 38-07216 Rev. *A Page 2 of 6 Overview The W132 is a PLL-based clock driver designed for use in dual inline memory modules. The clock driver has output frequen- cies of up to 133 MHz and output to output skews of less than 250 ps. The W132 provides minimum cycle-to-cycle and long term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications. The current generation of 256 and 512 megabyte memory modules needs to support 100-MHz clocking speeds. Espe- cially for cards configured in 16x4 or 8x8 format, the clock signal provided from the motherboard is generally not strong enough to meet all the requirements of the memory and logic on the DIMM. The W132 takes in the signal from the mother- board and buffers out clock signals with enough drive to sup- port all the DIMM board clocking needs. The W132 is also designed to meet the needs of new PC133 SDRAM designs, operating to 133 MHz. The W132 was specifically designed to accept SSFTG signals currently being used in motherboard designs to reduce EMI. Zero delay buffers which are not designed to pass this feature through may cause skewing failures. Output enable pins allow for shutdown of output when they are not being used. This reduces EMI and power consumption. Pin Definitions Pin Name Pin No. (-09B) Pin No. (-10B) Pin Type Pin Description CLK 24 24 I Reference Input: Output signals Q0:9 will be synchronized to this signal. FBIN 13 13 I Feedback Input: This input must be fed by one of the outputs (typically FBOUT) to ensure proper functionality. If the trace between FBIN and FBOUT is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the CLK signal input. Q0:8 3, 4, 5, 8, 9, 16, 17, 20, 21 3, 4, 5, 8, 9, 15, 16, 17, 20 O Integrated Series Resistor Outputs: The frequency and phase of the signals provided by these pins will be equal to the reference signal if properly laid out. Each output has a 25Ω series damping resistor integrated. Q9 n/a 21 O Integrated Series Resistor Output: The frequency and phase of the signal provided by this pin will be equal to the reference signal if properly laid out. This output has a 25Ω series damping resistor integrated. FBOUT 12 12 O Feedback Output: This output has a 25Ω series resistor integrated on chip. Typically it is connected directly to the FBIN input with a trace equal in length to the traces between outputs Q0:9 and the destination points of these output signals. AVDD 23 23 P Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. AGND 1 1 G Analog Ground Connection: Connect to common system ground plane. VDD 2, 10, 15, 2, 10, 14, P Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. GND 6, 7, 18, 6, 7, 18, G Ground Connections: Connect to common system ground plane. OE n/a 11 I Output Enable Input: Tie to V DD (HIGH, 1) for normal operation. when brought to GND (LOW, 0) all outputs are disabled to a LOW state. OE0:4 11 n/a I Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. when brought to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state. OE5:8 14 n/a I Output Enable Input: Tie to VDD (HIGH, 1) for normal operation. when brought to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.

Document #: 38-07216 Rev. *A Page 4 of 6 Absolute Maximum Ratings[1] Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit VDD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W Parameter Description Test Condition Min Typ Max Unit IDD Supply Current Unloaded, 100 MHz 200 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage 2.0 V VOL Output Low Voltage I OL = 12 mA 0.8 V VOH Output High Voltage I OH = –12 mA 2.1 V IIL Input Low Current V IN = 0V 50 µA IIH Input High Current V IN = VDD 50 µA Parameter Description Test Condition Min Typ Max Unit fOUT Output Frequency 30-pF load [5] 25 140 MHz tR Output Rise Time 0.8V to 2.0V, 30-pF load 2.1 ns tF Output Fall Time 2.0V to 0.8V, 30-pF load 2.5 ns tICLKR Input Clock Rise Time[2] 4.5 ns tICLKF Input Clock Fall Time[2] 4.5 ns tPEJ CLK to FBIN Skew Variation[3, 4] Measured at VDD /2 –350 0 350 ps tSK Output to Output Skew All outputs loaded equally –100 0 100 ps tD Duty Cycle 30-pF load 43 50 58 % tLOCK PLL Lock Time Power supply stable 1.0 ms tJC Jitter, Cycle-to-Cycle 150 ps Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Longer input rise and fall time will degrade skew and jitter performance. 3. Skew is measured at VDD /2 on rising edges. 4. Duty cycle is measured at VDD /2. 5. Production tests are run at 133 MHz.

Ordering Information

Ordering Code Option Package Type W132 -09B, -10B X = 24-pin TSSOP

Document #: 38-07216 Rev. *A Page 5 of 6 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 24-Pin Thin Shrink Small Outline Package (TSSOP)

Document #: 38-07216 Rev. *A Page 6 of 6 Document Title: W132 Spread Aware™ , Ten/Eleven Output Zero Delay Buffer Document Number: 38-07216 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110481 12/15/01 SZV Change from Spec number: 38-00792 to 38-07216 *A 122835 12/22/02 RBI Add Power up Requirements to Maximum Ratings Information