W130

W130 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

• Maximized EMI suppression using Cypress’s Spread Spectrum technology  Six copies of CPU Clock  Eight copies of PCI Clock (synchronous w/CPU clock)  Two copies of 14.318-MHz IOAPIC Clock  Two copies of 48-MHz USB Clock  Three buffered copies of 14.318-MHz reference input  Input is a 14.318-MHz XTAL or reference signal  Selectable 100-MHz or 66-MHz CPU Clocks  Power management control input pins  Test mode and output three-state capability Key Specifications VDDQ2 = 2.5V±5% Logic inputs have 250-kΩ pull-up resistors except SEL100/66#.

Table 1. Pin Selectable Frequency

No. Pin Type Pin Description CPU0:5 42, 41, 40, 39, 36, 35 O CPU Clock Outputs 0 through 5: These six CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI1:7 8, 10, 11, 13, 14, 16, 17 O PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. PCI_F 7 O Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. CPU_STOP# 30 I CPU_STOP# Input: When brought LOW, clock outputs CPU0:5 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:5 start beginning with a full clock cycle (2–3 CPU clock latency). PCI_STOP# 31 I PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F . Its effects take place on the next PCI_F clock cycle. SPREAD# 28 I SPREAD# Input: When brought LOW this pin activates Spread Spectrum clocking. APIC0:1 45, 44 O I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output volt- age swing is controlled by VDDQ2. 48MHz 22, 23 O 48-MHz Outputs: Fixed clock outputs at 48 MHz. Output voltage swing is controlled by voltage applied to VDDQ3. REF0:2 1, 2, 47 O Fixed 14.318-MHz Outputs 0 through 2: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. SEL100/66# SEL1, SEL0 25, 26, 27 I Frequency Selection Input: Selects power-up default CPU clock frequency as shown in Ta ble 1 on page 1. X1 4 I Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or reference signal. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PWR_DWN# 29 I Power Down Control: When this input is LOW, device goes into a low-power con- dition. All outputs are held LOW while in power-down. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2–3 CPU clock cycle latency). When brought HIGH, CPU, SDRAM and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). VDDQ3 9, 15, 19, 21, 33, 48 P Power Connection: Power supply for core logic, PLL circuitry, PCI output buffers, reference output buffers, and 48-MHz output buffers. Connected to 3.3V supply. VDDQ2 37,43,46 P Power Connection: Power supply for APIC0:1and CPU0:5 output buffers. Con- nected to 2.5V supply. GND 3, 6, 12, 18, 20, 24, 32, 34, 38 G Ground Connection: Connect all ground pins to the common system ground plane.

Stresses greater than those listed in this table may cause per- manent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specifi- cation is not implied. Maximum conditions for extended peri- ods may affect reliability. Parameter Description Rating Unit V DD , VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage T emperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient T emperature under Bias –55 to +125 °C ESD PROT Input ESD Protection 2 (min.) kV Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDDQ3 3.3V Supply Current CPU0:5 = 100 MHz Outputs Loaded[1] 95 mA IDDQ2 2.5V Supply Current CPU0:5 = 100 MHz Outputs Loaded[1] 75 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 V DD + 0.3 V IIL Input Low Current[2] –25 µA IIH Input High Current[2] 10 µA IIL Input Low Current (SEL100/66#) –5µ A IIH Input High Current (SEL100/66#) 5 µA Clock Outputs VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V VOH Output High Voltage CPU0:5, APIC0:1 I OH = –1 mA 2.2 V IOL Output Low Current CPU0:5 V OL = 1.25V 27 57 97 mA PCI_F , PCI1:7 V OL = 1.5V 20.5 53 139 mA APIC0:1 V OL = 1.25V 40 85 140 mA REF0:2 V OL = 1.5V 25 37 76 mA 48MHz V OL = 1.5V 25 37 76 mA IOH Output High Current CPU0:5 V OL = 1.25V 25 55 97 mA PCI_F , PCI1:7 V OL = 1.5V 31 55 189 mA IOAPIC V OL = 1.25V 40 87 155 mA REF0:2 V OL = 1.5V 27 44 94 mA 48MHz V OL = 1.5V 27 44 94 mA Notes: 1. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors. 2. W130 logic inputs have internal pull-up devices, except SEL100/66# (pull-ups not full CMOS level).

TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. Crystal Oscillator VTH X1 Input Threshold Voltage[3] VDDQ3 = 3.3V 1.65 V C LOAD Load Capacitance, as seen by External Crystal[4] 14 pF C IN,X1 X1 Input Capacitance[5] Pin X2 unconnected 28 pF Pin Capacitance/Inductance C IN Input Pin Capacitance Except X1 and X2 5 pF C OUT Output Pin Capacitance 6p F LIN Input Pin Inductance 7n H Notes: 3. X1 input threshold voltage (typical) is VDD /2. 4. The W130 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). Parameter Description Test Condition Min. Typ. Max. Unit CPU Clock Outputs, CPU0:5 (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6 MHz CPU = 100 MHz tP Period Measured on rising edge at 1.25V 15 15.5 10 10.5 ns tH High Time Duration of clock cycle above 2.0V 5.2 3.0 ns tL Low Time Duration of clock cycle below 0.4V 5.0 2.8 ns tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V . Max- imum difference of cycle time between two adjacent cycles. 200 200 ps tSK Output Skew Measured on rising edge at 1.25V 175 175 ps fST Frequency Stabiliza- tion from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 33 m s Z o AC Output Impedance Average value during switching transi- tion. Used for determining series termi- nation value. 15 15 Ω

PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V . Maximum difference of cycle time between two adjacent cycles. 250 ps tSK Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V . CPU leads PCI output. 1.5 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 30 Ω APIC0:1 Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.31818 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns tF Output Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns tD Duty Cycle Measured on rising and falling edge at 1.25V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 1.5 ms Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 15 Ω REF0:2 Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency, Actual Frequency generated by crystal oscillator 14.318 MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3m s Z o AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Ω

Document #: 38-00851 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments CPU = 66.6/100 MHz UnitMin. Typ. Max. f Frequency, Actual Determined by PLL divider ratio (see m/n below) 48.008 MHz fD Deviation from 48 MHz (48.008 – 48)/48 +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17 tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. 3m s Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Ω

Ordering Information

W130 H 48-pin SSOP (300 mils)

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagram 48-Pin Small Shrink Outline Package (SSOP , 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102