RTQ2134-QA RICHTEK | Alldatasheet
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Technical content
Features
⚫ FMEA Compliant PinOut ⚫ AEC-Q100 Grade1 Qualified ⚫ 2 + 2 / 2 + 1 + 1 Phase Output ⚫ I2C Programmable Output Voltage : 0.3V to 1.85V ⚫ Maximum Output Current : Total 20A, 5.5A per Phase ⚫ Output Remote Sense ⚫ Fast Transient Response ⚫ Input Supply Voltage Range : 3V to 6V ⚫ Selectable Automa tic Phase Shielding and Power Saving Mode Enables Higher Light Load Efficiency ⚫ Dynamic Voltage Scaling (DVS) with Programmable Slew Rate for Each Output ⚫ Programmable Soft-Start Function ⚫ Interrupt Function and Fault Detection ⚫ Watchdog Function ⚫ Input Under-Voltage Lockout (UVLO) ⚫ Cycle by Cycle Current Limit ⚫ Output Under-Voltage Protection ⚫ Over-Temperature Protection ⚫ WET-WQFN-30L 4.5x5 (FC) Simplified Application Circuit CIN VIN RTQ2134 EN RTN1 AVIN LX1 VOUT1 PVIN1 PVIN2 PVIN3 PVIN4 LX2 LX4 RTN2 VOUT2 VIO AVIN_FILT SCL SDA VOUT1 COUT1 LX3 RTN3 VOUT3 I2C Signal PGND AGND L2 VOUT2 L3 VOUT3 VSELA WDOG_RST Signal Input INTSignal Output COUT2 COUT3
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022
Ordering Information
Address Default VOUT and Delay Time Lead Plating System Package Type Grade Program to 2 + 1 + 1 phase operation RTQ2134GQWTF-21-QA-00 0x18 (1) VOUTx = 1V (2) No Enable/Disable delay time G : Green (Halogen Free and Pb Free) QWTF : WET-WQFN-30L 4.5x5 (FC) (W-Type) QA : AEC-Q100 Qualified and Screened by High Temperature RTQ2134GQWTF-21-QA-01 0x18 (1) VOUTx = 1V (2) Enable delay time : VOUT1/2/3 = 0/4/4ms (3) Disable delay time : VOUT1/2/3 = 4/0/0ms RTQ2134GQWTF-21-QA-02 0x19 (1) VOUTx = 1V (2) No Enable/Disable delay time RTQ2134GQWTF-21-QA-03 0x18 (2) Enable delay time : VOUT1/2/3 = 3/2/8ms (3) Disable delay time : VOUT1/2/3 = 4/8/0ms Program to 2 + 2 phase operation RTQ2134GQWTF-22-QA-00 0x18 (1) VOUTx = 1V (2) No Enable/Disable delay time G : Green (Halogen Free and Pb Free) QWTF : WET-WQFN-30L 4.5x5 (FC) (W-Type) QA : AEC-Q100 Qualified and Screened by High Temperature RTQ2134GQWTF-22-QA-01 0x18 (1) VOUTx = 1V (2) Enable delay time : VOUT1/2 = 4/0ms (3) Disable delay time : VOUT1/2 = 0/4ms RTQ2134GQWTF-22-QA-02 0x18 (1) VOUTx = 1V (2) Enable delay time : VOUT1/2 = 3/0ms (3) Disable delay time : VOUT1/2 = 0/3ms RTQ2134GQWTF-22-QA-03 0x18 (1) VOUT1/2 = 1.15V/1.06V (2) No Enable/Disable delay time RTQ2134GQWTF-22-QA-N0 0x18 (1) VOUT1 = 1V, VOUT2 = Disable (2) No Enable/Disable delay time RTQ2134GQWTF-22-QA-N1 0x19 (1) VOUTx = 1V (2) No Enable/Disable delay time Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Pin Configuration (TOP VIEW) PVIN4 PGND LX4 NC PVIN2 PGND LX2 NC AVIN_FILT RTN1 RTN3 RTN2 VOUT2 EN VIO LX1 LX3 VSELA AVIN VOUT3 INT NC NC AGND SDA WDOG_RST SCL PVIN1 PVIN3 29 28 27 2630 25 24 23 9 10 11 128 13 14 15 PGND VOUT1 WET-WQFN-30L 4.5x5 (FC) Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. Functional Pin Description Pin No. Pin Name Pin Function 1 PVIN4 Power input for power stage 4. It is recommended to use a 10 -F, X7R capacitor. 2, 6, 17, 21 NC No internal connection. 3 LX4 Switching node for power stage 4. 4, 19 PGND Power ground for power stage. 5 LX1 Switching node for power stage 1. 7 PVIN1 Power input for power stage 1. It is recommended to use a 10 -F, X7R capacitor. 8 VSELA VSEL input pin for all channels. Using corresponding register to define action. "Do Not" leave this pin floating. 9 AVIN_FILT Filtered analog supply voltage . It is recommended to use a 1 -F, X7R capacitor. 10 RTN1 Remote ground sense for Buck1. 11 VOUT1 Output voltage sense for Buck1. 12 RTN3 Remote ground sense for Buck3. 13 VOUT3 Output voltage sense for Buck3. 14 AGND Analog GND.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Pin No. Pin Name Pin Function
15 WDOG_RST
Control input for output voltage reset. Reset each Buck output voltage, DVSx, and ENDVSx registers to factory default setting value when this pin is pulled low. Connect this pin to be higher than 70% of VIO pin voltage if this pin is not used. "Do Not" leave this pin floating. The minimum watchdog debounce time is 100s. Note that the factory default setting value in watchdog register (0x25) is 0x00h (Disabled). 16 PVIN3 Power input for power stage 3. It is recommended to use a 10 -F, X7R capacitor. 18 LX3 Switching node for power stage 3. 20 LX2 Switching node for power stage 2. 22 PVIN2 Power input for power stage 2. It is recommended to use a 10 -F, X7R capacitor.
23 SCL
Clock input for I2C interface. The pull-up voltage supply must be the same as VIO voltage for correct operation. Connect this pin to AGND if I2C interface is not used. "Do Not" leave this pin floating.
24 SDA
Data line for I 2C interface. The pul l-up voltage supply must be the same as VIO voltage for correct operation. Connect this pin to AGND if I2C interface is not used. "Do Not" leave this pin floating. 25 INT Interrupt indicator. When INT function is used, set 0x33[6] = 1, 0x34[6] = 1 and 0x35[6] = 1. 26 VIO I/O supply voltage for digital communications. Connect this pin to 1.8V for normal operation. "Do Not" leave this pin floating. 27 EN Master chip enable. A logic-high enables the converter; a logic -low forces the device into shutdown mode. "Do Not" leave this pin floating. 28 VOUT2 Output voltage sense for Buck2. 29 RTN2 Remote ground sense for Buck2. 30 AVIN Analog input voltage. 31(Exposed PAD) PGND Exposed pad. The exposed pad is connected to PGND and must be soldered to a large PCB copper area for maximum power dissipation.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Functional Block Diagram DACDigital Logic I2C Buffer Interrupts Interface Enable & VSELA Logic Oscillator UVLO Protection Thermal Protection Voltage/Current Reference Core Control AVINAVIN_FILTVIO LX1 LX2 LX3 LX4 PGNDAGND VOUTxRTNx Watchdog LogicWDOG_RST INT Regulators EN VSELA SDA SCL Buck 1 Voltage/Current Protection Current Sensing Buck 2 Voltage/Current Protection Current Sensing Buck 3 Voltage/Current Protection Current Sensing Buck 4 Voltage/Current Protection Current Sensing PVINx
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com MODE Selection Whether it is DVS0 or DVS1, there are two modes of operation: forced continuous conduction mode (FCCM) and automatic power saving mode ( Auto mode). It is set in the following registers: 0x49[5], 0x4B[5], 0x63[5], 0x65[5], 0x7D[5] and 0x7F[5]. For example, t o set DVS0 of Buck1 to FCCM, just write "1" at 0x49[5]. Auto Mode with Automatic Phase Adding/Shedding Auto mode enables high efficiency at light load. At low load current, the inductor current can drop to zero and become negative. This is detected by inte rnal zero current-detect circuitry utilizing the LSFET R DS(ON) to sense the inductor current. The LSFET is turned off when the inductor current drops to zero, resulting in discontinuous operation (DCM). Both HSFET and LSFET remain off with the output capac itor supplying the load current until the feedback voltage falls below the feedback reference voltage. DCM operation maintains high efficiency at light load, while setting MODE to Forced PWM (FCCM) operation helps meet tight voltage regulation accuracy req uirements. For multiphase outputs, the RTQ2134 automatically increases the number of operating phases as the load continues to increase above 3A (typ). The two phases are interleaved with 180 degrees apart. Interleaving reduces ripple current at the input and output. Therefore, the input and output capacitors are also reduced. Conversely, when the load current per phase drops below 2.6A (typ), the RTQ2134 automatically sheds the number of phases. FCCM Mode Setting MODE to Forced PWM (FCCM) operation helps meet stringent voltage regulation accuracy requirements. Users must enable all the set outputs before setting into the FCCM. UVLO, Enable Control and Soft-Start The RTQ2134 implements under-voltage lo ckout protection (UVLO) to prevent operation without ful ly turn on the internal HSFET and LSFET . The UVLO monitors the voltage of AVIN. When the AVIN voltage is lower than UVLO threshold , IC stops switching and resets all digital functions. The RTQ2134 provides an EN pin, as an external chip enable control, to enable or disable the device. If VEN is held below a logic -low threshold voltage (V ENL) of the enable input (EN), the converter will enter into shutdown mode and reset all digital function (I 2C); that is, the converter is disabled even if the VIN voltage i s above VIN under -voltage lockout threshold (V UVLO). During shutdown mode, the supply current can be reduced to I SHDN (20A or below). If the EN voltage rises above the logic-high threshold voltage (VENH), the device starts switching. When appropriate volt ages are present on the VIN, AVIN, VIO and EN pins, the RTQ2134 will begin digital function, switching and initiate a soft-start ramp of the output voltage. After the device is turned on and VIO is ready, all digital functions including I2C communication start to work in a boot time with 230 s (typ.). The voltage of VIO can be used to supply power to digital function and it is recommended that enable the device after VIO voltage is ready. The RTQ2134 supports enable delay time setting (factory setting) and soft-start slew rate setting for each Buck. The soft-start function is used to prevent large inrush current while the converter is powered up. Register 0x55[5:4], 0x6F[5:4] and 0x89[5:4] let soft-start time of each be programmable. The start -up sequence is shown in Figure 3. IC also implements enable control by software, it can be set in the registers: If the output voltage of Buck is default disable which is only set by factory, the output voltage starts to ramp up by software and the Figure 4 shows the start -up sequence. For disable function, the device supports disable delay time setting (factory setting) by external EN pin and the output voltage ramps down with default discharge resistor. The discharge resistor can be controlled to on or off by register 0x42[0], 0x5F[0] and 0x79[0] when the converter is disabled by software. The power -off sequence is shown in Figure 5 and Figure 6.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 during the LSFET on-time. Once the curre nt rises above the LSFET valley current limit (I LIM_L), the on-time one -shot will be inhibited until the inductor current ramps down to the current limit level (I LIM_L), that is, another on-time can only be triggered when the inductor current goes below th e LSFET current limit. If the output load current exceeds the available inductor current (clamped by the LSFET current limit), the output capacitor needs to supply the extra current so that the output voltage will begin to drop. If it drops below the output under-voltage protection trip threshold, the IC will stop switching to avoid excessive heat. Output Under-Voltage Protection The RTQ2134 includes output under-voltage protection (UVP) against over -load or short -circuited condition by constantly monitoring the output voltage V OUT. If VOUT drops below the under-voltage protection trip threshold (typically 50% of the internal reference voltage), both HSFET and LSFET will stop switching . Register 0x37[3], 0x38[3] and 0x39[3] can select hiccup or latch protection behavior of each Buck converter when converter is in UV condition. For hiccup behavior, both HSFET and LSFET keep low state in a 1ms and then IC starts to switch. If the output voltage is not greater than UV threshold after internal soft -start end sign al is triggered, both HSFET and LSFET will still keep low state again for next cycle. When each Buck is set to latch mode, UVP will let converter enter shutdown mode unless resetting IC by external EN pin or falling to UVLO low threshold. Over-Temperature Protection The RTQ2134 includes an over-temperature protection (OTP) circuitry to prevent overheating due to excessive power dissipation. The OTP shut s down switching operation when junction temperature exceeds a thermal shutdown threshold T SD. Once the ju nction temperature cools down by a thermal shutdown hysteresis ( TSD), the IC resume s normal operation with a complete soft-start. It can select not to shut down IC when OTP happens by using register 0x30[3]. Note that the over-temperature protection is intended to protect the device during momentary overload conditions. The protection is activated outside of the absolute maximum range of operation as a secondary fail-safe and therefore should not be relied upon operationally. Continuous operation above the specified absolute maximum operating jun ction temperature may impair device reliability or permanently damage the device.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Absolute Maximum Ratings (Note 1) ⚫ Power Dissipation, PD @ TA = 25C ⚫ Package Thermal Resistance (Note 2) ⚫ ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)
Electrical Characteristics
(VIN = 3.7V, TJ = −40C to 125C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Analog Input Voltage VAVIN For 2 + 2 application 3.3 -- 6 V Power Input Voltage VPVIN For 2 + 2 application 3.3 -- 6 V Shutdown Current ISHDN EN = 0V, Digital circuit doesn't work -- 1 20 A Buck Off Current ISDBO EN = VIO = 1.8V, disable all Buck by software -- 20 80 A 1Phase no Switching Current ISLP VOUT = 1.2 x VOUT_SETTING -- 70 120 A Under-Voltage Lockout Threshold VUVLO VIN rising 2.1 2.32 2.45 V Under-Voltage Lockout Hysteresis VUVLO -- 300 -- mV High-Side Switch On-Resistance RDS(ON)_H VIN = 5V 18 25 45 m Low-Side Switch On-Resistance RDS(ON)_L VIN = 5V 8 15 25 m
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Parameter Symbol Test Conditions Min Typ Max Unit SDA, SCL, VSELA, WDOG_RST Logic-High VIH 3V VIN 6V 0.7 x VIO -- -- V Logic-Low VIL 3V VIN 6V -- -- 0.3 x VIO EN Threshold Logic-High VENH 1.2 -- -- V Logic-Low VENL -- -- 0.4 External Supply Voltage for I/O Pin VIN_I/O 1.7 1.8 VIN V VOUT DC Accuracy Auto PFM/PWM, VOUT = 1V (Note 5) −2.5 -- 2.5 % Forced PWM, 0.6V VOUT 1.85V −1.5 -- 1.5 % Load Regulation VLOAD IOUT(DC) = 1 to 5A (Note 5) -- −0.08 -- %/A Line Regulation VLINE 3V VIN 6V, IOUT(DC) = 1.5A (Note 5) -- 0.2 -- %/V Load Transient Response 2phase operation, 0.1 to 4A, tR = tF = 1s, L = 0.33H, COUT = 44F/phase (Note 5) -- 40 -- mV 1phase operation, 0.1 to 2A, tR = tF = 1s, L= 0.33H, COUT = 44F/phase (Note 5) -- 40 -- mV Line Transient Response 4V to 5V, tR = tF = 10s (Note 5) -- 40 -- mV Current Balance Load = 10A, |IAvg − ILX_1 or 4 | -- -- 0.5 A Phase Adding Level From 1phase to 2phase (Note 5) -- 3 -- A Phase Shedding Level From 2phase to 1phase (Note 5) -- 2.6 -- A Soft-Start Time Tstart Slew Rate = 10mV/s −20 -- 20 % High-Side Switch Current Limit per Channel ILIM_H 5.8 8 11 A Low-Side Switch Current Limit per Channel ILIM_L 5.1 7 9 A Thermal Shutdown TSD -- 160 -- C Thermal Shutdown Hysteresis TSD -- 30 -- C HOT Die Warning 0xAA = 0x02 (Note 5) -- 109 -- C HOT Die Hysteresis THYSHD (Note 5) -- 15 -- C Discharge Resistor 70 115 180 Output UVP Flag VUVP_T Trigger Level 40 50 60 % VUVP_R Recovery Level -- 57 -- % Output OVP Flag VOVP_T Trigger Level 123 133 143 % VOVP_R Recovery Level -- 125 -- % Switching Frequency fSW VOUT = 1V 1850 2100 2500 kHz
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Error Rate of DVS Slew Rate VIN = 3.7V, VOUT = 0.6V to 1.2V −20 -- 20 % Digital Output Pin : INT Output low level, ISOURCE = 2mA -- -- 0.4 V Push-pull, ISINK = 2mA 1.6 -- VIO V Digital Output Pin : SDA Output low level Resistor -- -- 40 I2C Speed -- -- 3.4 MHz Hold Time (Repeated) Start Condition. After this Period, the First Clock Pulse is Generated tHD;STA Fast mode (Note5) 0.6 -- -- s Low Period of the SCL Clock tLOW Fast mode (Note5) 1.3 -- -- s High Period of the SCL Clock tHIGH Fast mode (Note5) 0.6 -- -- s Set-Up Time for a Repeated START Condition tSU;STA Fast mode (Note5) 0.6 -- -- s Data Hold Time tHD;DAT Fast mode (Note5) 0 -- 0.9 s Data Set-Up Time tSU;DAT Fast mode (Note5) 100 -- -- ns Set-Up Time for STOP Condition tSU;STO Fast mode (Note5) 0.6 -- -- s Bus Free Time between a STOP and START Condition tBUF Fast mode ( Note5) 1.3 -- -- s Rising Time of both SDA and SCL Signals tR Fast mode ( Note5) 20 -- 300 ns Falling Time of both SDA and SCL Signals tF Fast mode ( Note5) 20 -- 300 ns SDA Output Low Sink Current IOL SDA Voltage = 0.4V ( Note5) 2 -- -- mA Detect SDA Low Timeout tTIMEOUT Fast/High speed mode ( Note5) -- 30 -- ms Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a Four-layer Richtek Evaluation Board. θJC is measured at the top of the package. Note 3. Devices are ESD sensitive. Handling precautions are recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Typical Application Circuit 2 + 1 + 1 Phase 0.33uH 10μF VIN 3V to 5.5V RTQ2134 EN RTN1 AVIN LX1 VOUT1PVIN1 PVIN2 PVIN3 PVIN4 LX2 LX4 RTN2 VOUT2 VIO AVIN_FILT SCL SDA VOUT1 (10A) 0.33uH 10μF 10μF 10μF 1.5V to 5.5V 22μF x 4 1.8V LX3 RTN3 VOUT3 PGND AGND 14 0.33uH C8 22μF x 2 VOUT2 (5A) 0.33uH C9 22μF x 2 VOUT3 (5A) 4, 19, 31 VSELA8 WDOG_RST15 INT25Signal Output 1μF 1μF I2C Signal Signal Input 2 + 2 Phase 0.33uH RTQ2134 EN RTN1 AVIN LX1 VOUT1PVIN1 PVIN2 PVIN3 PVIN4 LX2 LX4 RTN2 VOUT2 VIO AVIN_FILT SCL SDA VOUT1 (11A) 0.33uH 1.5V to 5.5V 22μF x 4 1.8V LX3 RTN3 VOUT3 PGND AGND 14 0.33uH 22μF x 4 VOUT2 (9A) 0.33uH 4, 19, 31 VSELA8 WDOG_RST15 INT25Signal Output 1μF 1μF 10μF VIN 3.3V to 5.5V 10μF 10μF 10μF I2C Signal Signal Input
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 2. Recommended BOM
- COUT = 44F per-phase is min. value for the RTQ2134.
- All the input and output capacitors are the suggested values, referring to the effective capacitances, subject to
any de-rating effect, like a DC bias.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Typical Operating Characteristics Efficiency vs. Output Current 100 0 1 2 3 4 5 6 7 8 9 10 11 Output Current (A) Efficiency (%) VIN = 3.3V VIN = 5V Two Phase, VOUT = 1V Efficiency vs. Output Current 100 Output Current (A) Efficiency (%) Single Phase, VOUT = 1V VIN = 3.3V VIN = 5V Output Voltage vs. Output Current 0.975 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 0 1 2 3 4 5 6 7 8 9 10 11 Output Current (A) Output Voltage (V) VIN = 5V VIN = 3.3V Two Phase, VOUT = 1V, FCCM Output Voltage vs. Output Current 0.975 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 Output Current (A) Output Voltage (V) Single Phase, VOUT = 1V, FCCM VIN = 5V VIN = 3.3V Output Voltage vs. Input Voltage 0.975 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 Input Voltage (V) Output Voltage (V)IOUT = 0A IOUT = 11A Two Phase, VOUT = 1V, FCCM Output Voltage vs. Input Voltage 0.975 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 Input Voltage (V) Output Voltage (V) IOUT = 0A IOUT = 5.5A Single Phase, VOUT =1V, FCCM
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com VIN = 3.8V, VOUT = 1V, IOUT = 0.1A to 4A TR = TF = 1s, FCCM, L = 0.33H COUT = 22F/1206/6.3V x 4 VOUT (20mV/Div) IOUT (2A/Div) Time (4s/Div) Load Transient Response-Two Phase VOUT (20mV/Div) IOUT (2A/Div) Time (4s/Div) Load Transient Response-Two Phase VIN = 3.8V, VOUT = 1V, IOUT = 4A to 0.1A TR = TF = 1s, FCCM, L = 0.33H COUT = 22F/1206/6.3V x 4 VOUT (20mV/Div) IOUT (1A/Div) Time (4s/Div) Load Transient Response-Single Phase VIN = 3.8V, VOUT = 1V, IOUT = 0.1A to 2A TR = TF = 1s, FCCM, L = 0.33H COUT = 22F/1206/6.3V x 2 VOUT (20mV/Div) IOUT (1A/Div) Time (4s/Div) Load Transient Response-Single Phase VIN = 3.8V, VOUT = 1V, IOUT = 2A to 0.1A TR = TF = 1s, FCCM, L = 0.33H COUT = 22F/1206/6.3V x 2 Time (1ms/Div) OCP Hiccup - Two Phase VOUT (500mV/Div) VLX1 (10V/Div) ILX4 (5A/Div) ILX1 (5A/Div) VIN = 3.8V, VOUT = 0.8V Time (1ms/Div) OCP Hiccup - Single Phase VOUT (400mV/Div) VLX2 (10V/Div) ILX2 (5A/Div) VIN = 3.8V, VOUT = 1.1V
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Time (500ns/Div) Output Ripple - Two Phase VOUT (10mV/Div) VLX4 (5V/Div) IOUT (5A/Div) VIN = 3.8V, VOUT = 1V, IOUT = 11A VLX1 (5V/Div) Time (500ns/Div) Output Ripple - Single Phase VOUT (10mV/Div) VLX2 (3V/Div) IOUT (5A/Div) VIN = 3.8V, VOUT = 1V, IOUT = 5.5A EN Threshold Voltage vs. Temperature 0.70 0.75 0.80 0.85 0.90 0.95 1.00 -50 -25 0 25 50 75 100 125 Temperature (°C) EN Threshold Voltage (V) Rising Falling VIN = 3.6V EN Pin Current vs. Temperature 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -50 -25 0 25 50 75 100 125 Temperature (°C) EN Pin Current (μA) VEN = 3.3V Current Limit vs. Temperature 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 -50 -25 0 25 50 75 100 125 Temperature (°C) Current Limit (A) HSFET VIN = 5.5V_Peak VIN = 4V_Peak MOSFET RDS(ON) vs. Temperature -50 -25 0 25 50 75 100 125 Temperature (°C) RDS(ON) (mΩ) RDS(ON)_H RDS(ON)_L VIN = 5V
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Radiated EMI Performance with Peak Limits 0.1 1 10 100 1000 Frequency (MHz) Emission Level (dBμV/m) VOUT1 = VOUT2 = 1V, IOUT1 = 8A (0.125Ω), IOUT2 = 6A (0.167Ω), FCCM, With EMI Filter CISPR25 Class 5 Peak Limit Vertical Polarization Horizontal Polarization
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022
Application Information
The RTQ2134 is a power management IC that integrates four high efficien cy Buck converters, and is capable of multiphas e or single -phase operation. The RTQ2134 supports 2 + 1 + 1 and 2 + 2 configuration. Inductor Selection The inductor selection are trade-offs among size, cost, efficiency, and transient response requirements. Generally, three key inductor parameters are specified for operation with the device: inductance value (L), inductor saturation current (I SAT), and DC resistance (DCR). A good compromise between size and loss is a 30% peak-to-peak ripple current to the IC rated current, but it still depends on size consideration. The inductor used in the Typical Applicati on Circuit of this datasheet is recommended. The switching frequency, input voltage, output voltage, and selected inductor ripple current determine the inductor value as follows : OUT IN OUT IN SW L V (V V )L = V f I To enhance the efficiency, choose a low -loss inductor having the lowest possible DC R that fits in the allotted dimensions. The selected inductor should have a saturation current rating greater than the peak current limit of the device. The core must be large enough not to saturate at the peak inductor current (IL_PEAK) : OUT IN OUT L IN SW L_PEAK OUT_MAX L V (V V )I = V f L 1I = I + I 2 The current flowing through the inductor is the inductor ripple current plus the output current. During power -up, faults, or transient load conditions, the inductor current can increase the peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. Input Capacitor Selection Input capacitance, CIN, is needed to filter the pulsating current at the drain of the HSFET. The CIN should be sized to do this without causing a large variatio n in input voltage. Several capacitors may also be paralleled to meet size, height and thermal requirements in the design. For low input voltage applications, sufficient bulk input capacitance is needed to minimize transient effects during output load changes. The input capacitor should be placed as close as possible to each VIN pin with a low inductance connection to the PGND of the IC. It is recommended to connect capacitors between the VIN pin and the PGND pin as shown in the Typical Application Circuit. The larger input capacitance is required when a lower switching frequency is used. The X7R capacitors are recommended for best performance across temperature and input voltage variations. Output Capacitor Selection The selection of C OUT is determined by considering to satisfy the voltage ripple and the transient loads. The peak-to-peak output ripple, VOUT, is determined by : OUT L OUT SW where the IL is the peak -to-peak inductor ripple current. The highest output ripple is at maximum input voltage since IL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Ceramic capacitors have very low equivalent series resistance (ESR) and provide the best ripple performance. The X7R dielectric capacitor is recommended for the best performance across temperature and input voltage variations. The variation of the capacitance value with temperature, DC bias voltage and switching frequency needs to be taken into consideration. For example, the capacitance value of a capacitor decreases as the DC bias across the capacitor increases. Be careful to consider the voltage coefficient of ceramic capacitors when choosing the
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com value and case size. Most ceramic capacitors lose 50% or more of their rated value s when used near their rated voltage. Transient performance can be improved with a higher value output capacitor. Increasing the output capacitance will also decrease the output voltage ripple. The recommended output cap acitors are shown in Typical Application Circuit section. Thermal Considerations In many applications, the RTQ2134 does not generate much heat due to its high efficiency and low thermal resistance of its WQFN - 30L 4.5x5 package. However, in applications where the RTQ2134 runs at a high ambient temperature and high input voltage or high switching frequency, the generated heat may exceed the maximum junction temperature of the part. The junction temperature should never exceed the absolute maximum junction temperatur e TJ(MAX), listed under Absolute Maximum Ratings, to avoid permanent damage to the device. If the junction temperature reaches approximately 1 60°C, the RTQ2134 stops switching the power MOSFETs until the temperature cools down by 30°C. The maximum power di ssipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) /JA(EFFECTIVE) where TJ(MAX) is the maximum allowed junction temperature of the die. For recommended operating condition specifications, the maximum junction temperature is 125°C. TA is the ambient operating temperature, JA(EFFECTIVE) is the system -level junction to ambient thermal resistance. It can be estimated from thermal modeling or measurements in the system. The thermal resistance of the device strongly depends on the surrounding PCB layout and can be improved by providing a heat sink of surrounding copper ground. The addition of backside copper with thermal vias, stiffeners, and other enhancements can also help reduce thermal resistance. Experiments in the Richtek thermal lab show that simply set JA(EFFECTIVE) as 110% to 120% of the JA is reasonable to obtain the allowed PD(MAX). The power loss of system can be found in the efficiency measurement and the formula below can be used to determine the power loss of IC by removing the loss of inductor including DC loss and AC loss. Two-phase converter power loss : 2OUT loss IN IN OUT OUT 2OUT OUT core_loss 22 INSW IP = (V I V I ) (( ) DCR) 2 2 V ACR VP 2 ( (1 ) ) 2 V12 L f Single-phase converter power loss : loss IN IN OUT OUT OUT core_loss 2OUT OUT
22 INSW
P = (V I V I ) I DCR P V ACR V (1 ) V12 L f − − Where Pcore_loss and ACR need to be obtained from inductor supplier. Total loss of IC can not be larger than maximum power loss. If the application requires a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or air flow. Note that t he over-temperature protection is intended to protect the device during momentary overload conditions. The protection is activated outside of the absolute maximum range of operation as a secondary fail -safe and therefore should not be relied upon operation ally. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Layout Guidelines When laying out the printed circuit board, the following checklist should be us ed to ensure proper operation of the RTQ2134 : Four-layer or six -layer PCB with maximum ground plane is strongly recommended for good thermal performance. Keep the traces of the main current paths wide and short.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 10. Layout Guideline for 2 + 2 Application
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Figure 13. A Complete Hs-mode Transfer
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 3. I2C Register Summary
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x38 FLT_BUCK 2_CTRL Reserved FLT_BU CK2_CT RLUV Reserved 0x0C 0x39 FLT_BUCK 3_CTRL Reserved FLT_BU CK3_CT RLUV Reserved 0x0C 0x3E BUCK1_ RAMP Reserved BUCK1_ DVS_UP Reserved BUCK1_ DVS_DO WN Reserved 0x44 0x42 BUCK1_ CFG0 Reserved BUCK1_ DIS 0x01 0x48 BUCK1_ DVS0CFG1 BUCK1_DVS0 0x8C 0x49 BUCK1_ DVS0CFG0 Reserved BUCK1_ DVS0M ODE Reserved BUCK1_ ENDVS0 0x00 0x4A BUCK1_ DVS1CFG1 BUCK1_DVS1 0x8C 0x4B BUCK1_ DVS1CFG0 Reserved BUCK1_ DVS1M ODE Reserved BUCK1_ ENDVS1 0x00 0x52 BUCK1_ DVSCFG Reserved BUCK1_ DVSPIN _POL BUCK1_DVS_ CTRL 0x00 0x54 BUCK1_ RSPCFG Reserved BUCK1_RSPUP Reserved BUCK1_RSPDN 0x14 0x55 BUCK1_ SLEWCTRL Reserved BUCK1_SS_ SLEW Reserved 0x00 0x5B BUCK2_ RAMP Reserved BUCK2_ DVS_UP Reserved BUCK2_ DVS_DO WN Reserved 0x44 0x5F BUCK2_ CFG0 Reserved BUCK2_ DIS 0x01 0x62 BUCK2_ DVS0CFG1 BUCK2_DVS0 0x8C 0x63 BUCK2_ DVS0CFG0 Reserved BUCK2_ DVS0M ODE Reserved BUCK2_ ENDVS0 0x00 0x64 BUCK2_ DVS1CFG1 BUCK2_DVS1 0x8C 0x65 BUCK2_ DVS1CFG0 Reserved BUCK2_ DVS1M ODE Reserved BUCK2_ ENDVS1 0x00 0x6C BUCK2_ DVSCFG Reserved BUCK2_ DVSPIN _POL BUCK2_DVS_ CTRL 0x00 0x6E BUCK2_ RSPCFG Reserved BUCK2_RSPUP Reserved BUCK2_RSPDN 0x14
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0x6F BUCK2_ SLEWCTRL Reserved BUCK2_SS_ SLEW Reserved 0x00 0x75 BUCK3_ RAMP Reserved BUCK3_ DVS_UP Reserved BUCK3_ DVS_DO WN Reserved 0x44 0x79 BUCK3_ CFG0 Reserved BUCK3_ DIS 0x01 0x7C BUCK3_ DVS0CFG1 BUCK3_DVS0 0x8C 0x7D BUCK3_ DVS0CFG0 Reserved BUCK3_ DVS0M ODE Reserved BUCK3_ ENDVS0 0x00 0x7E BUCK3_ DVS1CFG1 BUCK3_DVS1 0x8C 0x7F BUCK3_ DVS1CFG0 Reserved BUCK3_ DVS1M ODE Reserved BUCK3_ ENDVS1 0x00 0x86 BUCK3_ DVSCFG Reserved BUCK3_ DVSPIN _POL BUCK3_DVS_ CTRL 0x00 0x88 BUCK3_ RSPCFG Reserved BUCK3_RSPUP Reserved BUCK3_RSPDN 0x14 0x89 BUCK3_ SLEWCTR Reserved BUCK3_SS_ SLEW Reserved 0x00
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 4. I2C Register Map
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x0C Register Name IO_DIEID1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 0 1 1 1 0 1 0 Read/Write R R R R R R R R Bits Name Description Bit 7 to Bit 0 IO_DIEID1 IO_DIEID1 Register Address 0x0D Register Name IO_DIEID0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 0 0 1 1 0 0 0 Read/Write R R R R R R R R Bits Name Description Bit 7 to Bit 0 IO_DIEID0 IO_DIEID0 Register Address 0x0F Register Name IO_SOFTRESET Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R R R R R R RW Bits Name Description Bit 7 to Bit 1 Reserved Reserved bits Bit 0 IO_SOFTRESET Reset all digital functions to default setting. 0 : Not changed 1 : Reset and bit cleared
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x13 Register Name FLT_RECORDTEMP Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write RC R R R R RC RC R Bits Name Description Bit 7 FLT_BOOT Boot interrupt indicator. Read only and automatically cleared. 0 : Boot process doesn't occur. AVIN is less than UVLO rising threshold. 1 : Boot process has occurred. AVIN is greater than UVLO rising threshold or less than UVLO falling threshold. Bit 6 to Bit 3 Bit 0 Reserved Reserved bits Bit 2 FLT_HOTDIE Hot die interrupt indicator. Read only and automatically cleared. 0 : Temp of die is lower than threshold. 1 : Die hot. Greater than threshold. Bit 1 FLT_TEMPSDR OT interrupt indicator. Read only and automatically cleared. 0 : No Fault. Less than threshold. 1 : Fault. Greater than threshold or during fault recovery. Register Address 0x14 Register Name FLT_RECORDBUCK1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RC RC R R R R Bits Name Description Bit 7 BUCK1_PG Power good status indicator. 0 : VOUT > 110% of setting VOUT or VOUT < 90% of setting VOUT 1 : 110% of setting VOUT > VOUT > 90% of setting VOUT Bit 6 Bit 3 to Bit 0 Reserved Reserved bits Bit 5 FLT_BUCK1_OV OV interrupt indicator. Read only and automatically cleared. 0 : No Fault. Less than threshold. 1 : Fault. Greater than threshold. Bit 4 FLT_BUCK1_UV UV interrupt indicator. Read only and automatically cleared. 0 : No Fault. Greater than threshold. 1 : Fault. Less than threshold or during fault recovery.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x15 Register Name FLT_RECORDBUCK2 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RC RC R R R R Bits Name Description Bit 7 BUCK2_PG Power good status indicator. 0 : VOUT > 110% of setting VOUT or VOUT < 90% of setting VOUT 1 : 110% of setting VOUT > VOUT > 90% of setting VOUT Bit 6 Bit 3 to Bit 0 Reserved Reserved bits Bit 5 FLT_BUCK2_OV OV interrupt indicator. Read only and automatically cleared. 0 : No Fault. Less than threshold. 1 : Fault. Greater than threshold. Bit 4 FLT_BUCK2_UV UV interrupt indicator. Read only and automatically cleared. 0 : No Fault. Greater than threshold. 1 : Fault. Less than threshold or during fault recovery. Register Address 0x16 Register Name FLT_RECORDBUCK3 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RC RC R R R R Bits Name Description Bit 7 BUCK3_PG Power good status indicator. 0 : VOUT > 110% of setting VOUT or VOUT < 90% of setting VOUT 1 : 110% of setting VOUT > VOUT > 90% of setting VOUT Bit 6 Bit 3 to Bit 0 Reserved Reserved bits Bit 5 FLT_BUCK3_OV OV interrupt indicator. Read only and automatically cleared. 0 : No Fault. Less than threshold. 1 : Fault. Greater than threshold. Bit 4 FLT_BUCK3_UV UV interrupt indicator. Read only and automatically cleared. 0 : No Fault. Greater than threshold. 1 : Fault. Less than threshold or during fault recovery.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x22 Register Name IO_I2CCFG Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 1 1 0 0 0 Read/Write R R R R R R R R Bits Name Description Bit 7 Reserved Reserved bits Bit 6 to Bit 0 IO_I2CADDR IO_I2CADDR Register Address 0x25 Register Name IO_RSTDVS Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R RW RW RW R RW RW RW Bits Name Description Bit 7 and Bit 3 Reserved Reserved bits Bit 6 IO_RSTDVS Enable/disable Buck3 watchdog reset function to default voltage when WDOG_RST pin is pulled low. 1 : Enable 0 : Disable Bit 5 Enable/disable Buck2 watchdog reset function to default voltage when WDOG_RST pin is pulled low. 1 : Enable 0 : Disable Bit 4 Enable/disable Buck1 watchdog reset function to default voltage when WDOG_RST pin is pulled low. 1 : Enable 0 : Disable Bit 2 to Bit 0 IO_DBNTIME Watchdog Debounce Time 000 : 0ms (Default) 100 : 12.5ms 001 : 1.56ms 101 : 9ms 010 : 3.125ms 110 : 15.25ms 011 : 6.25ms 111 : 14.5ms
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x30 Register Name FLT_OT_CTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R R R RW R R R Bits Name Description Bit 7 to Bit 4 Bit 2 to Bit 0 Reserved Reserved bits Bit 3 FLT_CTRLOT1 When OT is detected, the Buck can be set to shutdown or not shutdown. 0 : Shutdown 1 : Not Shutdown Register Address 0x32 Register Name FLT_MASKTEMP Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write RW R R R R RW RW R Bits Name Description Bit 7 FLT_MASKBOOT Masking the BOOT detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 6 to Bit 3 Bit 0 Reserved Reserved bits Bit 2 FLT_MASKHD Masking the Hot die detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 1 FLT_MASKTSDR Masking the Thermal shutdown detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x33 Register Name FLT_MASKBUCK1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write RW RW RW RW R R R R Bits Name Description Bit 7 FLT_BUCK1MASKPG Masking Buck1 power good detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 6 BUCK1INTACT Write this bit to "1" to ensure Buck1 INT function normally. "0" is reserved for Richtek internal use only. Bit 5 FLT_BUCK1MASKOV Masking Buck1 over-voltage detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 4 FLT_BUCK1MASKUV Masking Buck1 under-voltage detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 3 to Bit 0 Reserved Reserved bits Register Address 0x34 Register Name FLT_MASKBUCK2 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write RW RW RW RW R R R R Bits Name Description Bit 7 FLT_BUCK2MASKPG Masking Buck2 power good detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 6 BUCK2INTACT Write this bit to "1" to ensure Buck2 INT function normally. "0" is reserved for Richtek internal use only. Bit 5 FLT_BUCK2MASKOV Masking Buck2 over-voltage detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 4 FLT_BUCK2MASKUV Masking Buck2 under-voltage detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 3 to Bit 0 Reserved Reserved bits
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x35 Register Name FLT_MASKBUCK3 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write RW RW RW RW R R R R Bits Name Description Bit 7 FLT_BUCK3MASKPG Masking Buck3 power good detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 6 BUCK3INTACT Write this bit to "1" to ensure Buck3 INT function normally. "0" is reserved for Richtek internal use only. Bit 5 FLT_BUCK3MASKOV Masking Buck3 over-voltage detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 4 FLT_BUCK3MASKUV Masking Buck3 under-voltage detection signal. 0 : Pass internal logic output to INT pin. 1 : Mask internal logic output to INT pin. Bit 3 to Bit 0 Reserved Reserved bits Register Address 0x37 Register Name FLT_BUCK1_CTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 1 1 0 0 Read/Write R R R R RW R R R Bits Name Description Bit 7 to Bit 4 Bit 2 to Bit 0 Reserved Reserved bits Bit 3 FLT_BUCK1_ CTRLUV Latch or hiccup protection behavior when Buck1 suffers UV detection. 0 : UV Shutdown 1 : UV Hiccup Register Address 0x38 Register Name FLT_BUCK2_CTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 1 1 0 0 Read/Write R R R R RW R R R Bits Name Description Bit 7 to Bit 4 Bit 2 to Bit 0 Reserved Reserved bits Bit 3 FLT_BUCK2_ CTRLUV Latch or hiccup protection behavior when Buck2 suffers UV detection. 0 : UV Shutdown 1 : UV Hiccup
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x39 Register Name FLT_BUCK3_CTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 1 1 0 0 Read/Write R R R R RW R R R Bits Name Description Bit 7 to Bit 4 Bit 2 to Bit 0 Reserved Reserved bits Bit 3 FLT_BUCK3_ CTRLUV Latch or hiccup protection behavior when Buck3 suffers UV detection. 0 : UV Shutdown 1 : UV Hiccup Register Address 0x3E Register Name BUCK1_RAMP Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 1 0 0 0 1 0 0 Read/Write R RW R R R RW R R Bits Name Description Bit 7 Bit 5 to Bit 3 Bit 1 to Bit 0 Reserved Reserved bits Bit 6 BUCK1_DVS_UP The operation mode when Buck1 ramps up. 0 : Auto Mode 1 : FCCM Bit 2 BUCK1_DVS_DOWN The operation mode when Buck1 ramps down. 0 : Decay Mode 1 : FCCM Register Address 0x42 Register Name BUCK1_CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 1 Read/Write R R R R R R R RW Bits Name Description Bit 7 to Bit 1 Reserved Reserved bits Bit 0 BUCK1_DIS The output discharge resistor operates when Buck1 is turned off by software or external enable pin. 0 : Disable output discharge resistor. 1 : Enable output discharge resistor.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x48 Register Name BUCK1_DVS0CFG1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 0 0 0 1 1 0 0 Read/Write RW RW RW RW RW RW RW RW Bits Name Description Bit 7 to Bit 0 BUCK1_DVS0 Buck1 DVS0 output voltage setting SEL[7:0] = 11111111 : VOUT = 1.85V SEL[7:0] = 11001000 : VOUT = 1.3V SEL[7:0] = 0000000 : 0.3V For 0.3V to 1.3V, VOUT = 0.3V + SEL7:0 x 5mV For 1.3V to 1.85V, VOUT = 1.3V + {SEL7:0 - 200} x 10mV Register Address 0x49 Register Name BUCK1_DVS0CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW R R R R RW Bits Name Description Bit 7 to Bit 6 Bit 4 to Bit 1 Reserved Reserved bits Bit 5 BUCK1_DVS0MODE Buck1 DVS0 operation mode setting 0 : Auto Mode 1 : FCCM Note : Please enable all the set outputs before setting into the FCCM. Bit 0 BUCK1_ENDVS0 Enable or disable Buck1 DVS0 0 : Disable 1 : Enable Register Address 0x4A Register Name BUCK1_DVS1CFG1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 0 0 0 1 1 0 0 Read/Write RW RW RW RW RW RW RW RW Bits Name Description Bit 7 to Bit 0 BUCK1_DVS1 Buck1 DVS1 output voltage setting SEL[7:0] = 11111111 : VOUT = 1.85V SEL[7:0] = 11001000 : VOUT = 1.3V SEL[7:0] = 0000000 : 0.3V For 0.3V to 1.3V, VOUT = 0.3V + SEL7:0 x 5mV For 1.3V to 1.85V, VOUT = 1.3V + {SEL7:0 - 200} x 10mV
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x4B Register Name BUCK1_DVS1CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW R R R R RW Bits Name Description Bit 7 to Bit 6 Bit 4 to Bit 1 Reserved Reserved bits Bit 5 BUCK1_DVS1MODE Buck1 DVS1 operation mode setting 0 : Auto Mode 1 : FCCM Note : Please enable all the set outputs before setting into the FCCM. Bit 0 BUCK1_ENDVS1 Enable or disable Buck1 DVS1 0 : Disable 1 : Enable Register Address 0x52 Register Name BUCK1_DVSCFG Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R R R R RW RW RW Bits Name Description Bit 7 to Bit 3 Reserved Reserved bits Bit 2 BUCK1_DVSPIN_ POL When Buck1 DVS up and down operations are controlled by using external VSELA pin, this bit can define the polarity for VSELA. 0 : VSELA = 1 → use DVS0 setting VSELA = 0 → use DVS1 setting 1 : VSELA = 1 → use DVS1 setting VSELA = 0 → use DVS0 setting Bit 1 to Bit 0 BUCK1_DVS_CTRL Buck1 DVS up and down operations are controlled by software or external pin. 00 : Use DVS0 setting 01 : Use DVS1 setting 10 : Controlled by VSELA pin
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x54 Register Name BUCK1_RSPCFG Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 1 0 1 0 0 Read/Write R RW RW RW R RW RW RW Bits Name Description Bit 7, Bit 3 Reserved Reserved bits Bit 6 to Bit 4 BUCK1_RSPUP Buck1 DVS slew rate setting for DVS UP 001 = 16mV/s 101 = 2mV/s 011 = 8mV/s 110 = 1mV/s Bit 2 to Bit 0 BUCK1_RSPDN Buck1 DVS slew rate setting for DVS Down 001 = 16mV/s 101 = 2mV/s 011 = 8mV/s 110 = 1mV/s Register Address 0x55 Register Name BUCK1_SLEWCTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW RW R R R R Bits Name Description Bit 7 to Bit 6 Bit 3 to Bit 0 Reserved Reserved bits Bit 5 to Bit 4 BUCK1_SS_SLEW Set the soft-start slew rate when Buck1 is turned on by software or external enable pin. Register Address 0x5B Register Name BUCK2_RAMP Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 1 0 0 0 1 0 0 Read/Write R RW R R R RW R R Bits Name Description Bit 7 Bit 5 to Bit 3 Bit 1 to Bit 0 Reserved Reserved bits Bit 6 BUCK2_DVS_UP The operation mode when Buck2 ramps up. 0 : Auto Mode 1 : FCCM Bit 2 BUCK2_DVS_DOWN The operation mode when Buck2 ramps down. 0 : Decay Mode 1 : FCCM
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x5F Register Name BUCK2_CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 1 Read/Write R R R R R R R RW Bits Name Description Bit 7 to Bit 1 Reserved Reserved bits Bit 0 BUCK2_DIS The output discharge resistor operation when Buck2 is turned off by software or external enable pin. 0 : Disable output discharge resistor. 1 : Enable output discharge resistor. Register Address 0x62 Register Name BUCK2_DVS0CFG1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 0 0 0 1 1 0 0 Read/Write RW RW RW RW RW RW RW RW Bits Name Description Bit 7 to Bit 0 BUCK2_DVS0 Buck2 DVS0 output voltage setting SEL[7:0] = 11111111 : VOUT = 1.85V SEL[7:0] = 11001000 : VOUT = 1.3V SEL[7:0] = 0000000 : 0.3V For 0.3V to 1.3V, VOUT = 0.3V + SEL7:0 x 5mV For 1.3V to 1.85V, VOUT = 1.3V + {SEL7:0 - 200} x 10mV Register Address 0x63 Register Name BUCK2_DVS0CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW R R R R RW Bits Name Description Bit 7 to Bit 6 Bit 4 to Bit 1 Reserved Reserved bits Bit 5 BUCK2_DVS0MODE Buck2 DVS0 operation mode setting 0 : Auto Mode 1 : FCCM Note : Please enable all the set outputs before setting into the FCCM. Bit 0 BUCK2_ENDVS0 Enable or disable Buck2 DVS0 0 : Disable 1 : Enable
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x64 Register Name BUCK2_DVS1CFG1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 0 0 0 1 1 0 0 Read/Write RW RW RW RW RW RW RW RW Bits Name Description Bit 7 to Bit 0 BUCK2_DVS1 Buck2 DVS1 output voltage setting SEL[7:0] = 11111111 : VOUT = 1.85V SEL[7:0] = 11001000 : VOUT = 1.3V SEL[7:0] = 0000000 : 0.3V For 0.3V to 1.3V, VOUT = 0.3V + SEL7:0 x 5mV For 1.3V to 1.85V, VOUT = 1.3V + {SEL7:0 - 200} x 10mV Register Address 0x65 Register Name BUCK2_DVS1CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW R R R R RW Bits Name Description Bit 7 to Bit 6 Bit 4 to Bit 1 Reserved Reserved bits Bit 5 BUCK2_DVS1MODE Buck2 DVS1 operation mode setting 0 : Auto Mode 1 : FCCM Note : Please enable all the set outputs before setting into the FCCM. Bit 0 BUCK2_ENDVS1 Enable or disable Buck2 DVS1 0 : Disable 1 : Enable
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x6C Register Name BUCK2_DVSCFG Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R R R R RW RW RW Bits Name Description Bit 7 to Bit 3 Reserved Reserved bits Bit 2 BUCK2_DVSPIN_ POL When Buck2 DVS up and down operations are controlled by using external VSELA pin, this bit can define the polarity for VSELA. 0 : VSELA = 1 → use DVS0 setting VSELA = 0 → use DVS1 setting 1 : VSELA = 1 → use DVS1 setting VSELA = 0 → use DVS0 setting Bit 1 to Bit 0 BUCK2_DVS_CTRL Buck2 DVS up and down operations are controlled by software or external pin. 00 : Use DVS0 setting 01 : Use DVS1 setting 10 : Controlled by VSELA pin Register Address 0x6E Register Name BUCK2_RSPCFG Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 1 0 1 0 0 Read/Write R RW RW RW R RW RW RW Bits Name Description Bit 7, Bit 3 Reserved Reserved bits Bit 6 to Bit 4 BUCK2_RSPUP Buck2 DVS slew rate setting for DVS UP 001 = 16mV/s 101 = 2mV/s 011 = 8mV/s 110 = 1mV/s Bit 2 to Bit 0 BUCK2_RSPDN Buck2 DVS slew rate setting for DVS Down 001 = 16mV/s 101 = 2mV/s 011 = 8mV/s 110 = 1mV/s
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x6F Register Name BUCK2_SLEWCTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW RW R R R R Bits Name Description Bit 7 to Bit 6 Bit 3 to Bit 0 Reserved Reserved bits Bit 5 to Bit 4 BUCK2_SS_SLEW Set the soft-start slew rate when Buck2 is turned on by software or external enable pin. Register Address 0x75 Register Name BUCK3_RAMP Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 1 0 0 0 1 0 0 Read/Write R RW R R R RW R R Bits Name Description Bit 7 Bit 5 to Bit 3 Bit 1 to Bit 0 Reserved Reserved bits Bit 6 BUCK3_DVS_UP The operation mode when Buck3 ramps up. 0 : Auto Mode 1 : FCCM Bit 2 BUCK3_DVS_DOWN The operation mode when Buck3 ramps down. 0 : Decay Mode 1 : FCCM Register Address 0x79 Register Name BUCK3_CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 1 Read/Write R R R R R R R RW Bits Name Description Bit 7 to Bit 1 Reserved Reserved bits Bit 0 BUCK3_DIS The output discharge resistor operation when Buck3 is turned off by software or external enable pin. 0 : Disable output discharge resistor. 1 : Enable output discharge resistor.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x7C Register Name BUCK3_DVS0CFG1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 0 0 0 1 1 0 0 Read/Write RW RW RW RW RW RW RW RW Bits Name Description Bit 7 to Bit 0 BUCK3_DVS0 Buck3 DVS0 output voltage setting SEL[7:0] = 11111111 : VOUT = 1.85V SEL[7:0] = 11001000 : VOUT = 1.3V SEL[7:0] = 0000000 : 0.3V For 0.3V to 1.3V, VOUT = 0.3V + SEL7:0 x 5mV For 1.3V to 1.85V, VOUT = 1.3V + {SEL7:0 - 200} x 10mV Register Address 0x7D Register Name BUCK3_DVS0CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW R R R R RW Bits Name Description Bit 7 to Bit 6 Bit 4 to Bit 1 Reserved Reserved bits Bit 5 BUCK3_DVS0MODE Buck3 DVS0 operation mode setting 0 : Auto Mode 1 : FCCM Note : Please enable all the set outputs before setting into the FCCM. Bit 0 BUCK3_ENDVS0 Enable or disable Buck3 DVS0 0 : Disable 1 : Enable Register Address 0x7E Register Name BUCK3_DVS1CFG1 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 1 0 0 0 1 1 0 0 Read/Write RW RW RW RW RW RW RW RW Bits Name Description Bit 7 to Bit 0 BUCK3_DVS1 Buck3 DVS1 output voltage setting SEL[7:0] = 11111111 : VOUT = 1.85V SEL[7:0] = 11001000 : VOUT = 1.3V SEL[7:0] = 0000000 : 0.3V For 0.3V to 1.3V, VOUT = 0.3V + SEL7:0 x 5mV For 1.3V to 1.85V, VOUT = 1.3V + {SEL7:0 - 200} x 10mV
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Register Address 0x7F Register Name BUCK3_DVS1CFG0 Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW R R R R RW Bits Name Description Bit 7 to Bit 6 Bit 4 to Bit 1 Reserved Reserved bits Bit 5 BUCK3_DVS1MODE Buck3 DVS1 operation mode setting 0 : Auto Mode 1 : FCCM Note : Please enable all the set outputs before setting into the FCCM. Bit 0 BUCK3_ENDVS1 Enable or disable Buck3 DVS1 0 : Disable 1 : Enable Register Address 0x86 Register Name BUCK3_DVSCFG Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R R R R RW RW RW Bits Name Description Bit 7 to Bit 3 Reserved Reserved bits Bit 2 BUCK3_DVSPIN_ POL When Buck3 DVS up and down operations are controlled by using external VSELA pin, this bit can define the polarity for VSELA. 0 : VSELA = 1 → use DVS0 setting VSELA = 0 → use DVS1 setting 1 : VSELA = 1 → use DVS1 setting VSELA = 0 → use DVS0 setting Bit 1 to Bit 0 BUCK3_DVS_CTRL Buck3 DVS up and down operations are controlled by software or external pin. 00 : Use DVS0 setting 01 : Use DVS1 setting 10 : Controlled by VSELA pin
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Register Address 0x88 Register Name BUCK3_RSPCFG Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 1 0 1 0 0 Read/Write R RW RW RW R RW RW RW Bits Name Description Bit 7, Bit 3 Reserved Reserved bits Bit 6 to Bit 4 BUCK3_RSPUP Buck3 DVS slew rate setting for DVS UP 001 = 16mV/s 101 = 2mV/s 011 = 8mV/s 110 = 1mV/s Bit 2 to Bit 0 BUCK3_RSPDN Buck3 DVS slew rate setting for DVS Down 001 = 16mV/s 101 = 2mV/s 011 = 8mV/s 110 = 1mV/s Register Address 0x89 Register Name BUCK3_SLEWCTRL Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default 0 0 0 0 0 0 0 0 Read/Write R R RW RW R R R R Bits Name Description Bit 7 to Bit 6 Bit 3 to Bit 0 Reserved Reserved bits Bit 5 to Bit 4 BUCK3_SS_SLEW Set the soft-start slew rate when Buck3 is turned on by software or external enable pin.
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 R 0.050 0.150 0.002 0.006 Tolerance WET W-Type 30L QFN 4.5x5 (FC) Package
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2134-QA-02 May 2022 www.richtek.com Footprint Information Package Number of Pin Tolerance WET-V/W/U/XQFN4.5x5-30(FC) 30 ±0.05
Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2134-QA-02 May 2022 Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications witho ut notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of pa tents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.