RT8015 RICHTEK | Alldatasheet
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Technical content
Features
l High Efficiency : Up to 95% l Low RDS(ON) Internal Switches : 110mW l Programmable Frequency : 300kHz to 2MHz l No Schottky Diode Required l 0.8V Reference Allows Low Output Voltage l Forced Continuous Mode Operation l Low Dropout Operation : 100% Duty Cycle l RoHS Compliant and 100% Lead (Pb)-Free SHDN/RT GND LX PGND COMP FB PVDD VDD GND 4 5 Package Type SP : SOP-8 (Exposed Pad-Option 2) RT8015 Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free)
DS8015-03 March 2011www.richtek.com Functional Pin Description Pin No. Pin Name Pin Function 1 SHDN/RT Oscillator Resistor Input. Connecting a resistor to ground from this pin sets the switching frequency. Forcing this pin to VDD causes the device to be shut down. 9 (Exposed Pad) GND Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 3 LX Internal Power MOSFET Switches Output. Connect this pin to the inductor. 4 PGND Power Ground. Connect this pin close to the ( −) terminal of CIN and COUT. 5 PVDD Power Input Supply. Decouple this pin to PGND with a capacitor. 6 VDD Signal Input Supply. Decouple this pin to GND with a capacitor. Normally V DD is equal to PVDD. 7 FB Feedback Pin. Receives the feedback voltage from a resistive divider connected across the output.
8 COMP
Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Connect external compensation elements to this pin to stabilize the control loop. Typical Application Circuit Note : Using all Ceramic Capacitors VOUT L1 (uH) C OUT (uF) R1 (k Ω) R2 (k Ω) R COMP (kΩ) C COMP (nF) 3.3V 2.2 22 750 240 13 1 2.5V 2.2 22 510 240 13 1 1.8V 1.0 22 300 240 7.5 1.5 1.2V 1.0 22 120 240 7.5 1.5 Recommended Component for Different Output Voltage Applications
6 VDD
2.6V to 5.5V
4 PGND
GND 2, Exposed Pad (9) ROSC 332k CIN 22uF 2.2uH 510k 240k COUT 22uFRCOMP 13k CCOMP 1nF VOUT 2.5V/2A
DS8015-03 March 2011 www.richtek.com Function Block Diagram Driver NISEN Control Logic NMOS I Limit 0.9V 0.7V 0.4V OC Limit ISEN Slope ComOSC Output ClampEA 0.8V Int-SS POR OTPVREF COMP SHDN/RT GND FB PVDD VDD PGND SD LX
DS8015-03 March 2011www.richtek.com Operation Main Control Loop The RT8015 is a monolithic, constant-frequency, current mode step-down DC/DC converter. During normal operation, the internal top power switch (P-Channel MOSFET) is turned on at the beginning of each clock cycle. Current in the inductor increases until the peak inductor current reach the value defined by the voltage on the COMP pin. The error amplifier adjusts the voltage on the COMP pin by comparing the feedback signal from a resistor divider on the FB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference. The error amplifier raises the COMP voltage until the average inductor current matches the new load current. When the top power MOSFET shuts off, the synchronous power switch (N-Channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. The operating frequency is set by an external resistor connected between the RT pin and ground. The practical switching frequency can range from 300kHz to 2MHz. Power Good comparators will pull the PGOOD output low if the output voltage comes out of regulation by 12.5%. In an over-voltage condition, the top power MOSFET is turned off and the bottom power MOSFET is switched on until either the over-voltage condition clears or the bottom MOSFET's current limit is reached. Frequency Synchronization The internal oscillator of the RT8011 can be synchronized to an external clock connected to the SYNC pin. The frequency of the external clock can be in the range of 300kHz to 2MHz. For this application, the oscillator timing resistor should be chosen to correspond to a frequency that is about 20% lower than the synchronization frequency. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the internal P-Channel MOSFET and the inductor. Low Supply Operation The RT8015 is designed to operate down to an input supply voltage of 2.6V. One important consideration at low input supply voltages is that the RDS(ON) of the P-Channel and N-Channel power switches increases. The user should calculate the power dissipation when the RT8015 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8015, however, separated inductor current signals are used to monitor over current condition. This keeps the maximum output current relatively constant regardless of duty cycle. Short Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring.
DS8015-03 March 2011 www.richtek.com Absolute Maximum Ratings (Note 1) l Power Dissipation, PD @ TA = 25°C l Package Thermal Resistance (Note 2) l ESD Susceptibility (Note 3)
Electrical Characteristics
(VDD = 3.3V, T A = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range VDD 2.6 -- 5.5 V Feedback Reference Voltage VREF 0.784 0.8 0.816 V Active , VFB = 0.78V, Not Switching -- 460 -- µA DC Bias Current Shutdown -- -- 1 µA Output Voltage Line Regulation VIN = 2.7V to 5.5V -- 0.04 -- %/V Output Voltage Load Regulation 0A < ILOAD < 2A -- 0.25 -- % Error Amplifier Transconductance gm -- 800 -- us Current Sense Transresistance RT -- 0.4 -- Ω Power Good Range -- ±12.5 ±15 % Power Good Pull-Down Resistance -- -- 120 Ω ROSC = 332k 0.8 1 1.2 MHz Switching Frequency Switching Frequency 0.3 -- 2 MHz Sync Frequency Range 0.3 -- 2 MHz To be continued Recommended Operating Conditions (Note 4)
DS8015-03 March 2011www.richtek.com Note 1. Stresses listed as the above “Absolute Maximum Ratings ” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at T A = 25 °C on 4-layers high effective thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit Switch On Resistance, High RPMOS ISW = 0.5A -- 110 160 mΩ Switch On Resistance, Low RNMOS ISW = 0.5A -- 110 170 mΩ Peak Current Limit ILIM 2.2 3.2 -- A VDD Rising -- 2.4 -- V Under Voltage Lockout Threshold VDD Falling -- 2.3 -- V Shutdown Threshold VSHDN/RT -- VIN − 0.7 VIN − 0.4 V
DS8015-03 March 2011 www.richtek.com Frequency vs. Temperature 1000 1020 1040 1060 1080 1100 -50 -25 0 25 50 75 100 125 Temperature Frequency (kHz) (°C) VIN = 3.3V, V OUT = 1.8V IOUT = 0A Quiescent Current vs. Input Voltage 450 470 490 510 530 550 Input Voltage (V) Quiescent Current (uA) Quiescent Current vs. Temperature 400 420 440 460 480 500 -50 -25 0 25 50 75 100 125 Temperature Quiescent Current (uA) (°C) VIN = 3.3V Peak Current Limited vs. Input Voltage 2.0 2.5 3.0 3.5 4.0 Input Voltage (V) Peak Current Limited (A) VOUT = 2.5V Typical Operating Characteristics Output Voltage vs. Output Current 1.790 1.792 1.794 1.796 1.798 1.800 1.802 1.804 1.806 1.808 1.810 0 250 500 750 1000 1250 15001750 2000 Output Current (mA) Output Voltage (V) VIN = 3.3V Efficiency vs. Output Current 100 0 250 500 750 100012501500 17502000 Output Current (mA) Efficiency (%) VIN = 3.3V, V OUT = 1.8V VIN = 5V, V OUT = 1.8V
DS8015-03 March 2011www.richtek.com VREF vs. Input Voltage 0.800 0.801 0.802 0.803 0.804 0.805 Input Voltage (V) VREF (V) Output Ripple Time (250ns/Div) ILX (2A/Div) VOUT (10mV/Div) VIN = 5V, VOUT = 2.5V IOUT = 2A VLX (5V/Div) Output Ripple Time (250ns/Div) ILX (2A/Div) VOUT (10mV/Div) VIN = 3.3V, VOUT = 2.5V IOUT = 2A VLX (5V/Div) Load Transient Response Time (50 μs/Div) ILX (1A/Div) VOUT (50mV/Div) VIN = 3.3V, VOUT = 2.5V IOUT = 1A to 2A Load Transient Response Time (50 μs/Div) ILX (1A/Div) VOUT (50mV/Div) VIN = 3.3V, VOUT = 2.5V IOUT = 0A to 2A Output Voltage vs. Temperature 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 -50 -25 0 25 50 75 100 125 Temperature Output Voltage (V) (°C) VIN = 3.3V
DS8015-03 March 2011 www.richtek.com Soft Start and Inrush Current Time (2.5ms/Div) IIN (2A/Div) VLX (5V/Div) VIN = 5V, VOUT = 2.5V IOUT = 2A VOUT (2V/Div) VIN (2V/Div) Soft Start and Inrush Current Time (2.5ms/Div) IIN (2A/Div) VLX (5V/Div) VIN = 3.3V, VOUT = 2.5V IOUT = 2A VOUT (2V/Div) VIN (2V/Div) Power On & Inductor Current Time (1ms/Div) ILX (2A/Div) VLX (5V/Div) VIN = 3.3V, VOUT = 2.5V IOUT = 2A VOUT (2V/Div) VIN (2V/Div) Power Good Time (1ms/Div) ILX (2A/Div) VOUT (2V/Div) VIN = 3.3V, VOUT = 2.5V IOUT = 2A PGOOD (2V/Div) VIN (2V/Div) Power On & Inductor Current Time (1ms/Div) ILX (2A/Div) VLX (5V/Div) VIN = 5V, VOUT = 2.5V IOUT = 2A VOUT (2V/Div) VIN (2V/Div)
DS8015-03 March 2011www.richtek.com
Application Information
The basic RT8015 application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. The operating frequency of the RT8015 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. The RT resistor value can be determined by examining the frequency vs. RT curve. Although frequencies as high as 4MHz are possible, the minimum on-time of the RT8015 imposes a minimum limit on the operating duty cycle. The minimum on-time is typically 110ns. Therefore, the minimum duty cycle is equal to 100 x 110ns x f(Hz). Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the ripple current. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. Having a lower ripple current reduces the ESR losses in the output capacitors and the output voltage ripple. Highest efficiency operation is achieved at low frequency with small ripple current. This, however, requires a large inductor. A reasonable starting point for selecting the ripple current is ΔI = 0.4(IMAX). The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : − ×=Δ IN OUTOUTL V V1Lf VI − Δ×= IN(MAX) OUT L(MAX) OUT V V1If VL Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or mollypermalloy cores. Actual core loss is independent of core size for a fixed inductor value but it is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This result in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! The transition from low current operation begins when the peak inductor current falls below the minimum peak current. Lower inductor values result in higher ripple current which causes this to occur at lower load currents. This causes a dip in efficiency in the upper range of low current operation. Figure 1 0.5 1.5 2.5 3.5 4.5 0 100200300400500600700800900100 RRT (k ) Frequency (MHz) RRT (kΩ ) 1000 RT = 154k for 2MHz RT = 332k for 1MHz
Figure 2. Setting the Output Voltage where VREF equals to 0.8V typical. of the output voltage as shown in Figure 2. height requirements in the design. the load transient response as described in a later section. high voltage coefficient and audible piezoelectric effects. can also lead to significant ringing. any radiated field/EMI requirements.
DS8015-03 March 2011www.richtek.com Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as : Efficiency = 100% − (L1+ L2+ L3+ ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: VDD quiescent current and I2R losses. The VDD quiescent current loss dominates the efficiency loss at very low load currents whereas the I 2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence. 1. The VDD quiescent current is due to two components : the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge ΔQ moves from VDD to ground. The resulting ΔQ/Δt is the current out of VDD that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT+QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VDD and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW and external inductor RL. In continuous mode the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (D) as follows : RSW = RDS(ON)TOP x D + RDS(ON)BOT x (1"D) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including C IN and C OUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD(ESR), where ESR is the effective series resistance of C OUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem. The COMP pin external components and output capacitor shown in Typical Application Circuit will provide adequate compensation for most applications. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junctions to ambient. The maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) − TA ) / θJA Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT8015, where T J(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance for SOP-8 (Exposed Pad) package is 75°C/W on the standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The copper thickness is 2oz. The maximum power dissipation at T A = 25 °C can be calculated by following formula: PD (MAX) = (125°C − 25°C) / (75°C/W) = 1.33W (SOP-8 Exposed Pad on the minimum layout)
Table 1. Recommended Inductor Table 2. Recommended Capacitor Follow the PCB layout guidelines for optimal performance of RT8015. to the IC. The exposed pad should be connected to GND. AC current into the internal power MOSFETs. away from LX node to prevent stray capacitive noise pick-up. resistor divider must be connected between V OUT and GND.
DS8015-03 March 2011 www.richtek.com Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com Outline Dimension A BJ F H M C D I Y X EXPOSED THERMAL PAD (Bottom of Package) 8-Lead SOP (Exposed Pad) Plastic Package Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Option 1 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Option 2 Y 3.000 3.500 0.118 0.138