RT8055B RICHTEK | Alldatasheet

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Technical content

Features

zzzzz High Efficiency : Up to 95% zzzzz Low RDS(ON) Internal Switches : 100mΩΩΩΩΩ zzzzz Programmable Frequency : 300kHz to 2MHz zzzzz No Schottky Diode Required zzzzz 0.8V Reference Voltage Allows for Low Output Voltage zzzzz Forced Continuous Mode Operation zzzzz 100% Duty Cycle Operation zzzzz Input Over Voltage Protection zzzzz Power Good Output Voltage Indicutor zzzzz RoHS Compliant and Halogen Free General Description The RT8055B is a high efficiency synchronous, step-down DC/DC converter. Its input voltage range is from 2.6V to 5.5V and provides an adjustable regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. The internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an external Schottky diode. The switching frequency is set by an external resistor. The 100% duty cycle provides low dropout operation extending battery life in portable systems. Current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. The RT8055B is operated in forced continuous PWM Mode which minimizes ripple voltage and reduces the noise and RF interference. The RT8055B is available in the WDFN-10L 3x3 package.

Ordering Information

(TOP VIEW) WDFN-10L 3x3 3A, 2MHz, Synchronous Step-Down Converter Note : Richtek products are : \ RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. \ Suitable for use in SnPb or Pb-free soldering processes.

Applications

z Battery-Powered Equipment z Notebook Computers z Distributed Power Systems z IP Phones z Digital Cameras z 3G/3.5G Data Card SHDN/RT GND PGND LX COMP FB PGOOD PVDD VDD LX GND Marking Information K3= : Product Code YMDNN : Date CodeK3=YM DNN RT8055B Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free)

1 SHDN/RT

3, 4 LX Internal Power MOSFET Switches Output. Connect this pin to the inductor. 5 PGND Power Ground. Connect this pin close to the negative terminal of C IN and COUT. 6 PVDD Power Supply Input. Decouple this pin to PGND with a capacitor. 8 PGOOD Power Good Indicator. The pin is an open drain logic output that is pulled to Ground. connected across the output.

10 COMP

Table 1. Recommended Component Selsction

DS8055B-03 April 2011 www.richtek.com Function Block Diagram Driver Control Logic 0.9V OC Limit ISEN Slope Comp.OSC Output ClampEA0.8V Internal Soft-Star POR GND FB PVDD VDD PGND LX OTP VREF SD NISEN N-MOSFET ILIM 0.7V 0.4V SHDN/RT COMP PGOOD

DS8055B-03 April 2011www.richtek.com Absolute Maximum Ratings (Note 1) z Power Dissipation, PD @ TA = 25°C z Package Thermal Resistance (Note 2) z ESD Susceptibility (Note 3)

Electrical Characteristics

(VDD = 3.3V, T A = 25°C, unless otherwise specified) To be continued Recommended Operating Conditions (Note 4) Parameter Symbol Test Conditions Min Typ Max Unit Input Voltage Range V DD 2.6 -- 5.5 V Feedback Reference Voltage V REF 0.784 0.8 0.816 V Feedback Leakage Current I FB V FB = 3.3V -- -- 0.1 μA Active, V FB = 0.7V, Not Switching -- 500 -- μA DC Bias Current Shutdown -- -- 1 μA Output Voltage Line Regulation ΔVLINE V IN = 2.6V to 5.5V -- 0.1 -- %/V Output Voltage Load Regulation ΔVLOAD VIN = 5V, VOUT = 3.3V, IOUT = 0A to 3A -- 0.4 -- % Error Amplifier Transconductance gm -- 400 -- μA/V Current Sense Transresistance R S -- 0.4 -- Ω RT Leakage Current SHDN/RT = V IN = 5.5V -- -- 1 μA ROSC = 180kΩ 1.44 1.8 2.16 MHz Switching Frequency Adjustable Switching Frequency Range 0.3 -- 2 MHz Switch On Resistance, High RDS(ON)_P I SW = 0.3A -- 100 160 m Ω Switch On Resistance, Low R DS(ON)_N I SW = 0.3A -- 100 170 m Ω

DS8055B-03 April 2011 www.richtek.com Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θ JA is measured in the natural convection at T A = 25°C on a high effective thermal conductivity four layers test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the exposed pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit Peak Current Limit I LIM 3.5 -- -- A V DD Rising -- 2.4 -- V Under Voltage Lockout Threshold V DD Falling -- 2.2 -- V Shutdown Threshold V SHDN V SHDN Rising -- V IN − 0.85 V IN − 0.4 V Power Good (PGOOD) V OUT Falling (Fault) -- 87 -- %V OU T V OUT Rising (Good) -- 90 -- %V OU T V OUT Rising (Fault) -- 114 -- %V OU T Power Good Threshold V OUT Falling (Good) -- 111 -- %V OU T

DS8055B-03 April 2011www.richtek.com Typical Operating Characteristics Output Voltage vs. Input Voltage 3.30 3.31 3.32 3.33 3.34 3.35 3.36 Input Voltage (V) Output Voltage (V) IOUT = 0A, VOUT = 3.3V Efficiency vs. Output Current 100 Output Current (A) Efficiency (%) VIN = 5V, VOUT = 3.3V Switching Frequency vs. Temperature 1.5 1.6 1.7 1.8 1.9 2.0 2.1 -50 -25 0 25 50 75 100 125 Temperature (°C) Switching Frequency (MHz) 1 VIN = 5V, VOUT = 3.3V IOUT = 0.3A, fSW = 1.8MHz VIN UVLO vs. Temperature 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 -50 -25 0 25 50 75 100 125 Temperature (°C) VIN UVLO (V) Rising Falling VOUT = 3.3V Output Voltage vs. Output Current 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 Output Current (A) Output Voltage (V) VIN = 5V, VOUT = 3.3V Switching Frequency vs. Input Voltage 1.5 1.6 1.7 1.8 1.9 2.0 2.1 Input Voltage (V) Switching Frequency (MHz) 1 VIN = 5V, VOUT = 3.3V IOUT = 0.3A, fSW = 1.8MHz

DS8055B-03 April 2011 www.richtek.com Output Ripple Time (500ns/Div) VIN = 5V, VOUT = 3.3V IOUT = 3A VLX (5V/Div) VOUT (5mV/Div) Reference Voltage vs. Temperature 0.760 0.768 0.776 0.784 0.792 0.800 0.808 0.816 0.824 0.832 0.840 -50 -25 0 25 50 75 100 125 Temperature (°C) Reference Voltage (V) Output Current Limit vs. Temperature 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Current Limit (A) VIN = 5V, VOUT = 3.3V Output Ripple Time (500ns/Div) VIN = 5V, VOUT = 3.3V IOUT = 0A VLX (5V/Div) VOUT (5mV/Div) Output Voltage vs. Temperature 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 -50 -25 0 25 50 75 100 125 Temperature (°C) Output Voltage (V) VIN = 5V, VOUT = 3.3V IOUT = 0A Output Current Limit vs. Input Voltage 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Voltage (V) Output Current Limit (A) VOUT = 3.3V

DS8055B-03 April 2011www.richtek.com Load Transient Response Time (100 μs/Div) IOUT (1A/Div) VOUT (200mV/Div) VIN = 5V, VOUT = 3.3V IOUT = 0A to 2A Load Transient Response Time (100 μs/Div) IOUT (1A/Div) VOUT (200mV/Div) VIN = 5V, VOUT = 3.3V IOUT = 0A to 3A Power On from V IN Time (1ms/Div) VIN = 5V, VOUT = 3.3V VIN (2V/Div) PGOOD (2V/Div) VOUT (2V/Div)

DS8055B-03 April 2011www.richtek.com This formula has a maximum at V IN = 2V OUT, where IRMS = I OUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of C OUT is determined by the Effective Series Resistance (ESR) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔV OUT, is determined by : ⎡ +Δ≤Δ OUT LOUT 8fC 1ESRIV Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. It is accomplished internally by adding a compensating ramp to the inductor current signal. Normally, the maximum inductor peak current is reduced when slope compensation is added. In the RT8055B, however, separated inductor current signals are used to monitor over current condition. This keeps the maximum output current relatively constant regardless of duty cycle. Short Circuit Protection When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. A current runaway detector is used to monitor inductor current. As current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔI L increases with higher VIN and decreases with higher inductance. OUT OUTL IN VVI = 1 fL V OUT OUT L(MAX) IN(MAX) VVL = 1fI V Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. However, it requires a large inductor to achieve this goal. For the ripple current selection, the val ue of ΔIL = 0.4(IMAX) will be a reasonable starting point. The large st ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : The inductor's current rating (caused a 40°C temperature rising from 25 °C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. The output ripple is highest at maximum input voltage since ΔI L increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by : OUT INRMS OUT(MAX) IN OUT V VII 1 VV=−

and temperature difference between junction to ambient. the junction to ambient thermal resistance. to ambient thermal resistance θJA is layout dependent. Figure 3. Derating Curves for RT8055B Package \` Flood all unused areas on all layers with copper. \` Connect the FB pin directly to the feedback resistors.

Table 2. Inductors Table 3. Capacitors for CIN and COUT Figure 4. PCB Layout Guide

DS8055B-03 April 2011 www.richtek.com Richtek Technology Corporation Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property inf ringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications i s assumed by Richtek. Richtek Technology Corporation Taipei Office (Marketing) 5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)86672399 Fax: (8862)86672377 Email: marketing@richtek.com Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.1 16 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.1 16 0.120 E2 1.500 1.750 0.059 0.069 e 0.500 0.020 L 0.350 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options D E A L be SEE DETAIL A