BAS316 | DigiCamel IC Datasheet

Online Datasheet

Read BAS316 online.

RTQ2079-QF RICHTEK | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 83

Technical content

Copyright © 202 4 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Functional Safety PMIC for Automotive Camera Sensors/ Modules

1 General Description

The RTQ2079-QF is a highly integrated PMIC designed for automotive camera applications. It includes three step-down converters, one high PSRR low-dropout (LDO) regulator , and one general low-dropout ( LDO) regulator. The high-voltage step-down converter operates with an input voltage range of up to 24V and is capable of sustaining a 36V load dump. It is suitable for a direct connection to a 12V battery or Power Over Coax ial (PoC) connection. The RTQ2079-QF offers overvoltage and undervoltage monitors, two error input receiver s, one error output indicator, and fault status report ed by I 2C for system fault reporting purpose. The device o ffers system design flexibility with I 2C or factory-trimmed configurable functions, including adjustable output voltage for each channel, customizable power -on sequencing, and overvoltage (OV) or undervoltage ( UV) monitor threshold voltage. The RTQ2079-QF is available in a WET-WQFN-24AL 4x4 package with wettable flanks. The recommended junction temperature range is −40C to 125C, and the ambient temperature range is −40C to 125C.

2 Applications

⚫ Function Safety Related Automotive Camera Modules ⚫ Surround View Cameras ⚫ Front View Cameras ⚫ Rear View Cameras ⚫ Dash Cams ⚫ Driver Monitoring Systems ⚫ Cabin Monitors ⚫ eMirrors

3 Features

⚫ AEC-Q100 Grade 1 Qualified ⚫ Compliance with ISO 26262 ASIL B ⚫ Power-On Built-In Self-Test (BIST) for OV/UV Monitors, I2C Cyclic Redundancy Check (CRC), and OTP Register CRC Protection ⚫ Three Step-Down Converters (HVBuck1, LVBuck2, and LVBuck3) with Peak-Current Mode PWM Operation and PSM Mode for Sentry Mode via I2C Setting ⚫ Fixed Switching Frequency at 2.1MHz ⚫ EMI Reduction Features including Spread Spectrum and Phase-Shift Operation ⚫ HVBuck1 Supports Input Voltage from 4V to 24V with Load Dump Protection (36V for  400ms Transient), Adjustable Output Voltage, and up to 1.5A Output Current ⚫ LVBuck2 and LVBuck3 Support Input Voltage from 2.7V to 5V, Adjustable Output Voltage, and up to 1.5A Output Current ⚫ Pins Related to LVBuck2/LVBuck3 Can Float if the Channel is Unused ⚫ Two Low-Dropout Regulators (LDO1 and LDO2) ⚫ LDO1 with 2.7V to 5V Input Voltage, Adjustable Output Voltage, up to 0.3A Output Current, and High PSRR with 0.1A Output Current (60dB at 100kHz, 40dB at 1MHz) ⚫ LDO2 with 2.7V to 5V Input Voltage, Adjustable Output Voltage, and up to 0.4A Output Current ⚫ Input and Output Functions ⚫ Sequence Control for External IC via SEQOUT ⚫ Power Status Indication via PGOOD ⚫ Error Status Indication via ERROUT ⚫ Two Error Signal Receivers via ERRIN1/ERRIN2 ⚫ External Voltage Monitor via VMONIN ⚫ Small Form Factor ⚫ Wettable WET-WQFN-24AL 4x4 Package with Compact BOM ⚫ Junction Temperature Range: −40C to 125C ⚫ Ambient Temperature Range: −40C to 125C

4 Ordering Information

QF: AEC-Q100 and ISO 26262 Qu alified, Screened by High Temperature Package Type (2) N: WET-WQFN-24AL 4x4 (W-Type) Trim Code(1) -QF Package Code T: Wettable Packing A: Standard Note 1. ⚫ Marked with (1) indicated: The trim code for UVLO, POWER_ON_SEQ, ON_Td, OFF_Td + UV_SD , HVBUCK1 VOUT, LVBUCK2 VOUT, LVBUCK3 VOUT, LDO1 VOUT, and LDO 2 VOUT settings has various combinations. For more details, contact our sales representative directly or through a Richtek distributor in your area. ⚫ Richtek products are Richtek Green Policy compliant and marked with (2) indicates compatible with the current requirements of IPC/JEDEC J-STD-020.

5 Marking Information

For marking information, contact our sales representative directly or through a Richtek distributor located in your area.

6 Simplified Application Circuit

VOUT_HV1 AGND BOOT CP1, CP2, CP3, CP4, PGND VOUT_LV2 SDA SCL VOUT1 RESETIN ERROUT VOUT5 ERRIN1 EN C3C4 C6 C7 L2 L3 ERRIN2 VMONIN PGOOD C10 VOUT_HV1 VOUT_LDO1 VOUT_LDO2 VOUT_LV3 VOUT_LV3 SEQOUT PGOOD ERROUT SCL SDA RESET ERRIN1 ERRIN2 VMON EN R1 R2 R3 RTQ2079-QF

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table of Contents 15.3 General CIS Application for Battery Input ... 24

17.1 System Undervoltage and

18.5 Power Sequence and Interval Time Setting 38

18.9 External Error Monitoring

7 Pin Configuration

(TOP VIEW) VOUT5 VOUT4 PVCC VMONIN RESETIN PVD45 SCL SDA ERRIN1 ERRIN2 PGOOD ERROUT VOUT1 AGND EN VIN SW1 BOOT SW3 SEQOUT VOUT2 SW2 PVD23 VOUT3 7 8 9 10 1211 21 20 1924 2223 PGND CP1 CP2 CP3 CP4CP1 CP2 CP3 CP4 WET-WQFN-24AL 4x4

8 Functional Pin Description

Pin No. Pin Name Pin Function 1 VOUT1 HVBuck1 output voltage feedback. It is recommended to directly connect the output capacitor node to this pin for better regulation. 2 AGND Analog ground for the PMIC analog circuit. 3 EN Chip hardware enable input pin. When the EN = High, the I2C read/write function is enabled. 4 VIN HVBuck1 and PMIC system input source power. 5 SW1 HVBuck1 switch node. 6 BOOT HVBuck1 BOOT pin. 7 VOUT2 LVBuck2 output voltage feedback. It is recommended to d irectly connect the output capacitor node to this pin for better regulation. 8 SW2 LVBuck2 switch node. 9 PVD23 LVBuck2/3 input source power. Assume that PVD23 connects to the HVbuck1 output. 10 SW3 LVBuck3 switch node. 11 VOUT3 LVBuck3 output voltage feedback. It is recommended to directly connect the output capacitor node to this pin for better regulation. 12 SEQOUT Open-drain output. Use this pin to enable an external device for the desired system ON/OFF sequence. 13 ERROUT Open-drain output. ERROUT changes the output status until the PMIC detects faults for indication. 14 PGOOD Open-drain output, PMIC power status for indication. When PGOOD is in a high state, it indicates that all outputs are functioning normally. 15 ERRIN2 Error input monitor 2 for external system fault detection. This pin can be set to active high or active low by register.

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Pin No. Pin Name Pin Function 16 ERRIN1 Error input monitor 1 for external system fault detection. This pin can be set to active high or active low by register. 17 SDA I2C interface serial d ata pin , open-drain. Connect to an external pull -up resistor is required. 18 SCL I2C interface serial clock input pin, open-drain. Connect to an external pull- up resistor is required. 19 VOUT4 LDO1 output pin . It is recommended to directly connect the output capacitor node to this pin for better regulation. 20 PVD45 LDO1/2 input source power. Assume that PVD45 connects to the HVbuck1 output. 21 VOUT5 LDO2 output pin . It is recommended to directly connect the output capacitor node to this pin for better regulation. 22 RESETIN Chip external reset input pin. 23 VMONIN Built-in OV/UV voltage monitor for external voltage detection.

24 PVCC

Internal analog power output. Connect a 1F ceramic decoupling capacitor between this pin and ground. Additional external loading to this pin is forbidden. (Exposed Pad) PGND IC thermal pad and power ground. It must be connected to the main ground plane for proper operation. CP1 CP1 Corner Pins for package reliability improvement. There pins are i nternally connected to the Exposed Pad. CP2 CP2 CP3 CP3 CP4 CP4

9 Functional Block Diagram

VREF1, IBIAS1, OSC1, TSD BOOT Pre-Regulator1 LVBuck2 Driver Control LDO1 Driver Control HVBuck1 Driver Control LVBuck3 Driver Control PGOOD/SEQOUT Control Control Logic PVD23 POR/ UVLO VIN Pre-Regulator2 Output, OVP, UVP VREF2, IBIAS2, OSC2 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 SEQOUT LDO2 Driver Control PVD45 VOUT5 BIST FSS ERROUT Control ERROUT ERRIN Monitor ERRIN1 ERRIN2 VMONIN I2C Control SCL SDA AGND EN, RESET Monitor EN RESETIN PGND VMONIN OVP, UVP CP1, CP2, CP3, CP4

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com (Note 2) ⚫ VOUT1, VOUT2, SW2, PVD23, SW3, VOUT3, SEQOUT, ERROUT, PGOOD, Note 2. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

11 ESD Rating

(Note 3) ⚫ ESD Susceptibility Note 3. Devices are ESD sensitive. Handling precautions are recommended.

12 Recommended Operating Conditions

(Note 4) Note 4. The device is not guaranteed to function outside its operating conditions.

13 Thermal Information

(Note 5) Thermal Parameter WET-WQFN-24AL 4x4 Unit JA Junction-to-ambient thermal resistance (JEDEC standard) 37 C/W JC(Top) Junction-to-case (top) thermal resistance 34.8 C/W JC(Bottom) Junction-to-case (bottom) thermal resistance 0.48 C/W JB Junction-to-board thermal resistance 9.72 C/W Note 5. For more information about thermal parameter, see the Application and Definition of Thermal Resistances report, AN061.

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 unless otherwise specified.) Parameter Symbol Test Conditions Min Typ Max Unit System Shutdown Current of VIN ISHUTDOWN EN = L, VIN  12V, VOUT_HV1 ties to PVD23 and PVD45 0 -- 10 A VIN Undervoltage Lockout Falling VUVLO_F 3.1 3.3 3.465 V 3.56 3.8 3.99 4.085 4.3 4.515 6.46 6.8 7.14 VIN Undervoltage Lockout Rising VUVLO_R 3.55 3.8 3.99 V 4.23 4.5 4.725 4.71 5 5.25 6.935 7.3 7.665 VIN Overvoltage Rising Threshold VOVP_R_VIN 24.735 25.5 26.265 V VIN Overvoltage Hysteresis VOVP_HYS_VIN 5 6 7 V Pre-Regulator (Note 6) PVCC Voltage Range VPVCC 4.26 4.58 4.92 V CH1_HVBuck1 Input Voltage Range VIN_HV1 VIN_HV1 = VIN 4 -- 24 V Output Voltage Range VOUT_HV1 VIN_HV1 = 4V to 24V 2.7 -- 5 V Output Voltage Accuracy VOUT_ACC_HV1_FPWM VOUT_HV1 = 2.7V to 5V, VIN_HV1 = 6V, 9V, 12V, IOUT_HV1 = 0 to 1.5A, FPWM −1.5 -- 1.5 % Soft-Start Time tSS_HV1 Time for V OUT_HV1 to rise from 10% to 90% of the target value, no load 500 1000 1500 s Switching Frequency fSW_HV1 1.89 2.1 2.31 MHz Spread Spectrum Range fSSP_HV1 -- 12 -- % High-Side MOSFET On- Resistance RON_UG_HV1 -- 220 -- m Low-Side MOSFET On- Resistance RON_LG_HV1 -- 120 -- m Minimum On- Time tMIN_ON_HV1 -- -- 40 ns

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Minimum Off- Time tMIN_OFF_HV1 -- -- 50 ns Positive Inductor Peak Current Limit ICL_PK_HV1 1.9 2.5 3.1 A Positive Inductor Valley Current Limit ICL_VALLEY_HV1 -- 1.6 -- A Negative Inductor Peak Current Limit ICL_N_PK_HV1 HVBuck1 in FPWM 1.3 1.8 2.3 A Output Discharge Resistor RDIS_HV1 20 50 80  HVBuck1 Output Undervoltage Falling Threshold Detection VUVP_HV1 -- 80 -- % HVBuck1 Output Undervoltage Falling Threshold Detection Accuracy VUVP_ACC_HV1 −1.3 -- 1.3 % HVBuck1 Output Overvoltage Rising Threshold Detection VOVP_HV1 -- 110 -- % HVBuck1 Output Overvoltage Rising Threshold Detection Accuracy VOVP_ACC_HV1 −1.3 -- 1.3 % CH2_LVBuck2 Input Voltage Range VIN_LV2 2.7 -- 5 V Output Voltage Range VOUT_LV2 0.6 1.1 1.9 V Output Voltage Accuracy VOUT_ACC_LV2_FPWM VOUT_LV2 = 0.6V to 1.9V, VIN_LV2 = 3.6V, IOUT_LV2 = 0A to 1.5A, FPWM −1.5 -- 1.5 % Soft-Start Time tSS_LV2 Time for VOUT_LV2 to rise from 10% to 90% of the target value, no load 600 1200 1800 s Switching Frequency fSW_LV2 1.89 2.1 2.31 MHz Spread Spectrum Range fSSP_LV2 -- 12 -- %

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Parameter Symbol Test Conditions Min Typ Max Unit High-Side MOSFET On- Resistance RON_UG_LV2 -- 90 -- m Low-Side MOSFET On- Resistance RON_LG_LV2 -- 35 -- m Minimum On- Time tMIN_ON_LV2 -- -- 44 ns Positive Inductor Peak Current Limit ICL_PK_LV2 2.1 2.5 2.9 A Positive Inductor Valley Current Limit ICL_VALLEY_LV2 -- 1.8 -- A Negative Inductor Peak Current Limit ICL_N_PK_LV2 LVBuck2 in FPWM 0.7 1.7 2.9 A Output Discharge Resistor RDIS_LV2 6 9 14  LVBuck2 Output Undervoltage Falling Threshold Detection VUVP_LV2 -- 95 -- % LVBuck2 Output Undervoltage Falling Threshold Detection Accuracy VUVP_ACC_LV2 −1.3 -- 1.3 % LVBuck2 Output Overvoltage Rising Threshold Detection VOVP_LV2 -- 105 -- % LVBuck2 Output Overvoltage Rising Threshold Detection Accuracy VOVP_ACC_LV2 −1.3 -- 1.3 % PVD23 Overvoltage Rising Protection VOVP_PVD23 5.35 5.8 6.25 V PVD23 Overvoltage Hysteresis VOVP_HYS_PVD23 -- 580 -- mV CH3_LVBuck3 Input Voltage Range VIN_LV3 2.7 -- 5 V Output Voltage Range VOUT_LV3 0.6 1.8 1.9 V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Output Voltage Accuracy VOUT_ACC_LV3_FPWM VOUT_LV3 = 0.6V to 1.9V, VIN_LV3 = 3.6V, IOUT_LV3 = 0A to 1.5A, FPWM −1.5 -- 1.5 % Soft-Start Time tSS_LV3 Time for VOUT_LV3 to rise from 10% to 90% of the target value, no load 600 1200 1800 s Switching Frequency fSW_LV3 1.89 2.1 2.31 MHz Spread Spectrum Range fSSP_LV3 -- 12 -- % High-Side MOSFET On- Resistance RON_UG_LV3 -- 90 -- m Low-Side MOSFET On- Resistance RON_LG_LV3 -- 42 -- m Minimum On- Time tMIN_ON_LV3 -- -- 44 ns Positive Inductor Peak Current Limit ICL_PK_LV3 2.1 2.5 2.9 A Positive Inductor Valley Current Limit ICL_VALLEY_LV3 -- 1.8 -- A Negative Inductor Peak Current Limit ICL_N_PK_LV3 LVBuck3 in FPWM 0.7 1.7 2.9 A Output Discharge Resistor RDIS_LV3 6 9 14  LVBuck3 Output Undervoltage Falling Threshold Detection VUVP_LV3 -- 95 -- % LVBuck3 Output Undervoltage Falling Threshold Detection Accuracy VUVP_ACC_LV3 −1.3 -- 1.3 % LVBuck3 Output Overvoltage Rising Threshold Detection VOVP_LV3 -- 105 -- % LVBuck3 Output Overvoltage Rising Threshold Detection Accuracy VOVP_ACC_LV3 −1.3 -- 1.3 %

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Parameter Symbol Test Conditions Min Typ Max Unit PVD23 Overvoltage Rising Protection VOVP_PVD23 5.35 5.8 6.25 V PVD23 Overvoltage Hysteresis VOVP_HYS_PVD23 -- 580 -- mV CH4_LDO1 Input Voltage Range VIN_LDO1 2.7 -- 5 V Output Voltage Range VOUT_LDO1 1.8 3.3 3.5 V Output Voltage Accuracy VOUT_ACC_LDO1 VOUT_LDO1 = 1.8V to 3.5V, (VIN_LDO1 - VOUT_LDO1)  0.3V, IOUT_LDO1 = 0mA to 300mA −1.5 -- 1.5 % Soft-Start Time tSS_LDO1 Time for VOUT_LDO1 to rise from 10% to 90% of target value, no load 200 700 1100 s Dropout Voltage (Note 7) VDROP_300_LDO1 IOUT_LDO1 = 300mA -- -- 300 mV VDROP_150_LDO1 IOUT_LDO1 = 150mA -- -- 150 Maximum Output Current IOUT_MAX_LDO1 300 -- -- mA Output Current Limit ICL_LDO1 345 450 555 mA Output Discharge Resistor RDIS_LDO1 32 60 88  LDO1 Output Undervoltage Falling Threshold Detection VUVP_LDO1 -- 95 -- % LDO1 Output Undervoltage Falling Threshold Detection Accuracy VUVP_ACC_LDO1 −1.3 -- 1.3 % LDO1 Output Overvoltage Rising Threshold Detection VOVP_LDO1 -- 105 -- % LDO1 Output Overvoltage Rising Threshold Detection Accuracy VOVP_ACC_LDO1 −1.3 -- 1.3 % PVD45 Overvoltage Rising Protection VOVP_PVD45 5.35 5.8 6.25 V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit PVD45 Overvoltage Hysteresis VOVP_HYS_PVD45 -- 500 -- mV CH5_LDO2 Input Voltage Range VIN_LDO2 2.7 -- 5 V Output Voltage Range VOUT_LDO2 1.8 1.8 3.3 V Output Voltage Accuracy VOUT_ACC_LDO2 VOUT_LDO2 = 1.8V to 3.5V, (VIN_LDO2 - VOUT_LDO2) ≥ 0.4V, IOUT_LDO2 = 0mA to 400mA −1.5 -- 1.5 % Soft-Start Time tSS_LDO2 Time for VOUT_LDO2 to rise from 10% to 90% of target value, no load 344 410 472 s Dropout Voltage (Note 7) VDROP_400_LDO2 IOUT_LDO2 = 400mA -- -- 400 mV VDROP_150_LDO2 IOUT_LDO2 = 150mA -- -- 150 Maximum Output Current IOUT_MAX_LDO2 400 -- -- mA Output Current Limit ICL_LDO2 450 600 750 mA Output Discharge Resistor RDIS_LDO2 32 60 88  LDO2 Output Undervoltage Falling Threshold Detection VUVP_LDO2 -- 95 -- % LDO2 Output Undervoltage Falling Threshold Detection Accuracy VUVP_ACC_LDO2 −1.3 -- 1.3 % LDO2 Output Overvoltage Rising Threshold Detection VOVP_LDO2 -- 105 -- % LDO2 Output Overvoltage Rising Threshold Detection Accuracy VOVP_ACC_LDO2 −1.3 -- 1.3 % PVD45 Overvoltage Rising Protection VOVP_PVD45 5.35 5.8 6.25 V PVD45 Overvoltage Hysteresis VOVP_HYS_PVD45 -- 500 -- mV

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Parameter Symbol Test Conditions Min Typ Max Unit I/O Control SEQOUT Low- Level Output Voltage VOL_SEQOUT The current into the SEQOUT pin is equal to 5mA -- -- 200 mV SEQOUT Input Leakage Current ILEAK_SEQOUT 1.8V is applied on the SEQOUT pin -- -- 1 A PGOOD Low- Level Output Voltage VOL_PGOOD The current into the PGOOD pin is equal to 5mA -- -- 200 mV PGOOD Input Leakage Current ILEAK_PGOOD 1.8V applied on the PGOOD pin -- -- 1 A PGOOD Delay Time tPGOOD_DLY Time interval between the completion of the soft-start process for the last channel and the subsequent assertion of the PGOOD signal 8.3 9.4 10.5 ms EN Low-Level Input Voltage VIL_EN -- -- 0.4 V EN High-Level Input Voltage VIH_EN 1.2 -- -- V EN Pull-Down Current IPD_EN 1 -- 11 A RESETIN Low- Level Input Voltage VIL_RESETIN -- -- 0.4 V RESETIN High- Level Input Voltage VIH_RESETIN 1.2 -- -- V RESETIN Pull- Down Resistance RPD_RESETIN -- 300 -- k Safety I/O Control ERROUT Low- Level Output Voltage VOL_ERROUT The current into ERROUT is equal to 5mA -- -- 200 mV ERROUT Input Leakage Current ILEAK_ERROUT 1.8V is applied on the ERROUT pin -- -- 1 A ERRIN1/2 Low- Level Input Voltage VIL_ERRIN1/2 -- -- 0.4 V ERRIN1/2 High- Level Input Voltage VIH_ERRIN1/2 1.2 -- -- V ERRIN1/2 Pull- Down Resistance RPD_ERRIN1/2 -- 300 -- k

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit VMONIN VMONIN Monitor High-Voltage Range VMONIN_H Default: 1.28V 0.938 0.96 0.982 V 1.162 1.18 1.198 1.261 1.28 1.299 1.31 1.33 1.35 VMONIN Monitor Low-Voltage Range VMONIN_L Default: 1.14V 0.821 0.84 0.859 V 1.005 1.02 1.035 1.123 1.14 1.157 1.075 1.09 1.106 Note 6. PVCC is the pre-regulator output voltage only for internal circuitry. External loading on the PVCC pin is forbidden. Note 7. Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below its nominal value.

14.1 System Characteristics

The following specifications are guaranteed by design and are not performed in production testing. (T A = TJ = −40C to 125C, Parameter Symbol Test Conditions Min Typ Max Unit System Quiescent Current of VIN IQ_ON EN = H, VUVLO_R  VIN  24V, VOUT_HV1 ties to PVD23 and PVD45, all channels are ON, no load -- 20 -- mA Quiescent Current of VIN IQ_OFF EN = H, VUVLO_R  VIN  24V, VOUT_HV1 ties to PVD23 and PVD45, all channels are OFF -- 3 -- mA Over- Temperature Protection TTSD -- 170 -- C Over- Temperature Protection Hysteresis TTSD_H -- 20 -- C Over- Temperature Warning TOTW -- 130 -- C Over- Temperature Warning Hysteresis TOTW_H -- 20 -- C CH1_HVBuck1 Maximum Output Current IOUT_MAX_HV1 Depends on the input voltage and the output voltage 1.5 -- -- A

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Parameter Symbol Test Conditions Min Typ Max Unit Load Transient VLOAD_TRAN_HV1_FPWM VOUT_HV1 = 3.6V, VIN_HV1 = 6V/9V/12V, IOUT_HV1 = 10mA to 0.5A to 10mA, 1s, FPWM −150 -- 150 mV Line Transient VLINE_TRAN_HV1_FPWM VOUT_HV1 = 3.6V, VIN_HV1 = 5V to 18.5V to 5V, 100s, IOUT_HV1 = 0.5A, FPWM −50 -- 50 mV Load Regulation VLOAD_REG_HV1 VOUT_HV1 = 3.6V, VIN_HV1 = 6V/9V/12V, IOUT_HV1 = 1.5A, FPWM -- -- 0.15 % Line Regulation VLINE_REG_HV1 VOUT_HV1 = 3.6V, VIN_HV1 = 5V to 18.5V, IOUT_HV1 = 1.5A -- -- 1 % Output Ripple Voltage VRIPPLE_HV1_FPWM Peak to peak in one switching cycle, FPWM, SSP_EN bit = 0 -- -- 20 mVpp CH2_LVBuck2 Maximum Output Current IOUT_MAX_LV2 1.5 -- -- A Load Transient VLOAD_TRAN_LV2_FPWM VOUT_LV2 = 1.1V, VIN_LV2 = 3.6V, IOUT_LV2 = 100mA to 0.5A to 100mA, 1s, FPWM −50 -- 50 mV Line Transient VLINE_TRAN_LV2_FPWM VOUT_LV2 = 1.1V, VIN_LV2 = 3V to 5V to 3V, 50s, IOUT_LV2 = 10mA/0.75A/1.5A, FPWM −50 -- 50 mV Load Regulation VLOAD_REG_LV2 VOUT_LV2 = 1.1V, VIN_LV2 = 3.6V, IOUT_LV2 = 1.5A, FPWM -- -- 0.15 % Line Regulation VLINE_REG_LV2 VOUT_LV2 = 1.1V, VIN_LV2 = 2.7V to 5V, IOUT_LV2 = 1.5A -- -- 1 % Output Ripple Voltage VRIPPLE_LV2_FPWM Peak to peak in one switching cycle, FPWM, SSP_EN bit = 0 -- 10 15 mVpp CH3_LVBuck3 Maximum Output Current IOUT_MAX_LV3 1.5 -- -- A Load Transient VLOAD_TRAN_LV3_FPWM VOUT_LV3 = 1.8V, VIN_LV3 = 3.6V, IOUT_LV3 = 100mA to 0.5A to 100mA, 1s, FPWM −50 -- 50 mV Line Transient VLINE_TRAN_LV3_FPWM VOUT_LV3 = 1.8V, VIN_LV3 = 3V to 5V to 3V, 50s, IOUT_LV3 = 10mA/0.75A/1.5A, FPWM −50 -- 50 mV

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Load Regulation VLOAD_REG_LV3 VOUT_LV3 = 1.8V, VIN_LV3 = 3.6V, IOUT_LV3 = 1.5A, FPWM -- -- 0.15 % Line Regulation VLINE_REG_LV3 VOUT_LV3 = 1.8V, VIN_LV3 = 2.7V to 5V, IOUT_LV3 = 1.5A -- -- 1 % Output Ripple Voltage VRIPPLE_LV3_FPWM Peak to peak in one switching cycle, FPWM, SSP_EN bit = 0 -- 10 15 mVpp CH4_LDO1 Power Supply Rejection Ratio PSRR_LDO1 VOUT_LDO1 = 3.3V, VIN_LDO1  3.6V, IOUT_LDO1 = 100mA, f = 100kHz Disturbing signal = 100mV -- 60 -- dB VOUT_LDO1 = 3.3V, VIN_LDO1  3.6V, IOUT_LDO1 = 100mA, f = 100kHz to 1MHz Disturbing signal = 100mV -- 40 -- dB Load Transient VLOAD_TRAN_LDO1 VOUT_LDO1 = 3.3V, VIN_LDO1 = 3.6V, IOUT_LDO1 = 10mA to 0.2A to 10mA, 1s, CO_LDO1 = 2.2F −25 -- 25 mV Line Transient VLINE_TRAN_LDO1 VOUT_LDO1 = 3.3V, VIN_LDO1 step 600mV, 10s, the LDO1 is not in dropout condition, IOUT_LDO1 = 1mA/ 0.3A −25 -- 25 mV CH5_LDO2 Power Supply Rejection Ratio PSRR_LDO2 VOUT_LDO2 = 3.3V, VIN_LDO2  3.7V, IOUT_LDO2 = 100mA, f = 100kHz Disturbing signal = 100mV -- 20 -- dB VOUT_LDO2 = 3.3V, VIN_LDO2  3.7V, IOUT_LDO2 = 100mA, f = 100kHz to 1MHz Disturbing signal = 100mV -- 15 -- dB Load Transient VLOAD_TRAN_LDO2 VOUT_LDO2 = 1.8V, VIN_LDO2 = 3.6V, IOUT_LDO2 = 10mA to 0.2A to 10mA, 1s, CO_LDO2 = 2.2F −50 -- 50 mV Line Transient VLINE_TRAN_LDO2 VOUT_LDO2 = 1.8V, VIN_LDO2 step 600mV, 10s, the LDO2 is not in dropout condition, IOUT_LDO2 = 1mA/ 0.4A −25 -- 25 mV

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Parameter Symbol Test Conditions Min Typ Max Unit I2C SCL, SDA High- Level Input Threshold Voltage VIH_I2C 1.2 -- -- V SCL, SDA Low- Level Input Threshold Voltage VIL_I2C -- -- 0.4 V SCL Clock Frequency fSCL -- -- 1000 kHz (Repeated) Start Hold Time tHD;STA Hold time (repeated) start condition. After this period, the first clock pulse is generated. 0.26 -- -- s SCL Clock Low Time tLOW 0.5 -- -- s SCL Clock High Time tHIGH 0.26 -- -- s (Repeated) Start Setup Time tSU;STA Set-up time for a repeated START condition 0.26 -- -- s SDA Data Hold Time tHD;DAT 0 -- -- ns SDA Set-Up Time tSU;DAT 50 -- -- ns STOP Condition Setup Time tSU;STO 0.26 -- -- s Bus Free Time between Stop and Start Condition tBUF 0.5 -- -- s Rising Time of Both SDA and SCL Signals tR -- -- 120 ns Falling Time of Both SDA and SCL Signals tF -- -- 120 ns SDA Output Low Sink Current IOL_I2C SDA voltage = 0.4V 2 -- -- mA SDA Valid Acknowledge Time tVD;ACK -- -- 0.45 s I/O Time Deglitch EN Rising Deglitch Time tEN_R_DEG -- 5 -- s EN Falling Deglitch Time tEN_F_DEG -- 50 -- s

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit RESETIN Detection Delay Time tRESETIN_DET_DLY Delay time starts detecting RESETIN after PGOOD normal state is ready -- 100 -- s RSETIN Rising Deglitch Time tRSETIN_R_DEG -- 50 -- s RSETIN Falling Deglitch Time tRSETIN_F_DEG -- 5 -- s Safety I/O Time Deglitch ERRIN1/2 Detection Delay Time tERRIN1/2_DET_DLY Delay time starts detecting ERRIN1/2 after PGOOD normal state is ready -- 100 -- s ERRIN1/2 Rising Deglitch Time tERRIN1/2_R_DEG -- 50 -- s ERRIN1/2 Falling Deglitch Time tERRIN1/2_F_DEG -- 50 -- s VMONIN Time Deglitch VMONIN Monitor Voltage Detection Delay Time tVMONIN_DET_DLY Delay time starts detecting VMONIN after PGOOD normal state is ready -- 100 -- s VMONIN Monitor Voltage Deglitch Time tVMONIN_DEG -- 50 -- s Protection Time Deglitch HVBuck1 Output UVP Deglitch Time tUVP_DEG_HV1 -- 50 -- s LVBuck2 Output UVP Deglitch Time tUVP_DEG_LV2 -- 50 -- s LVBuck3 Output UVP Deglitch Time tUVP_DEG_LV3 -- 50 -- s LDO1 Output UVP Deglitch Time tUVP_DEG_LDO1 -- 50 -- s LDO2 Output UVP Deglitch Time tUVP_DEG_LDO2 -- 50 -- s HVBuck1 Output OVP Deglitch Time tOVP_DEG_HV1 -- 50 -- s LVBuck2 Output OVP Deglitch Time tOVP_DEG_LV2 -- 50 -- s

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Parameter Symbol Test Conditions Min Typ Max Unit LVBuck3 Output OVP Deglitch Time tOVP_DEG_LV3 -- 50 -- s LDO1 Output OVP Deglitch Time tOVP_DEG_LDO1 -- 50 -- s LDO2 Output OVP Deglitch Time tOVP_DEG_LDO2 -- 50 -- s PVD23 OVP Rising Deglitch Time tOVP_R_DEG_PVD23 V = 700mV -- 5 6 s PVD23 OVP Falling Deglitch Time tOVP_F_DEG_PVD23 V = 700mV -- 5 6 s PVD45 OVP Rising Deglitch Time tOVP_R_DEG_PVD45 -- 5 -- s PVD45 OVP Falling Deglitch Time tOVP_F_DEG_PVD45 -- 5 -- s HVBuck1 OCP Deglitch Time tOCP_DEG_HV1 -- 1 -- ms LVBuck2 OCP Deglitch Time tOCP_DEG_LV2 -- 1 -- ms LVBuck3 OCP Deglitch Time tOCP_DEG_LV3 -- 1 -- ms LDO1 OCP Deglitch Time tOCP_DEG_LDO1 -- 1 -- ms LDO2 OCP Deglitch Time tOCP_DEG_LDO2 -- 1 -- ms Component Constraint Effective Output Inductance LHV1 1 1.5 2 H LLV2 0.68 1 1.2 LLV3 0.68 1 1.2 Effective Boot Capacitance CBOOT 0.07 0.1 0.13 F Effective PVCC Capacitance CPVCC 0.3 1 1.4 F Effective Input Capacitance CIN_HV1 1.5 4.7 10 F CIN_PVD23 1.5 4.7 10 CIN_PVD45 0.7 2.2 4

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Parameter Symbol Test Conditions Min Typ Max Unit Effective Output Capacitance CO_HV1 3.3 10 14 CO_LV2 4.5 10 14 CO_LV3 4.5 10 14 CO_LDO1 0.7 2.2 33 CO_LDO2 0.7 2.2 22 Output Capacitance ESR for HVBuck1, LVBuck2, LVBuck3, LDO1, and LDO2 CO_ESR -- 10 20 m

15 Typical Application Circuit

15.1 General CIS Application

VOUT_HV1 3.6V AGND BOOT CP1, CP2, CP3, CP4, PGND VOUT_LV2 1.1V SDA SCL VOUT1 RESETIN ERROUT VOUT5 ERRIN1 4.7μF 1μF 0.1μF 10μF 4.7μF 10μF 10μF 2.2μF 1.5μH 1μH 1μH ERRIN2 VMONIN PGOOD 2.2μF C10 2.2μF VOUT_HV1 VOUT_LDO2 VOUT_LV3 10k 10k CIS Serializer DVDD AVDD IOVDD DVDD IOVDD VOUT_LV2 SCL SDA I/O VCAPO1 VOUT_LDO1 3.3V VOUT_LV3 1.8V RTQ2079-QF RESET 2324 CP1, CP2, CP3, CP4, 25 (Exposed Pad) EN3 ERROUT1 ERROUT2 I/O DC / DC Option 10k 10k 10k VOUT_LV3

15.2 General CIS with ISP Application

VOUT_HV1 3.6V AGND BOOT VOUT_LV2 1.1V SDA SCL VOUT1 RESETIN ERROUT VOUT5 ERRIN1 4.7μF 1μF 0.1μF 10μF 4.7μF 10μF 10μF 2.2μF 1.5μH 1μH 1μH ERRIN2 VMONIN PGOOD 2.2μF C10 2.2μF VOUT_HV1 VOUT_LDO2 1.8V VOUT_LDO2 10k 10k 10k CIS Serializer DVDD AVDD IOVDD DVDD IOVDD VOUT_LV2 SCL SDA RESET VCAPO1 VOUT_LDO1 3.3V VOUT_LV3 0.9V ISP DVDD VPLL VCORE IOVDD PG RTQ2079-QF CP1, CP2, CP3, CP4, PGND CP1, CP2, CP3, CP4, 25 (Exposed Pad) EN3

15.3 General CIS Application with Battery Input

VOUT_HV1 3.6V AGND BOOT VOUT_LV2 1.1V SDA SCL VOUT1 RESETIN ERROUT VOUT5 ERRIN1 4.7μF 1μF 0.1μF 10μF 4.7μF 10μF 10μF 2.2μF 1.5μH 1μH 1μH ERRIN2 VMONIN PGOOD 2.2μF C10 2.2μF VOUT_HV1 VOUT_LDO2 1.8V VOUT_LDO2 10k 10k 10k CIS Serializer DVDD AVDD IOVDD DVDD IOVDD VOUT_LV2 SCL SDA RESET VCAPO1 VOUT_LDO1 3.3V VOUT_LV3 0.9V ISP DVDD VPLL VCORE IOVDD PG RTQ2079-QF CP1, CP2, CP3, CP4, PGND CP1, CP2, CP3, CP4, 25 (Exposed Pad) EN3VEN Option Load dump protection circuit 1.6M 100k

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Table 1. Recommended Component List for Evaluation Board Table 2. Recommended Component List for Load Dump Protection Circuit

16 Typical Operating Characteristics

Efficiency (%) Output Current (A) HVBuck1 Efficiency VOUT_HV1 = 3.6V, TA = 25C VIN = 6V VIN = 9V VIN = 12V VIN = 16V VIN = 24V 3.600 3.605 3.610 3.615 3.620 3.625 3.630 Output Voltage (V) Output Current (A) HVBuck1 Load Regulation VOUT_HV1 = 3.6V, TA = 25C VIN = 24V VIN = 16V VIN = 12V VIN = 9V VIN = 6V HVBuck1 Load Transient Time (160s/Div) VOUT_HV1 = 3.6V, VIN = 6V, TA = 25C, IOUT = 10mA to 0.5A to 10mA, 1s, FPWM IOUT (0.2A/Div) VOUT_HV1 (0.1V/Div) 100 Efficiency (%) Output Current (A) LVBuck2 Efficiency PVD23 = 2.7V PVD23 = 3.3V PVD23 = 3.6V PVD23 = 5V VOUT_LV2 = 1.1V, TA = 25C 1.096 1.098 1.100 1.102 1.104 1.106 Output Voltage (V) Output Current (A) LVBuck2 Load Regulation PVD23 = 2.7V PVD23 = 3.3V PVD23 = 3.6V PVD23 = 5V VOUT_LV2 = 1.1V, TA = 25C LVBuck2 Load Transient Time (160s/Div) VOUT_LV2 = 1.1V, PVD23 = 3.6V, TA = 25C, IOUT = 10mA to 0.5A to 10mA, 1s, FPWM IOUT (0.2A/Div) VOUT_LV2 (0.05V/Div)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com 100 Efficiency (%) Output Current (A) LVBuck3 Efficiency PVD23 = 2.7V PVD23 = 3.3V PVD23 = 3.6V PVD23 = 5V VOUT_LV3 = 1.8V, TA = 25C 1.796 1.798 1.800 1.802 1.804 1.806 Output Voltage (V) Output Current (A) LVBuck3 Load Regulation PVD23 = 2.7V PVD23 = 3.3V PVD23 = 3.6V PVD23 = 5V VOUT_LV3 = 1.8V, TA = 25C IOUT (0.2A/Div) LVBuck3 Load Transient Time (160s/Div) VOUT_LV3 = 1.8V, PVD23 = 3.6V, TA = 25C, IOUT = 10mA to 0.5A to 10mA, 1s, FPWM VOUT_LV3 (0.05V/Div) 3.265 3.270 3.275 3.280 3.285 3.290 3.295 3.300 3.305 Output Voltage (V) Output Current (A) LDO1 Load Regulation PVD45 = 3.6V PVD45 = 4.2V PVD45 = 5V VOUT_LDO1 = 1.8V, TA = 25C 1.780 1.785 1.790 1.795 1.800 1.805 1.810 Output Voltage (V) Output Current (A) LDO2 Load Regulation VOUT_LDO2 = 1.8V, TA = 25C PVD45 = 2.7V PVD45 = 3.1V PVD45 = 3.3V PVD45 = 3.6V PVD45 = 5V 100 120 140 160 180 0 50 100 150 200 250 300 Dropout Voltage (mV) Output Current (mA) LDO1 Dropout Voltage vs. Output Current 125C 25C −40C VOUT_LDO1 = 3.3V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 100 150 200 250 0 50 100 150 200 250 300 350 400 Dropout Voltage (mV) Output Current (mA) LDO2 Dropout Voltage vs. Output Current 125C 25C −40C VOUT_LDO2 = 3.3V -100 -80 -60 -40 -20 10 100 1000 10000 100000 100000010000000 PSRR (dB) Frequency (Hz) LDO1 PSRR −40C 25C 125C PVD45 = 3.6V, VOUT_LDO1 = 3.3V, IOUT_LDO = 100mA -100 -80 -60 -40 -20 10 100 1000 10000 100000 100000010000000 PSRR (dB) Frequency (Hz) LDO2 PSRR −40C 25C 125C PVD45 = 3.7V, VOUT_LDO2 = 3.3V, IOUT_LDO = 100mA 0.01 0.1 100 1000 10000 100000 Output Noise (µV∕√ ) Frequency (Hz) LDO1 Output Noise −40C 25C 125C PVD45 = 3.6V, VOUT_LDO1 = 3.3V, IOUT_LDO1 = 100mA 0.01 0.1 100 1000 10000 100000 Output Noise (µV∕√ ) Frequency (Hz) LDO2 Output Noise −40C 25C 125C PVD45 = 3.7V, VOUT_LDO2 = 3.3V, IOUT_LDO2 = 100mA Output Voltage Ripple (Full Load) VOUT_HV1 (10mV/Div) VOUT_LV2 (10mV/Div) VOUT_LV3 (10mV/Div) VOUT_LDO1 (10mV/Div) VOUT_LDO2 (10mV/Div) Time (200ns/Div) VOUT_HV1 = 3.6V, VOUT_LV2 = 1.1V, VOUT_LV3 = 1.8V, VOUT_LDO1 = 3.3V, VOUT_LDO2 = 1.8V, SSP_EN bit = 0, TA = 25C,

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com VOUT_HV1 (2V/Div) SEQ4 Power-On VOUT_LV2 (1V/Div) VOUT_LV3 (1V/Div) VOUT_LDO1 (1V/Div) VOUT_LDO2 (1V/Div) Time (1ms/Div) VOUT_HV1 = 3.6V, VOUT_LV2 = 1.1V, VOUT_LV3 = 1.8V, VOUT_LDO1 = 3.3V, VOUT_LDO2 = 1.8V SEQ4 Power-Off VOUT_HV1 (2V/Div) VOUT_LV2 (1V/Div) VOUT_LV3 (1V/Div) VOUT_LDO1 (1V/Div) VOUT_LDO2 (1V/Div) Time (2ms/Div) VOUT_HV1 = 3.6V, VOUT_LV2 = 1.1V, VOUT_LV3 = 1.8V, VOUT_LDO1 = 3.3V, VOUT_LDO2 = 1.8V

17 Operation

The RTQ2079-QF is a highly integrated power management integrated circuit (PMIC) for automotive camera system. It includes three step-down converters (HVBuck1, LVBuck2, and LVBuck3) and two generic LDOs (LDO1 and LDO2).

17.1 System Undervoltage and Overvoltage Protection

The RTQ2079-QF disables all channels if the VIN voltage falls below the undervoltage-lockout level (VUVLO_F) and the duration time is longer than 32 s. The device initializes in its default state after the VIN voltage recovers from VUVLO_R. When the VIN voltage reaches the overvoltage protection level (V OVP_R_VIN), the step-down converters, LDOs, and SEQOUT are disabled immediately. Then the IC enters the “Regulator-Off” state and PGOOD and ERROUT changes from "H" to "L" to indicate the IC is in a fault status. When VIN falls below 19.5V and the duration time is longer than 5s, then the RTQ2079-QF resumes operation automatically.

17.2 Over-Temperature Protection

The RTQ2079 -QF features over -temperature warning (OTW) and over-temperature protection (TSD). When the junction temperature exceeds the typical value of 130°C, the OTW function is activated, and the ERROUT status changes from "H" to "L" state for indication, but all outputs continue to operate. When the junction temperature exceeds the typical value of 170°C, the TSD function is activated, resulting in the disabling all outputs and the device enters the "Regulator-Off" state. Meanwhile, the PGOOD status also changes from "H" to "L" state to indicate the IC is in a fault status. The RTQ2079-QF will automatically resume normal operation once the junction temperature falls below the TSD threshold with a 20°C hysteresis band.

17.3 Pre-Regulator

The device integrates a 4.58V linear regulator (PVCC) supplied by VIN to provide power to the internal circuitry. The PVCC is “NOT” allowed to power any other device or circuitry. A 1 F decoupling capacitor must be connected between PVCC and AGND to filter the noise, and it needs to be placed as close as possible to the PVCC pin.

17.4 Peak Current Mode Control

The three step-down converters utilize peak current mode control. At the beginning of each clock cycle, the internal high-side MOSFET turns on, allowing the current to ramp up in the inductor. By comparing the inductor peak current signal with the internal compensation signal derived from the feedback voltage, the turn-on time of high-side and low- side MOSFETs in every switching cycle are determined. In other words, the inductor current is used to control the duty-cycle and output voltage regulation of the converter.

17.5 Spread Spectrum Operation

Due to the periodicity of the switching signal, energy tends to concentrate at the fundamental frequency and its N - order harmonics. This concentration of energy can result in radiation that may cause the EMI issues. To address this, the RTQ2079-QF is equipped with a spread spectrum function designed to reduce EMI and ensure compliance with automotive EMC standards (CISPR 25). The spread spectrum function employs a pseudo -random sequence to modulate the switching frequency, allowing it to vary ra ndomly within a range of 0% to 12%. For example, with a 2.1MHz typical switching frequency, the actual frequency will randomly oscillate between 2.1MHz and 2.352MHz. As a result, the RTQ207 9-QF effectively prevents the switching frequency from interfering with the 1.8MHz AM band, which is a critical requirement of CISPR 25.

17.6 Phase-Shift Operation

converters are in use, the initial turn -on time between two high-side MOSFETs has a 180-degree phase difference. Likewise, there is a 120-degree phase difference when three step-down converters are in use.

17.7 Channel Floating Allowable

malfunction in an unused channel will not impact the device operation.

17.8 Reboot Operation

is set to 0, the IC remains in the Fail-Safe state.

17.9 Power-Good Indication

a "Power-Good" status after a 10ms delay. Table 3. Unused Channel Pin Connection

7 VOUT2 Floating

8 SW2 Floating

9 PVD23 Connect to a fixed stable voltage

10 SW3 Floating

11 VOUT3 Floating

19 VOUT4 Floating with minimum effective

20 PVD45 Connect to a fixed stable voltage

21 VOUT5 Floating with minimum effective

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Unused Channel Unused Pin Number Unused Pin Name Pin Configuration ERRIN1 16 ERRIN1 ⚫ Floating (0x0E[3] = 0) ⚫ Connect to ground (0x0E[3] = 1, 0x0E[1] = 1) ⚫ Connect to a fixed stable voltage ERRIN2 15 ERRIN2 ⚫ Floating (0x0E[2] = 0) ⚫ Connect to ground (0x0E[2] = 1, 0x0E[0] = 1) ⚫ Connect to a fixed stable voltage I2C

17 SDA Connect to ground

18 SCL Connect to ground

RESETIN 22 RESETIN Connect to ground VMONIN 23 VMONIN Floating (0x0C[4] = 0)

18.1 Load Dump Protection

18.2 Device and Channel Enable Control

below the UVLO falling voltage.

18.3 Device Register Configuration Control

18.4 Device State Machine

There are seven main states listed in the Table 4. Table 4. Device State

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 State Description Entry Exit ⚫ RESET behavior (RESETIN, RESET bit) ⚫ SEQ_CTRL_bit 0x00[0] = 0 From Fail-Safe ⚫ EN = L ⚫ VIN  VUVLO_F ⚫ RESET behavior (RESETIN, RESET bit) ⚫ REBOOT_ACT 0x00[1] = 1 Standby The device passes the built- in self -test (BIST) and waits for an I2C command to enable all channels. BIST pass To Regulator-Off ⚫ EN = L ⚫ VIN  VUVLO_F ⚫ Fault event (VIN OVP, VPVD23 OVP, VPVD45 OVP, TSD) To Power-On ⚫ SEQ_CTRL 0x00[0] = 1 and no RESET behavior (RESETIN, RESET bit) Power-On Channel power-on procedure starts. From Standby SEQ_CTRL 0x00[0] = 1 and no RESET behavior (RESETIN, RESET bit) To Regulator-Off ⚫ EN = L ⚫ VIN  VUVLO_F ⚫ Fault event (VIN OVP, VPVD23 OVP, VPVD45 OVP, TSD) To Active ⚫ The output voltages of all enable channels rise to 90% of the target values To Fail-Safe ⚫ Fault event (CH VO UVP, CH VO OVP) if the register 0x0F = 1Fh, 0x10 = 1Fh ⚫ Fault event (CH OCP)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com State Description Entry Exit Active The output voltages of all enabled channels rise to 90% of their target values. The PGOOD and ERROUT signals change to a high state to indicate the power status and any fault events. The ERRIN1, ERRIN2, VMONIN, and RESEIN functions are activated after the PGOOD signal changes to a high state. From Power-On The output voltages of all enabled channels rise to 90% of the target values. From Alarm ⚫ All fault registers (0x11 to 0x15) event = 0 To Regulator-Off ⚫ EN = L ⚫ VIN  VUVLO_F ⚫ Fault event (VIN OVP, VPVD23 OVP, VPVD45 OVP, TSD) ⚫ RESET behavior (RESETIN, RESET bit) ⚫ SEQ_CTRL 0x00[0] = 0 To Alarm ⚫ Fault event (CH VO UVP, CH VO OVP) if register 0x0F = 00h, 0x10 = 00h ⚫ Fault event (ERRIN1, ERRIN2, VMON UVP, VMON OVP) ⚫ Fault event (OTW) ⚫ Any fault register (0x11 to 0x15, except 0x12[6]) event = 1 To Fail-Safe ⚫ Fault event (CH VO UVP, CH VO OVP) if register 0x0F = 1Fh, 0x10 = 1Fh ⚫ Fault event (CH OCP) Alarm When a fault event is detected but the channel is not turned off, the PGOOD signal remains in a high state, and ERROUT changes to a low state as a warning. From Active ⚫ Fault event (CH VO UVP, CH VO OVP) if register 0x0F = 00h, 0x10 = 00h ⚫ Fault event (ERRIN1, ERRIN2, VMON UVP, VMON OVP) ⚫ Fault event (OTW) ⚫ Any fault register (0x11 to 0x15, except 0x12[6]) event = To Regulator-Off ⚫ EN = L ⚫ VIN  VUVLO_F ⚫ Fault event (VIN OVP, VPVD23 OVP, VPVD45 OVP, TSD) ⚫ RESET behavior (RESETIN, RESET bit) ⚫ SEQ_CTRL 0x00[0] = 0 To Active ⚫ All fault registers (0x11 to 0x15) event = 0 To Fail-Safe ⚫ Fault event (CH VO UVP, CH VO OVP) if register 0x0F = 1Fh, 0x10 = 1Fh ⚫ Fault event (CH OCP)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 State Description Entry Exit Fail-Safe When a fault event is detected and all channels are turned off, the PGOOD signal changes to a low state to indicate the power status. The ERROUT signal also changes to a low state to indicate a fault has been detected. ⚫ BIST failure ⚫ Fault event (CH VO UVP, CH VO OVP) if register 0x0F = 1Fh, 0x10 = 1Fh ⚫ Fault event (CH OCP) To Regulator-Off ⚫ VIN  VUVLO_F ⚫ EN = L ⚫ RESET behavior (RESETIN, RESET bit) ⚫ REBOOT_ACT 0x00[1] = 1

18.5 Power Sequence and Interval Time Setting

power sequence and interval time to establish factory default settings. Table 5. Power-On Sequence

18.6 Power-On/Off Control

reverse order of the power-on sequence. Figure 2. Example of SEQ4 Power Sequence Triggered by VUVLO (VIN = EN)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. sequence will change to the power-off sequence. Figure 7. Example of SEQ4 Power Sequence Triggered by RESETIN

18.7 Output Voltage Setting

programmable settings for the corresponding output voltages, establishing them as the factory default settings.

18.7.1 HVBuck1, LVBuck2, and LVBuck3

HVBuck1 output voltage can be set via the register at 0x03[3:0] from 2.7V to 5V, and the default voltage is 3.6V. LVBuck2 output voltage can be set via the register at 0x04[4:0] from 0.6V to 1.9V, and the default voltage is 1.1V. LVBuck3 output voltage can be set via the register at 0x05[4:0] from 0.6V to 1.9V, and the default voltage is 1.8V.

18.7.2 LDO1 and LDO2

18.8 External Voltage Monitoring (VMONIN)

18.9 External Error Monitoring (ERRIN1, ERRIN2)

The RTQ2079-QF includes two error-monitoring pins, ERRIN1 and ERRIN2, to monitor external device error signals. When the ERRIN configuration register bit at 0x0E[3] or 0x0E[2] is set to 1, the device monitors the error signal 100s after the PGOOD signal asserts high. If an external error signal is detected through ERRIN1 or ERRIN2, the device enters an Alarm state. The ERROUT signal changes from a high to a low state as a warning, without disabling any channels. The ECU can configure different signal triggering directions via the register at 0x0E[1:0]. This function is enabled by default with a high active direction and can be configured through the register at 0x0E[3:2].

18.10 Reset Function

The RTQ2079-QF is equipped with an external hardware reset pin, RESETIN , and a RESET register at 0x0D[4] to reset the device. The device activates the RESET function 100s after the PGOOD signal asserts high. The RESET_ACT register bit at 0x0D[3] offers two configuration options: ⚫ If the register bit 0x0D[3] is set to 0, all registers except for the sequence control related registers at 0x02[4:0], the external error monitoring related register at 0x0E[3:0], and the fault event indication registers at 0x11 to 0x15 are reset to their default values. The device follows the sequence settings to disable output rails. The fault event log remains stored in the corresponding registers and can be accessed by the ECU after reset. ⚫ If the register bit 0x0D[3] is set to 1, all registers except for the sequence control related register at 0x02[4:0] and external error monitoring related register at 0x0E[3:0] are reset to their default values. The device follows the sequence settings to disable output rails.

18.11 Protection Features

The RTQ2079-QF is equipped with multiple protections to safeguard the device from damage caused by abnormal operations or fault conditions, including overload, short-circuit, soldering issues, and more.

18.11.1 Channel Output Undervoltage Protection (UVP)

There are four configurable UVP thresholds via the registers at 0x08 and 0x09[5:4]. The output UVP deglitch time is adjustable through the registers at 0x09[3:0]. When any of the bits at 0x0F[4:0] is configured to 1, the device disables all channels simultaneously and enters a Fail -Safe state once a UV fault is detected on any channel. Conversely, if all bits at 0x0F[4: 0] are configured to 0 when a UV fault is detected, the device does not disable any channels but enters an Alarm state instead. The registers at 0x13[4:0] indicate that a UV fault event occurred on the corresponding channel, independent of the setting at 0x0F[4: 0]. The RTQ207 9-QF also includes OTP35 at registers 0xE3[1], providing one-time programmable settings of the channel output UVP behavior to be set as the factory default. Based on various states, there are different methods to reset the device, as shown in Table 4.

18.11.2 Channel Output Overvoltage Protection (OVP)

There are four configurable OVP thresholds via the registers at 0x0A and 0x0B[5:4]. The output OVP deglitch time is adjustable through the registers at 0x0B[3:0]. When any of the bits at 0x10[4:0] is configured to 1, the device disables all channels simultaneously and enters a Fail-Safe state once an OV fault is detected on any channel. Conversely, if all bits at 0x10[4:0] are configured to 0 when an OV fault is detected, the device does not disable any channels but enters an Alarm state instead. The registers at 0x14[4:0] indicate that the OV fault event occurred on the corresponding channel , independent of the setting s at 0x10[4:0]. The RTQ 2079-QF also includes OTP35 at registers 0xE3[2], providing one-time programmable settings of the channel output OVP behavior to be set as the factory default. Based on various states, there are different methods to reset the device, as shown in Table 4.

18.11.3 Channel Overcurrent Protection (OCP)

This section describes overcurrent protection function of HVBuck1, LVBuck2, LVBuck3, LDO1, and LDO2.

18.11.3.1 HVBuck1, LVBuck2, and LVBuck3

The step-down converter includes a cycle -by-cycle peak current limit for the high -side MOSFET, safeguarding against abnormal increases in inductor current, including those beyond the inductor’s saturation current rating. In the event of an overcurrent, the controller immediately turns off the high -side MOSFET and turn s on the low -side MOSFET to keep the inductor current within the peak current limit. After the inductor current decreases to below the valley current limit, the high -side MOSFET resumes switching. If an overcurrent fault is continuously detected for a duration longer than the deglitch time, the device disables all channels simultaneously and enters a Fail -Safe state. There are different methods to reset the device, as shown in Table 4.

18.11.3.2 LDO1 and LDO2

When the load exceeds the current-limit threshold, the output current is regulated to stay at this limit. If the overcurrent condition persists beyond the deglitch time, the device will disable all channels simultaneously and enter the Fail- Safe state. The device can be reset using various methods, as specified in Table 4.

18.11.4 Channel Input Overvoltage Protection (OVP)

If the input voltage of the step-down converters (LVBuck2 and LVBuck3), or LDO1 and LDO2 reaches the overvoltage protection threshold, the device disables all channels simultaneously and enters a Regulator -Off state. The device then automatically restarts and powers back on once the input voltage falls below the overvoltage threshold minus the hysteresis value.

18.11.5 Built-In Self-Test Protection

The RTQ2079-QF features a Built-In Self-Test (BIST) to ensure design integrity and enhance reliability. It conducts internal circuit tests before starting the rail power-on procedure The device enters a Fail-Safe state without activating the rails if the BIST fails, and the BIST_FAULT_EVT register at 0x11[6] is set to 1 to indicate a BIST failure.

18.11.6 ERROUT Protection

The ERROUT signal output is designed for error indication. The ERROUT pin is an open-drain design, and a pull-up resistor is needed. The ERROUT signal is pull ed low if the RTQ2079-QF detects any fault in the Active state. The RTQ2079-QF implements an ERROUT monitor to detect the open-drain logic faults. The fault will be recorded by the register bit at 0x12[6].

18.11.7 OTP Register CRC (Cyclic Redundancy Check) Protection

When EN changes to a high state and the supply voltage VIN exceeds the power-on reset level of 2.7V (typical), the device loads OTP data to reset all registers to default values . The CRC controller then begins to perform a CRC to verify the integrity of the OTP registers. The CRC controller calculates the checksum value of the OTP registers and compares it against the stored checksum value in OTP40. If a checksum error is detected, the device remains in the Power-Off state and sets the OTP_CRC_EVT register at 0x11[5] to 1 as an indication.

18.11.8 Device Configuration Register CRC Protection

When the ECU changes the registers to apply new settings, the CRC controller executes a CRC check to validate the integrity of the affected registers. If a checksum mismatch occurs, the device remains the current settings without reconfiguration. The CRC controller uses the standard CRC-8 polynomial, X8 + X2 + X+1, to calculate the checksum,

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. and it evaluates the CRC across an 8-bit string. Table 6. Protection List Table 4. (Alarm state) Table 4. (Fail-Safe state)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Channel Type PGOOD ERROUT Event CH3 LVBuck3 UVP H (0x0F[2] = 0) L LVBUCK3_UV_EVT (0x13[2] = 1) L (0x0F[2] = 1) OVP H (0x10[2] = 0) L LVBUCK3_OV_EVT (0x14[2] = 1) L (0x10[2] = 1) OCP L L LVBUCK3_OC_EVT (0x15[2] = 1) Input OVP L L PVD23_OV_EVT (0x11[1] = 1) CH4 LDO1 UVP H (0x0F[1] = 0) L LDO1_UV_EVT (0x13[1] = 1) L (0x0F[1] = 1) OVP H (0x10[1] = 0) L LDO1_OV_EVT (0x14[1] = 1) L (0x10[1] = 1) OCP L L LDO1_OC_EVT (0x15[1] = 1) Input OVP L L PVD45_OV_EVT (0x11[0] = 1) CH5 LDO2 UVP H (0x0F[0] = 0) L LDO2_UV_EVT (0x13[0] = 1) L (0x0F[0] = 1) OVP H (0x10[0] = 0) L LDO2_OV_EVT (0x14[0] = 1) L (0x10[0] = 1) OCP L L LDO2_OC_EVT (0x15[0] = 1) Input OVP L L PVD45_OV_EVT (0x11[0] = 1)

18.12 Inductor Selection

18.12.1 HVBuck1, LVBuck2, and LVBuck3

Based on the following equations, the maximum inductor current for various load conditions can be determined. It is recommended that the inductor’s saturation current rating exceed the calculated maximum current. To achieve optimal performance and efficiency, an inductor with a low Direct Current Resistance (DCR) should be chosen. The recommended nominal inductance is 1.5H for HVBuck1 and 1H for LVBuck2/LVBuck3. IL = VOUT × (VIN - VOUT) VIN × fSW × L IL_peak = IOUT + 1 2 × IL

18.13 Input and Output Capacitor Selection

18.13.1 HVBuck1, LVBuck2, and LVBuck3

It is recommended to use at least a 4.7F input capacitor with a 10F output capacitor for step-down converters. The ripple voltage is an important parameter when choosing output capacitor. This portion consists of two parts. One is the product of the ripple current and the ESR of the output capacitor; the other is generated by the charging and discharging cycles of the output capacitor. The output ripple voltage can be calculated using the following formula: VOUTRipple = VESR + VOUT = VESR + IL 8 × COUT × fSW where VESR = ICrms × RCESR

18.13.2 LDO1 and LDO2

Proper selection of external capacitors is crucial for stability and performance of any LDO. A 2.2 F capacitor is generally suitable for both input and output of the LDO. Additional capacitors in parallel on the output can enhance noise suppression, it may also result in increased inrush current during the LDO’s power-up sequence. This potential trade-off should be carefully evaluated.

18.14 I2C Interface

18.14.1 Slave Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 = LSB 1 1 1 0 1 0 1 R/W

18.14.2 Read and Write Function

Driven by Master, Driven by Slave, Start, Repeat StartStop, S SrP S 0 1 A P LSBMSB Assume Address = m Data for Address = m Sr Slave Address Register Address Slave Address Data 1 R/W AA A Read N bytes of data from Registers S 0 1 A P LSBMSB Assume Address = m Data for Address = m Sr Slave Address Register Address Slave Address Data R/W AA A Read a single byte of data from Register A CRC LSBMSB Checksum for Register Address, Slave Address(Read) and Data A CRC 1 LSBMSB Checksum for Register Address, Slave Address(Read) and Data 1 A LSBMSB Data for Address = m + 1 Data 2 A CRC 2 LSBMSB Checksum for Register Address, Slave Address(Read), Data 1, CRC 1 and Data 2 A LSBMSB Data for Address = m + N - 1 Data N A CRC N LSBMSB Checksum for Register Address, Slave Address(Read), Data 1~ N-1, CRC 1~ N-1 and Data N S 0 P Assume Address = m Data for Address = m Data for Address = m + N - 1Data for Address = m + 1 R/W Data N LSBMSB A A A LSB Slave Address Register Address Data 1 Data 2 MSB MSB LSB Write N bytes of data to Registers S 0 P Assume Address = m Data for Address = mR/W A A A Slave Address Register Address DataMSB LSB Write a single byte of data to Register CRCMSB LSB A Checksum for Slave Address, Register Address and Data A CRC 1MSB LSB A Checksum for Slave Address, Register Address and Data 1 A CRC 2MSB LSB Checksum for Slave Address, Register Address, Data 1, CRC 1 and Data 2 A A CRC NMSB LSB Checksum for Slave Address, Register Address, Data 1~ N-1, CRC 1~ N-1 and Data N

18.14.3 I2C Waveform Information

tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA tHD;STA tSP tBUF tSU;STO P S tR SrS tF tR

18.15 Thermal Considerations

the maximum power dissipation. Figure 8. Derating Curve of Maximum Power Dissipation

18.16 Layout Considerations

loop, which will help to improve EMI characteristics. ⚫ Place the input and output capacitors as close as possible to their respective pins to ensure effective filtering. ⚫ Keep the main power traces as wide and short as possible.

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. ⚫ Connect the AGND and PGND to a solid ground plane to enhance thermal dissipation and provide noise immunity. caused by parasitic resistance and inductance in the PCB traces. Figure 9. PCB Layout Guide and any safety, security, or other requirements.

19 Functional Register Description

R: Read Only R/W: Read and Write W1C: Write Clear (Write ‘1’ then automatic clears to ‘0’ after procedure finish) Table 8. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TOP_ CFG 0x00 Meaning Reserved Reserved Reserved UVLO UVLO_ DEG REBOOT _ACT SEQ_ CTRL Default 0 0 0 0 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W UVLO (CFG_LOCK) VIN UVLO (Falling/Rising) voltage setting 00: 3.3V/3.8V (default) 01: 3.8V/4.5V 10: 4.3V/5.0V 11: 6.8V/7.3V UVLO_DEG (CFG_LOCK) UVLO falling deglitch time setting 0: 32s (default) 1: 64s REBOOT_ACT (CFG_LOCK) IC auto-reboot behavior selection when the PMIC enters a Fail-Safe State 0: Auto-reboot is disabled. (default) 1: Auto-reboot is enabled (register keep) SEQ_CTRL Sequence ON and OFF control 0: Sequence OFF 1: Sequence ON (default)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 9. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CH_ CFG 0x01 Meaning PGOOD_DLY BUCK_ MODE HVBUCK 1_DIS LVBUCK 2_DIS LVBUCK 3_DIS LDO1_ DIS LDO2_ DIS Default 0 1 1 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PGOOD_DLY (CFG_LOCK) Time interval between the completion of the soft-start process for the last channel and the announcement of the Power-Good status. 00: 4.7ms 01: 9.4ms (default) 10: 14.1ms 11: 18.8ms BUCK_MODE (CFG_LOCK) LVBuck2 and LVBuck3 operation mode 0: PSM 1: FPWM (default) HVBUCK1_DIS (CFG_LOCK) HVBuck1 active output discharge 0: Enable (default) 1: Disable LVBUCK2_DIS (CFG_LOCK) LVBuck2 active output discharge 0: Enable (default) 1: Disable LVBUCK3_DIS (CFG_LOCK) LVBuck3 active output discharge 0: Enable (default) 1: Disable LDO1_DIS (CFG_LOCK) LDO1 active output discharge 0: Enable (default) 1: Disable LDO2_DIS (CFG_LOCK) LDO2 active output discharge 0: Enable (default) 1: Disable

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 10. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEQ_ ON_ CFG 0x02 Meaning Reserved ON_Td OFF_Td POWER_ON_SEQ Default 0 0 0 1 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W ON_Td (CFG_LOCK) Delay time between power-on channel and its next channel 00: 0ms (default) 01: 0.5ms 10: 1ms 11: 2ms OFF_Td (CFG_LOCK) Delay time between power-off channel and its next channel 00: 1ms 01: 1.5ms 10: 2ms (default) 11: 3ms POWER_ON_SEQ (CFG_LOCK) Power-on sequence setting 000: SEQ0 001: SEQ1 (default) 010: SEQ2 011: SEQ3 100: SEQ4 101: SEQ5 110: SEQ6 111: SEQ7 Table 11. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HVBUC K1_OU T_CFG 0x03 Meaning Reserved Reserved Reserved Reserved HVBUCK1_VOUT Default 0 0 0 0 1 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W HVBUCK1_VOUT (CFG_LOCK) HVBuck1 output voltage can be set from 2.7V to 4V (100mV/step), 4.5V, and 5.0V 0000: 2.7V 0001: 2.8V 0010: 2.9V 0011: 3.0V 0100: 3.1V 0101: 3.2V 0110: 3.3V 0111: 3.4V 1000: 3.5V 1001: 3.6V (default) 1010: 3.7V 1011: 3.8V 1100: 3.9V 1101: 4.0V 1110: 4.5V 1111: 5.0V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 12. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LVBUC K2_OU T_CFG 0x04 Meaning Reserved Reserved Reserved LVBUCK2_VOUT Default 0 0 0 0 1 0 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LVBUCK2_VOUT (CFG_LOCK) LVBuck2 output voltage can be set from 0.6V to 1.4V (50mV/step) and 1.4V to 1.9V (100mV/step) 00000: 0.60V 00001: 0.65V 00010: 0.70V 00011: 0.75V 00100: 0.80V 00101: 0.85V 00110: 0.90V 00111: 0.95V 01000: 1.00V 01001: 1.05V 01010: 1.10V (default) 01011: 1.15V 01100: 1.20V 01101: 1.25V 01110: 1.30V 01111: 1.35V 10000: 1.40V 10001: 1.50V 10010: 1.60V 10011: 1.70V 10100: 1.80V 10101: 1.90V 10110: 1.90V 10111: 1.90V 11000: 1.90V 11001: 1.90V 11010: 1.90V 11011: 1.90V 11100: 1.90V 11101: 1.90V 11110: 1.90V 11111: 1.90V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 13. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LVBUC K3_OU T_CFG 0x05 Meaning Reserved Reserved Reserved LVBUCK3_VOUT Default 0 0 0 1 0 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LVBUCK3_VOUT (CFG_LOCK) LVBuck3 output voltage can be set from 0.6V to 1.4V (50mV/step) and 1.4V to 1.9V (100mV/step) 00000: 0.60V 00001: 0.65V 00010: 0.70V 00011: 0.75V 00100: 0.80V 00101: 0.85V 00110: 0.90V 00111: 0.95V 01000: 1.00V 01001: 1.05V 01010: 1.10V 01011: 1.15V 01100: 1.20V 01101: 1.25V 01110: 1.30V 01111: 1.35V 10000: 1.40V 10001: 1.50V 10010: 1.60V 10011: 1.70V 10100: 1.80V (default) 10101: 1.90V 10110: 1.90V 10111: 1.90V 11000: 1.90V 11001: 1.90V 11010: 1.90V 11011: 1.90V 11100: 1.90V 11101: 1.90V 11110: 1.90V 11111: 1.90V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 14. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LDO1_ OUT_ CFG 0x06 Meaning Reserved LDO1_IOUT_OC_SS LDO1_VOUT Default 0 1 1 1 0 0 1 1 Read/Write R/W R R R/W R/W R/W R/W R/W LDO1_IOUT_OC_SS LDO1 output current limit at soft-start duration 00: 450mA 01: 450mA 10: 50mA 11: 150mA (default) LDO1_VOUT (CFG_LOCK) LDO1 output voltage can be set from 1.8V to 1.9V (50mV/step) and 2.5V to 3.5V (50mV/step) 00000: 1.80V 00001: 1.85V 00010: 1.90V 00011: 2.50V 00100: 2.55V 00101: 2.60V 00110: 2.65V 00111: 2.70V 01000: 2.75V 01001: 2.80V 01010: 2.85V 01011: 2.90V 01100: 2.95V 01101: 3.00V 01110: 3.05V 01111: 3.10V 10000: 3.15V 10001: 3.20V 10010: 3.25V 10011: 3.30V (default) 10100: 3.35V 10101: 3.40V 10110: 3.45V 10111: 3.50V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 15. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LDO2_ OUT_ CFG 0x07 Meaning Reserved Reserved Reserved Reserved LDO2_VOUT Default 0 0 0 1 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LDO2_VOUT (CFG_LOCK) LDO2 output voltage can be set from 1.8V to 3.3V(100mV/step) 0000: 1.8V (default) 0001: 1.9V 0010: 2.0V 0011: 2.1V 0100: 2.2V 0101: 2.3V 0110: 2.4V 0111: 2.5V 1000: 2.6V 1001: 2.7V 1010: 2.8V 1011: 2.9V 1100: 3.0V 1101: 3.1V 1110: 3.2V 1111: 3.3V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 16. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CH_ UVP1_ CFG 0x08 Meaning HVBUCK1_UV LVBUCK2_UV LVBUCK3_UV LDO1_UV Default 1 1 0 1 0 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W HVBUCK1_UV (CFG_LOCK) HVBuck1 UV detection threshold with respect to the target voltage 00: 95% 01: 90% 10: 85% 11: 80% (default) LVBUCK2_UV (CFG_LOCK) LVBuck2 UV detection threshold with respect to the target voltage 00: 96.5% 01: 95% (default) 10: 94% 11: 90% LVBUCK3_UV (CFG_LOCK) LVBuck3 UV detection threshold with respect to the target voltage 00: 96.5% 01: 95% (default) 10: 94% 11: 90% LDO1_UV (CFG_LOCK) LDO1 UV detection threshold with respect to the target voltage 00: 96.5% 01: 95% (default) 10: 94% 11: 90% Table 17. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CH_ UVP2_ CFG 0x09 Meaning Reserved Reserved LDO2_UV HVBUCK1_UV_DEG LVCH_UV_DEG Default 0 0 0 1 0 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LDO2_UV (CFG_LOCK) LDO2 UV detection threshold with respect to the target voltage 00: 96.5% 01: 95% (default) 10: 94% 11: 90% HVBUCK1_UV_DEG (CFG_LOCK) HVBuck1 UV detection deglitch time selection 00: Reserved 01: 50s (default) 10: 75s 11: 100s LVCH_UV_DEG (CFG_LOCK) LVBuck2, LVBuck3, LDO1, and LDO2 UV detection deglitch time selection 00: Reserved 01: 50s (default) 10: 75s 11: 100s

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 18. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CH_ OVP1_ CFG 0x0A Meaning HVBUCK1_OV LVBUCK2_OV LVBUCK3_OV LDO1_OV Default 0 1 0 1 0 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W HVBUCK1_OV (CFG_LOCK) HVBuck1 OV detection threshold with respect to the target voltage 00: 105% 01: 110% (default) 10: 115% 11: 120% LVBUCK2_OV (CFG_LOCK) LVBuck2 OV detection threshold with respect to the target voltage 00: 103.5% 01: 105% (default) 10: 106% 11: 110% LVBUCK3_OV (CFG_LOCK) LVBuck3 OV detection threshold with respect to the target voltage 00: 103.5% 01: 105% (default) 10: 106% 11: 110% LDO1_OV (CFG_LOCK) LDO1 OV detection threshold with respect to the target voltage 00: 103.5% 01: 105% (default) 10: 106% 11: 110% Table 19. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CH_ OVP2_ CFG 0x0B Meaning Reserved Reserved LDO2_OV HVBUCK1_OV_DEG LVCH_OV_DEG Default 0 0 0 1 0 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LDO2_OV (CFG_LOCK) LDO2 OV detection threshold with respect to the target voltage 00: 103.5% 01: 105% (default) 10: 106% 11: 110% HVBUCK1_OV_DEG (CFG_LOCK) HVBuck1 OV detection deglitch time selection 00: Reserved 01: 50s (default) 10: 75s 11: 100s LVCH_OV_DEG (CFG_LOCK) LVBuck2, LVBuck3, LDO1 and LDO2 OV detection deglitch time selection 00: Reserved 01: 50s (default) 10: 75s 11: 100s

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 20. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VMON_ CFG 0x0C Meaning Reserved VMON_DEG VMON_EN VMON_H VMON_L Default 0 1 1 0 0 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W VMON_DEG (CFG_LOCK) VMONIN deglitch time 00: 10s 01: 15s 10: 25s 11: 50s (default) VMON_EN (CFG_LOCK) VMONIN function 0: Disable (default) 1: Enable VMON_H (CFG_LOCK) VMON sensed voltage high level can be set from 0.96V to 1.33V. 00: 1.33V 01: 1.28V (default) 10: 1.18V 11: 0.96V VMON_L (CFG_LOCK) VMON sensed voltage low level can be set from 0.84V to 1.14V. 00: 1.09V 01: 1.14V (default) 10: 1.02V 11: 0.84V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 21. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FUNC1 _CFG 0x0D Meaning Reserved Reserved Reserved RESET RESET_ ACT FAULT_ MASK PHASE_ EN SSP_EN Default 0 0 0 0 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W RESET SW reset and reset behavior follows 0x0D[3], RESET_ACT 0: None (default) 1: SW Reset RESET_ACT (CFG_LOCK) RESET triggered registers behavior selection 0: Reset all registers to default value , with the exception of the fault event registers (default) 1: Reset all registers to default value FAULT_MASK (CFG_LOCK) All faults event mask 0: Unmask (default) 1: Mask PHASE_EN (CFG_LOCK) Bucks' switching phase shift function 0: Disable 1: Enable (default) SSP_EN (CFG_LOCK) Bucks' switching frequency spread spectrum function 0: Disable 1: Enable (default) Table 22. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FUNC2 _CFG 0x0E Meaning Reserved Reserved Reserved Reserved ERRIN1 _EN ERRIN2 _EN ERRIN1 _ACTL ERRIN2 _ACTL Default 0 0 0 0 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W ERRIN1_EN ERRIN1 function 0: Disable 1: Enable (default) ERRIN2_EN ERRIN2 function 0: Disable 1: Enable (default) ERRIN1_ACTL ERRIN1 pin level to act selection 0: Low to act 1: High to act (default) ERRIN2_ACTL ERRIN2 pin level to act selection 0: Low to act 1: High to act (default)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 23. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PROTE C1_ CFG 0x0F Meaning Reserved Reserved Reserved HVBUC K1_UV_ SD LVBUCK 2_UV_ SD LVBUCK 3_UV_ SD LDO1_ UV_SD LDO2_ UV_SD Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W HVBUCK1_UV_SD (CFG_LOCK) HVBuck1 undervoltage protection behavior selection 0: Only inform ECU of fault events (default) 1: Channel latch-off and inform ECU of fault events LVBUCK2_UV_SD (CFG_LOCK) LVBuck2 undervoltage protection behavior selection 0: Only inform ECU of fault events (default) 1: Channel latch-off and inform ECU of fault events LVBUCK3_UV_SD (CFG_LOCK) LVBuck3 undervoltage protection behavior selection 0: Only inform ECU of fault events (default) 1: Channel latch-off and inform ECU of fault events LDO1_UV_SD (CFG_LOCK) LDO1 undervoltage protection behavior selection 0: Only inform ECU of fault events (default) 1: Channel latch-off and inform ECU of fault events LDO2_UV_SD (CFG_LOCK) LDO2 undervoltage protection behavior selection 0: Only inform ECU of fault events (default) 1: Channel latch-off and inform ECU of fault events

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 24. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PROTE C2_ CFG 0x10 Meaning Reserved Reserved Reserved HVBUC K1_OV_ SD LVBUCK 2_OV_ SD LVBUCK 3_OV_ SD LDO1_ OV_SD LDO2_ OV_SD Default 0 0 0 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W HVBUCK1_OV_SD (CFG_LOCK) HVBuck1 overvoltage protection behavior selection 0: Only inform ECU of fault events 1: Channel latch-off and inform ECU of fault events (default) LVBUCK2_OV_SD (CFG_LOCK) LVBuck2 overvoltage protection behavior selection 0: Only inform ECU of fault events 1: Channel latch-off and inform ECU of fault events (default) LVBUCK3_OV_SD (CFG_LOCK) LVBuck3 overvoltage protection behavior selection 0: Only inform ECU of fault events 1: Channel latch-off and inform ECU of fault events (default) LDO1_OV_SD (CFG_LOCK) LDO1 overvoltage protection behavior selection 0: Only inform ECU of fault events 1: Channel latch-off and inform ECU of fault events (default) LDO2_OV_SD (CFG_LOCK) LDO2 overvoltage protection behavior selection 0: Only inform ECU of fault events 1: Channel latch-off and inform ECU of fault events (default)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 25. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BASE1 _EVT 0x11 Meaning Reserved BIST_ FAULT_ EVT OTP_ CRC_ EVT TWARN_ EVT TSD_ EVT VIN_OV_ EVT PVD23_ OV_EVT PVD45_ OV_EVT Default 0 0 0 0 0 0 0 0 Read/Write R/W W1C W1C W1C W1C W1C W1C W1C BIST_FAULT_EVT BIST fault acknowledgement 0: No faults are detected, or faults are masked (default) 1: Fault is detected OTP_CRC_EVT Internal OTP CRC checking fault acknowledgement 0: No faults are detected, or faults are masked (default) 1: Fault is detected TWARN_EVT Thermal warning event acknowledgement 0: No faults are detected, or faults are masked (default) 1: Fault is detected TSD_EVT Thermal shutdown event acknowledgement 0: No faults are detected, or faults are masked (default) 1: Fault is detected VIN_OV_EVT VIN overvoltage threshold event acknowledgement 0: No faults are detected, or faults are masked (default) 1: Fault is detected PVD23_OV_EVT PVD23 overvoltage threshold event acknowledgement 0: No faults are detected, or faults are masked (default) 1: Fault is detected PVD45_OV_EVT PVD45 overvoltage threshold event acknowledgement 0: No faults are detected, or faults are masked (default) 1: Fault is detected

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 26. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BASE2 _EVT 0x12 Meaning Reserved ERROUT _ALARM _EVT Reserved Reserved VMONIN _OV_ EVT VMONIN _UV_ EVT ERRIN1 _EVT ERRIN2 _EVT Default 0 0 0 0 0 0 0 0 Read/Write R/W W1C R/W R/W W1C W1C W1C W1C ERROUT_ALARM_EVT ERROUT logic fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected VMONIN_OV_EVT VMONIN overvoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected VMONIN_UV_EVT VMONIN undervoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected ERRIN1_EVT ERRIN1 fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected ERRIN2_EVT ERRIN2 fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 27. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CH_UV _EVT 0x13 Meaning Reserved Reserved Reserved HVBUC K1_UV_ EVT LVBUCK 2_UV_ EVT LVBUCK 3_UV_ EVT LDO1_ UV_EVT LDO2_ UV_EVT Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W W1C W1C W1C W1C W1C HVBUCK1_UV_EVT HVBuck1 undervoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LVBUCK2_UV_EVT LVBuck2 undervoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LVBUCK3_UV_EVT LVBuck3 undervoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LDO1_UV_EVT LDO1 undervoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LDO2_UV_EVT LDO2 undervoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 28. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CH_OV _EVT 0x14 Meaning Reserved Reserved Reserved HVBUC K1_OV_ EVT LVBUCK 2_OV_ EVT LVBUCK 3_OV_ EVT LDO1_ OV_EVT LDO2_ OV_EVT Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W W1C W1C W1C W1C W1C HVBUCK1_OV_EVT HVBuck1 overvoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LVBUCK2_OV_EVT LVBuck2 overvoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LVBUCK3_OV_EVT LVBuck3 overvoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LDO1_OV_EVT LDO1 overvoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LDO2_OV_EVT LDO2 overvoltage fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 29. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CH_OC _EVT 0x15 Meaning Reserved Reserved Reserved HVBUC K1_OC_ EVT LVBUCK 2_OC_ EVT LVBUCK 3_OC_ EVT LDO1_ OC_EVT LDO2_ OC_EVT Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W W1C W1C W1C W1C W1C HVBUCK1_OC_EVT HVBuck1 overcurrent fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LVBUCK2_OC_EVT LVBuck2 overcurrent fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LVBUCK3_OC_EVT LVBuck3 overcurrent fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LDO1_OC_EVT LDO1 overcurrent fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected LDO2_OC_EVT LDO2 overcurrent fault event 0: No faults are detected, or faults are masked (default) 1: Fault is detected

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 30. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEV_ STAT 0x16 Meaning Reserved Reserved Reserved Reserved Reserved DEV_STATE Default 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R DEV_STATE Indicates the PMIC present state 000: Regulator-Off state or BIST state (default) 001: Standby state 010: Power-On state 011: Active state 100: Alarm state 101: Fail-Safe state Table 31. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP_ CRC_1 0x18 Meaning CRC_ START CRC_ FAIL CRC_ DONE CRC_ EN Reserved Reserved Reserved Reserved Default 0 0 0 1 0 0 0 0 Read/Write R/W R R R/W R/W R/W R/W R/W CRC_START For OTP CRC value calculation, the calculated value is displayed at 0x19 0: None (default) 1: Enable CRC_FAIL OTP CRC comparison result 0: None or CRC pass (default) 1: CRC fail CRC_DONE OTP CRC calculation process 0: None or calculating (default) 1: Calculation completed CRC_EN OTP CRC function 0: Disable 1: Enable (default) Table 32. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP_ CRC_2 0x19 Meaning OTP_CRC_RESULT Default 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R OTP_CRC_RESULT OTP CRC calculation value

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 33. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM_ PASS_ CODE1 0x20 Meaning TM_PASS_CODE1 Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TM_PASS_CODE1 To enter guest mode, set 0x20 = 8'h69 and 0x21 = 8'h96 sequentially To leave guest mode, set 0x20 ≠ 8'h69 or 0x21 ≠ 8'h96 Table 34. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM_ PASS_ CODE2 0x21 Meaning TM_PASS_CODE2 Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TM_PASS_CODE2 To enter guest mode, set 0x20 = 8'h69 and 0x21 = 8'h96 sequentially To leave guest mode, set 0x20 ≠ 8'h69 or 0x21 ≠ 8'h96 Table 35. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP34 0xE2 Meaning UV_LVCH OV_LVCH UV_DEG_LVCH OV_DEG_LVCH Default 0 1 0 1 0 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W UV_LVCH (Not in RTK P/N Options) LVBuck2, LVBuck3, LDO1 , and LDO2 UV detection threshold with respect to target voltage 00: 96.5% 01: 95% (default) 10: 94% 11: 90% OV_LVCH (Not in RTK P/N Options) LVBuck2, LVBuck3, LDO1 , and LDO2 OV detection threshold with respect to target voltage 00: 103.5% 01: 105% (default) 10: 106% 11: 110% UV_DEG_LVCH (Not in RTK P/N Options) LVBuck2, LVBuck3, LDO1, and LDO2 UV detection deglitch time selection 00: Reserved 01: 50s (default) 10: 75s 11: 100s OV_DEG_LVCH (Not in RTK P/N Options) LVBuck2, LVBuck3, LDO1, and LDO2 OV detection deglitch time selection 00: Reserved 01: 50s (default) 10: 75s 11: 100s

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 36. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP35 0xE3 Meaning OV_HVCH UVLO UVLO_ DEG CH_OV_ SD CH_UV_ SD REBOOT Default 0 1 0 0 0 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W OV_HVCH (Not in RTK P/N Options) HVBuck1 OV detection threshold with respect to the target voltage 00: 105% 01: 110% (default) 10: 115% 11: 120% UVLO VIN UVLO (falling/rising) voltage setting 00: 3.3V/3.8V (default) 01: 3.8V/4.5V 10: 4.3V/5.0V 11: 6.8V/7.3V UVLO_DEG (Not in RTK P/N Options) UVLO falling deglitch time setting 0: 32s (default) 1: 64s CH_OV_SD (Not in RTK P/N Options) HVBuck1, LVBuck2, LVBuck3, LDO1, and LDO2 overvoltage protection behavior selection 0: Only inform ECU of fault events 1: Channel latch-off and inform ECU of fault events (default) CH_UV_SD HVBuck1, LVBuck2, LVBuck3, LDO1 , and LDO2 undervoltage protection behavior selection 0: Only inform ECU of fault events (default) 1: Channel latch-off and inform ECU of fault events REBOOT (Not in RTK P/N Options) IC auto-reboot behavior selection when the PMIC enters a Fail-Safe state 0: Auto-reboot is disabled (default) 1: Auto-reboot is enabled (register keep)

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 37. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP36 0xE4 Meaning SEQ_ CTRL ON_Td OFF_Td POWER_ON_SEQ Default 1 0 0 1 0 0 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SEQ_CTRL (Not in RTK P/N Options) Sequence on and off control 0: Sequence off 1: Sequence on (default) ON_Td Delay time between power-on channel and its next channel 00: 0ms (default) 01: 0.5ms 10: 1ms 11: 2ms OFF_Td Delay time between power-off channel and its next channel 00: 1ms 01: 1.5ms 10: 2ms (default) 11: 3ms POWER_ON_SEQ Power-on sequence setting 000: SEQ0 001: SEQ1 (default) 010: SEQ2 011: SEQ3 100: SEQ4 101: SEQ5 110: SEQ6 111: SEQ7

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 38. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP37 0xE5 Meaning HVBUCK1_VOUT LVBUCK2_VOUT Default 1 0 0 1 0 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W HVBUCK1_VOUT HVBuck1 output voltage can be set from 2.7V to 4V (100mV/step), 4.5V, and 5.0V 0000: 2.7V 0001: 2.8V 0010: 2.9V 0011: 3.0V 0100: 3.1V 0101: 3.2V 0110: 3.3V 0111: 3.4V 1000: 3.5V 1001: 3.6V (default) 1010: 3.7V 1011: 3.8V 1100: 3.9V 1101: 4.0V 1110: 4.5V 1111: 5.0V LVBUCK2_VOUT LVBuck2 output voltage can be set from 0.9V to 1.4V (50mV/step) and 1.4V to 1.9V (100mV/step) 0000: 0.90V 0001: 0.95V 0010: 1.00V 0011: 1.05V 0100: 1.10V (default) 0101: 1.15V 0110: 1.20V 0111: 1.25V 1000: 1.30V 1001: 1.35V 1010: 1.40V 1011: 1.50V 1100: 1.60V 1101: 1.70V 1110: 1.80V 1111: 1.90V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DSQ2079-QF-00 October 2024 Table 39. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP38 0xE6 Meaning LVBUCK3_VOUT LDO1_VOUT Default 1 1 1 0 1 1 0 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LVBUCK3_VOUT LVBuck3 output voltage can be set from 0.9V to 1.4V (50mV/step) and 1.4V to 1.9V (100mV/step) 0000: 0.90V 0001: 0.95V 0010: 1.00V 0011: 1.05V 0100: 1.10V 0101: 1.15V 0110: 1.20V 0111: 1.25V 1000: 1.30V 1001: 1.35V 1010: 1.40V 1011: 1.50V 1100: 1.60V 1101: 1.70V 1110: 1.80V (default) 1111: 1.90V LDO1_VOUT LDO1 output voltage can be set from 1.8V and 2.7V to 3.4V (50mV/step) 0000: 1.80V 0001: 2.70V 0010: 2.75V 0011: 2.80V 0100: 2.85V 0101: 2.90V 0110: 2.95V 0111: 3.00V 1000: 3.05V 1001: 3.10V 1010: 3.15V 1011: 3.20V 1100: 3.25V 1101: 3.30V (default) 1110: 3.35V 1111: 3.40V

Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DSQ2079-QF-00 October 2024 www.richtek.com Table 40. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP39 0xE7 Meaning LDO2_VOUT VMON_DEG VMON_LEVEL VMON_ EN ADR Default 0 0 1 1 0 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W LDO2_VOUT LDO2 output voltage can be set from 1.8V, 2.5V, 2.9V and 3.3V 00: 1.8V (default) 01: 2.5V 10: 2.9V 11: 3.3V VMON_DEG (Not in RTK P/N Options) VMONIN deglitch time 00: 10s 01: 15s 10: 25s 11: 50s (default) VMON_LEVEL (Not in RTK P/N Options) VMON sensed voltage level can be set as follows 00: VMON_H/VMON_L = 1.33V/1.09V 01: VMON_H/VMON_L = 1.28V/1.14V (default) 10: VMON_H/VMON_L = 1.18V/1.02V 11: VMON_H/VMON_L = 0.96V/0.84V VMON_EN (Not in RTK P/N Options) VMONIN function 0: Disable (default) 1: Enable ADR (Not in RTK P/N Options) PMIC slave address 0: 75h (7bit) (default) 1: 76h (7bit) Table 41. Address Name Register Address Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OTP40 0xE8 Meaning CRC_B7 CRC_B6 CRC_B5 CRC_B4 CRC_B3 CRC_B2 CRC_B1 CRC_B0 Default 0 1 0 0 0 1 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W CRC_CODE After modifying the settings of OTP34 to OTP40, write the register 0x18[7] = 1. This action triggers the PMIC to automatically calculate a new CRC which is shown in the register 0x19. Enter the new CRC value into OTP40 to complete the PMIC BIST process successfully.

20 Outline Dimension

Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 b1 0.150 0.250 0.006 0.010 D 3.900 4.100 0.154 0.161 D2 2.650 2.750 0.104 0.108 E 3.900 4.100 0.154 0.161 E2 2.650 2.750 0.104 0.108 e 0.500 0.020 L 0.300 0.400 0.012 0.016 L1 0.330 0.430 0.013 0.017 R 0.050 0.150 0.002 0.006 S 0.001 0.090 0.000 0.004 WET W-Type 24AL QFN 4x4 Package

21 Footprint Information

(mm) ±0.050

22 Packing Information

22.1 Tape and Reel Data

(W1) (mm) Pocket Pitch (P) (mm) Reel Size (A) Units per Reel Trailer (mm) Leader (mm) Reel Width (W2) Min./Max. (mm) (mm) (in) (V, W) QFN/DFN 4x4 12 8 180 7 1,500 160 600 12.4/14.4 Tape Size W1 P B F ØJ K H C, D, and K are determined by component size. The clearance between the components and the cavity is as follows: - For 12mm carrier tape: 0.5mm max.

22.2 Tape and Reel Packing

Step Photo/Description Step Photo/Description Reel 7” 3 reels per inner box Box A HIC & Desiccant (1 Unit) inside 12 inner boxes per outer box Caution label is on backside of Al bag Outer box Carton A Container Package Reel Box Carton Size Units Item Reels Units Item Boxes Unit (V, W) QFN/DFN 4x4 7” 1,500 Box A 3 4,500 Carton A 12 54,000 Box E 1 1,500 For Combined or Partial Reel.

22.3 Packing Material Anti-ESD Property

Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is curre nt and complete. Rich tek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidi aries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiar ies. Surface Resistance Aluminum Bag Reel Cover tape Carrier tape Tube Protection Band /cm2 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011

23 Datasheet Revision History

Version Date Description Item 00 2024/10/9 Final Packing Information on page 80 - Updated Tape and Reel Data

Product Information

BAS316 specifications and overview.

Summary

Functional Safety PMIC for Automotive Camera Sensors/ Modules October 2024

Description

Functional Safety PMIC for Automotive Camera Sensors/ Modules October 2024

Source title BAS316 Datasheet(PDF) - Richtek Technology Corporation

Related Parts

More parts from the same family.

Browse manufacturer