UPB1009K-E1-A

UPB1009K CEL | Alldatasheet

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Technical content

DESCRIPTION

The µPB1009K is a silicon monolithic IC developed for GPS receivers. This IC integrates a full VCO, second IF filter, 4-bit ADC, and digital control interface to reduce cost and mounting space. In addition, its power consumption is low. Moreover, use of a TCXO with frequency of 16.368 MHz/16.384 MHz, 14.4 MHz, 19.2 MHz, or 26 MHz switchable with an on-chip divider is possible. NEC’s stringent quality assurance and test procedures ensure the highest reliability and performance.

FEATURES

• Double conversion : fREFin = 16.368 MHz, f1stIFin = 61.380 MHz, f2ndIFin = 4.092 MHz
• Multiple system clocks : On-chip switchable frequency divider (1/N = 100, 3/256, 9/1024, 65/4096)
• A/D converter : On-chip 4-bit A/D converter
• High-density RF block : On-chip VCO tank circuit and 2ndIF filter
• Supply voltage : VCC = 2.7 to 3.3 V
• Low current consumption : ICC = 26.0 mA TYP. @ VCC = 3.0 V, N = 100
• High-density surface mountable : 44-pin plastic QFN

APPLICATIONS

• Consumer use GPS receiver of reference frequency 16.368 MHz, 2nd IF frequency 4.092 MHz
• Consumer use GPS receiver of reference frequency 14.4, 16.384, 19.2, 26 MHz, 2ndIF frequency 2.556 MHz UPB1009K NEC’s LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT

ORDERING INFORMATION

Part Number Package Supplying Form µPB1009K-E1-A 44-pin plastic QFN • 12 mm wide embossed taping

• Pin 1 indicates pull-out direction of tape
• Qty 1.5 kpcs/reel, Dry pack specification Remark To order evaluation samples, contact your nearby sales office. Part number for sample order: µPB1009K UPB1009K

PRODUCT LINE-UP (TA = +25°C, VCC = 3.0 V) Type Part Number Functions (Frequency unit: MHz) VCC (V) ICC (mA) CG (dB) Package Status µPB1009K Pre-amplifier + RF/IF down- converter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 REF = 14.4, 16.384, 19.2, 26 1stIF = 62.980/2ndIF = 2.556 On-chip 4-bit ADC 2.7 to 3.3 26.0 44-pin plastic QFN New Device µPB1008K LNA + Pre-amplifier + RF/IF down-converter + PLL synthesizer REF = 27.456 1stIF = 175.164/2ndIF = 0.132 On-chip 2-bit ADC 2.7 to 3.3 18.0 100 to 120 36-pin plastic QFN µPB1007K Pre-amplifier + RF/IF down- converter + PLL synthesizer REF = 16.368 1stIF = 61.380/2ndIF = 4.092 36-pin plastic QFN Clock Frequency Specific 1 chip IC µPB1005K REF = 16.368 1stIF = 61.380/2ndIF = 4.092 2.7 to 3.3 25.0 100 to 120 36-pin plastic QFN Available Remark Typical performance. Please refer to ELECTRICAL CHARACTERISTICS in detail. SYSTEM APPLICATION EXAMPLE GPS receiver RF block diagram PD1 and PD2 in the figure are Power Save Mode control pins. MS1 and MS2 in the figure are TXCO (GPS, W-CDMA, PDC, GSM) control pins. Caution This diagram schematically shows only the µPB1009K’s internal functions on the system. This diagram does not present the actual application circuits. UPB1009K

PIN CONNECTION AND INTERNAL BLOCK DIAGRAM UPB1009K

No. Pin Name Function and Application Internal Equivalent Circuit 1 PreAMPout Output pin of preamplifier.

2 Rext Connect a resistor for the reference constant-

current power supply to this pin. Ground this pin at 22 kΩ. 3 RegGND Ground pin for regulator. 42 PreAmpVCC Power supply voltage pin for preamplifier. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 43 PreAmpGND Ground pin of preamplifier. 44 PreAmpin Input pin of preamplifier. 4 1stMIXin 1stMIX input pin. 5 1stMIXGND Ground pin for first MIX. 40 1stMIXVCC Power supply voltage pin for RF mixer. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 41 1stIFout Output pin of RF mixer. Insert an IFSAW filter between this pin and pin 37. The VCO oscillation signal can be monitored on this pin. UPB1009K

No. Pin Name Function and Application Internal Equivalent Circuit MS1 : L MS2 : L TCXO : 16.368,

16.384 MHz

MS1 : L MS2 : H TCXO : 19.2 MHz MS1 : H MS2 : L TCXO : 14.4 MHz MS1 MS2 Low : 0 to 0.3 (V) High : VCC − 0.3 to VCC (V) MS1 : H MS2 : H TCXO : 26 MHz 11 CPout Output pin of charge pump. Connect external R and C to this pin to set a dumping factor and natural angular frequency (Isink = Isource = 0.45 mA). 13 Refin Reference frequency input pin. Connect an external reference transmitter (such as TCXO) to this pin. 14 PLLVCC Power supply voltage pin of PLL. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. 15 PLLGND Ground pin of PLL. 16 CLKout Clock (fTCXO) output pin (IC test pin). UPB1009K

No. Pin Name Function and Application Internal Equivalent Circuit 7 LoVCC Power supply voltage pin of VCO. Connect a bypass capacitor to this pin to reduce the high-frequency impedance. VCO1 VCO2 IC test pin. Leave this pin open when the µPB1009K is mounted on board. 10 LoGND Ground pin of VCO. 17 IFGND Ground pin of IF block. 18 2ndIFout Output pin of IF amplifier. 38 1stIFin Input pin of second IF mixer. 39 IFVCC Power supply voltage pin of IF block. UPB1009K

No. Pin Name Function and Application Internal Equivalent Circuit 19 2ndIFin Input pin of ADC buffer amplifier. 20 DCOFFout Output pin of DC trimming OP amplifier. 21 DCOFFin DC trimming pulse input pin. Connect this pin to pin 20 via a capacitor to convert an input pulse signal into DC. GNDana GNDbuf Ground pin for OP amplifier and ADC power supply.

24 VDDana Power supply pin for OP amplifier and ADC

comparator.

25 VDDbuf Power supply pin for output driver amplifier of

ADC. Connect this pin to the ground pin of the A/D converter via a bypass capacitor to reduce the high-frequency impedance. 26 GNDsub Ground pin of CMOS substrate. Digital signal output pins. LSB = D0, MSB = D3 31 SCKin Sampling clock signal input pin. 32 AGCin AGC control pulse signal input pin. 33 AGCout AGC control signal output pin. UPB1009K

No. Pin Name Function and Application Internal Equivalent Circuit

34 VDDlogi Power supply voltage pin for power control

logic. 35 GNDlogi Ground pin for power control logic. PD1 : L PD2 : L Sleep mode (all circuits off). PD1 : L PD2 : H Warm-up mode (PLL on). PD1 : H PD2 : L Calibration mode PD1 PD2 Low : 0 to 0.3 (V) High : VCC − 0.3 to VCC (V) PD1 : H PD2 : H Active mode (all circuits on). UPB1009K

Parameter Symbol Test Conditions Ratings Unit Supply Voltage VCC TA = +25°C 3.6 V Total Circuit Current ICCTotal TA = +25°C 100 mA Power Dissipation PD TA = +25°C Note 266 mW Operating Ambient Temperature TA −40 to +85 °C Storage Temperature Tstg −55 to +125 °C Note Mounted on double-sided copper-clad 50 × 50 × 1.6 mm epoxy glass PWB RECOMMENDED OPERATING RANGE Parameter Symbol MIN. TYP. MAX. Unit Supply Voltage VCC 2.7 3.0 3.3 V Operating Ambient Temperature TA −30 +25 +85 °C RF Input Frequency fRFin − 1 575.42 − MHz 1st LO Oscillating Frequency f1stLOin − 1 636.8/1 638.4 − MHz 1st IF Input Frequency f1stIFin − 61.38/62.98 − MHz 2nd LO Input Frequency f2ndLOin − 65.472/65.536 − MHz 2nd IF Input Frequency f2ndIFin − 4.092/2.556 − MHz Reference Input/Output Frequency fREFin fREFout − TCXO − MHz Clock mode control voltage (Low Level) VIL1 0 − 0.3 V Clock mode control voltage (High Level) VIH1 VCC − 0.3 − VCC V Power-down control voltage (Low Level) VIL2 0 − 0.3 V Power-down control voltage (High Level) VIH2 VCC − 0.3 − VCC V UPB1009K

The µPB1009K consists of an RF block, an IF block, and a PLL block. By controlling reduction of power to each block (by applying a voltage to the PD1 and PD2 pins), the following four modes can be used. Test ConditionsMode No. Mode Name PD1 PD2 RF Block IF Block (IF + ADC) PLL Block

1 Active mode L H ON ON ON

2 Calibration mode H H OFF ON ON

3 Warm-up mode H L OFF OFF ON

4 Sleep mode L L OFF OFF OFF

Caution To use only the active mode and sleep mode, fix PD1 to L and select the desired mode with PD2. REFERENCE CLOCK CONTROL MODE The divided frequency can be selected as follows so that it can be shared with the TCXO of each system. Test ConditionsTCXO Frequency PD1 PD2 1/N Phase Comparison Frequency

16.368 MHz (GPS)

16.384 MHz (GPS)

L L 1/100 16.368 MHz 19.2 MHz (W-CDMA) L H 3/256 19.2 MHz 14.4 MHz (PDC) H L 9/1024 14.4 MHz

26 MHz (GSM) H H 65/4096 26 MHz

Caution When the reference clock frequency is 16.368 MHz, the 1stIF frequency and 2ndIF frequency are 61.38 MHz and 4.092 MHz, respectively. They are respectively 62.98 MHz and 2.556 MHz in all other cases. UPB1009K

ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Rest current of overall IC in each mode Rest status without input signal, including sampling clock. MS1 = L, MS2 = L Sleep mode Note Is PD1 = L, PD2 = L 1.3 2.2 3.5 mA Warm-up mode Iw PD1 = H, PD2 = L 10.5 13.0 15.5 mA Calibration mode Ic PD1 = H, PD2 = H 18.0 22.0 25.3 mA Active mode Ia PD1 = L, PD2 = H 22.1 26.0 30.0 mA Rest current of PLL block in each clock mode Current of PLL block. Overall current in calibration mode and active mode increases from that in basic mode (MS1 = L, MS2 = L). PD1 = H, PD2 = L. Current when 1/100 divider is used Iw1 MS1 = L, MS2 = L 5.3 6.5 7.6 mA Current when 256/3 divider is used Iw2 MS1 = L, MS2 = H 9.7 11.3 12.6 mA Current when 1024/9 divider is used Iw3 MS1 = H, MS2 = L 10.2 12.1 13.5 mA Current when 4096/65 divider is used Iw4 MS1 = H, MS2 = H 10.4 12.3 13.9 mA Maximum mode control pin current H application − − 20 µA6 pin MS1 L application −20 − − µA H application − − 20 µA12 pin MS2 L application −20 − − µA H application − − 1 µA36 pin PD1 L application −1 − − µA H application − − 1 µA37 pin PD2 L application −1 − − µA <Pre-amplifier> fRFin = 1 575.42 MHz Circuit Current 1 ICC1 No Signals, 1-pin current 1.9 2.3 2.7 mA Power Gain GLNA PRFin = −40 dBm 12.5 15.0 17.5 dB Noise Figure NFLNA fRFin = 1 575 MHz − 3.0 3.5 dB Saturated Output Power PO(SAT)LNA PRFin = −10 dBm −4.0 −2.7 − dBm Input 1dB Compression Level PLNA−1 fRFin = 1 575.42 MHz −25 −21.8 − dBm Input 3rd Order Intercept Point IIP3LNA fRFin = 1 575.42 MHz, 1 576.42 MHz −12 −9.5 − dBm Input Inpedance ZinLNA − 11.2 − j21.5 − Ω Output Inpedance ZoutLNA Calculated from S-parameter where input DC cut capacitance = 1 nF, output load L = 100 n, and DC cut capacitance = 1 nF − 16.4 − j136.6 − Ω Note Most of the current flows into the ADC ladder resistor (VDDana ♦ GNDana) in the sleep mode, and the sleep mode current between other VCC (VDD) and GND is 10 µA maximum. UPB1009K

ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit <RF mixer> fRF = 1 575.42 MHz, f1stLOin = 1 636.80 MHz, f1stIF = 61.38 MHz Circuit Current 2 ICC2 No Signals, 40 pin current 2.0 2.5 3.0 mA RF Conversion Gain CGRF PRFMIXin = −40 dBm 14.0 16.1 19.0 dB Noise Figure SSBNF = 10*log (2*DSBNF (Linear value) −1) MHz − 12.8 16.0 dB Maximum IF Output PRFMIXin = −10 dBm −4.0 −0.8 − dBm Input 1dB Compression Level PRFMIX-1 fRFMIXin = 1 575.42 MHz −29.0 −25.5 − dBm Input 3rd Order Intercept Point IIP3RFMIX fRFMIXin = 1 575.42 MHz, 1 576.42 MHz f1stLO = 1 636.8 MHz −19.0 −17.2 − dBm LO Leakage to IF Pin LOIF − −34.5 −30 dBm LO Leakage to RF Pin LORF Leakage of 1 636.8 MHz frequency when VCO oscillates correctly. − −54.7 −30 dBm Input Inpedance ZinMIX − 50.1 − j22.3 − Ω Output Inpedance ZoutMIX Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 1 nF − 57.3 + j2.6 − Ω <IF mixer, LPF, IFamp> f1stFin = 61.38 MHz, f2ndLOin = 65.472 MHz, ZL = 2 kΩ Circuit Current 3 ICC3 No Signals, 39 pin current 6.3 7.3 8.5 mA VAGC = 0.5 V 66.0 70.3 75.0 dB VAGC = 1.5 V 45.0 51.2 58.0 dB IF Conversion Gain CG (GV) IF VAGC = 2.5 V 19.5 26.4 33.5 dB In Band Gain Fluctuation ΔCG1 3.092 to 5.092 MHz − 0.7 1.0 dB Out Of Band Attenuation ΔCG2 Gain difference at 4.092 MHz and 9.092 MHz, VAGC = 0.5 V 20.0 25.0 − dB Conversion Gain Range CGRange VAGC = 0 to 2.5 V 32.5 43.9 − dB IF ⋅ SSB Noise Figure NFIF VAGC = 0.5 V (at maximum gain) − 13.7 17.5 dB Maximum 2ndIF Output V Pin = −50 dBm, VAGC = 0.5 V 1.0 1.3 − VPP VAGC = 0.5 V −70.5 −64.4 − dBm VAGC = 1.5 V −53.5 −44.9 − dBm Input 1dB Compression Level PIF-1 f1stIFin = 61.38 MHz VAGC = 2.5 V −37.0 −30.6 − dBm VAGC = 0.5 V −56.0 −51.3 − dBm VAGC = 1.5 V −38.0 −30.7 − dBm Input 3rd Order Intercept Point IIP3IF f1stIFin1 = 61.28 MHz f1stIFin2 = 61.38 MHz f2ndLO = 65.472 MHz VAGC = 2.5 V −27.0 −21.4 − dBm Input Inpedance ZinIF − 69.3 − j4.8 − Ω Output Inpedance ZoutIF Calculated from S-parameter where input DC cut capacitance = 1 nF and output DC cut capacitance = 100 nF − 163 + j3.8 − Ω UPB1009K

ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit <PLL Synthesizer> Circuit Current 4 ICC4 PLL, VCO current, MS1 = L, MS2 = L 8.0 9.5 10.6 mA Icpsink −0.55 −0.45 −0.35 mACharge Pump Output Current Icpsource V13 pin = VCC/2 0.35 0.45 0.55 mA Loop Filer Output (High Level) VCC−0.3 − − V Loop Filer Output (Low Level) − − 0.2 V Reference Input Level VREFin − 0.2 1.6 VPP VCO Modulation Sensitivity KV Center frequency − 100 − MHz VCO Control Voltage VT When PLL is Locked 0.5 1.3 2.0 V C/N C/N Δ10 kHz 70.0 81.0 − dBc/Hz <A/D Converter> Circuit Current 5 ICC5 3.1 4.1 5.4 mA Resolution ResAD − 4 − bits Sampling Clock fs − − 20 MHz Input Band Width ADBW 5.1 − − MHz Integral Non-linear Error INL DC characteristics − 0.2 1.0 LSB Signal-to-noise Ratio SNR IF = 5.17 MHz, fs = 20.48 MHz 22.0 25.3 − dB Signal-to-noise + Distortion Ratio SINAD IF = 5.17 MHz, fs = 20.48 MHz 20.0 25.1 − dB Number ENOB ENOB = (SINAD−1.763)/6.02 3.0 3.9 − bits Total Harmonic Distortion Ratio THD IF = 5.17 MHz, fs = 20.48 MHz Second-degree to fifth-degree distortion components − −40 −30 dBc Remarks 1. Timing characteristics of ADC during normal operation A buffer amplifier is internally inserted before the ADC core of the µPB1009K. The bias of this buffer amplifier is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC. Because the ladder resistor of the ADC is directly connected between VDDana and GNDana, changes in VDDana affect the resolution of the ADC. UPB1009K

As illustrated in the operation timing chart below, the data of SampleN is pipeline delayed by 1.5 clocks during normal operation, and is output at the rising edge of the sample clock with output delay time Tod. When the operation is changed from normal operation to power-down operation, the status of the output data immediately before the power-down operation is retained (drive status). The following table shows each timing parameter for reference purposes. Symbol Parameter Test Conditions MIN. TYP. MAX. Unit Tod Output Delay CL = 10 pF, fclk = 19.2 MHz − − 12 ns Tpld Pipeline Delay − 1.5 − clock Tds Sampling Delay (Aperture Delay) − 2 − ns Toh Output Hold Time 2 − − ns UPB1009K

Remarks 2. Power-down timing characteristics of ADC The output code of the ADC of the µPB1009K is undefined for 7.5 clocks after the power-down signal is cleared when the ADC returns from the power-down status to normal operation. Note The output data is undefined from the start of the power-down operation to the 7.5th clock from the falling edge of the clock at which the power-down operation is cleared. UPB1009K

TYPICAL CHARACTERISTICS (TA = +25°C, VCC = 3.0 V, unless otherwise specified)  IC TOTAL CHARACTERISTICS  Remark The graphs indicate nominal characteristics. UPB1009K

 PRE-AMPLIFIER BLOCK CHARACTERISTICS  Remark The graphs indicate nominal characteristics. UPB1009K

 RF MIX BLOCK CHARACTERISTICS  Remark The graphs indicate nominal characteristics. UPB1009K

 IF BLOCK CHARACTERISTICS  Remark The graphs indicate nominal characteristics. UPB1009K

 VCO MODULATION SENSITIVITY CHARACTERISTICS   C/N CHARACTERISTICS  Remark The graphs indicate nominal characteristics. UPB1009K

 SINAD CHARACTERISTICS OF A/D CONVERTOR (IFin = 5.17 MHz, SCLKin = 20.48 MHz)  Remark The graphs indicate nominal characteristics. UPB1009K

DESCRIPTION OF PINS OF TEST CIRCUIT Pin No. Pin Function Pin Name Pin No. Pin Function Pin Name

1 Preamplifier Input PreAmpin 14 DC Offset Input DCOFFin

2 Preamplifier Output PreAmpout 15 Digital Signal Output Pin D0

3 RF Mixer Input 1stMIXin 16 D1

4 MS1 MS1 17 D2

5 Prescaler Input Presin 18 D3

6 VCO Power Control Pin VCOc 19 Sampling Signal Input SCKin

7 VT Measurement Pin (Charge Pump

Output) CPout 20 AGC Input AGCin

8 MS2 MS2 21 AGC Control Voltage Output AGCout

9 Reference Clock Input REFin 22 PD1 Output (Default onboard : GND) PD1

10 Clock Output CLKout 23 PD1 Output (Default on board : VCC) PD2

11 2ndIF Output 2ndIFout 24 1stIF Input 1stIFin 12 2ndIF Input 2ndIFin 25 1stIF Output 1stIFout

13 DC Offset Output DCOFFout

PD1 PD2 Power-down mode MS1 MS2 TCXO N 0 0 Sleep mode (full off) 0 0 16.368/16.384 MHz 100 1 0 Warm-up mode (PLL on) 0 1 19.2 MHz 256/3 1 1 Calibration mode (PLL on) 1 0 14.4 MHz 1024/9 0 1 Active mode (full on) 1 1 26.0 MHz 4096/65 UPB1009K

44-PIN PLASTIC QFN (UNIT: mm) Caution The island pins located on the corners are needed to fabricate products in our plant, but do not serve any other function. Consequently the island pins should not be soldered and should remain non-connection pins. UPB1009K

(1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as widely as possible to minimize ground impedance (to prevent abnormal oscillation). (3) Keep the wiring length of the ground pins as short as possible. (4) Connect a bypass capacitor to the VCC pin. (5) High-frequency signal I/O pins must be coupled with the external circuit using a coupling capacitor. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Soldering Conditions Condition Symbol Infrared Reflow Peak temperature (package surface temperature) : 260°C or below Time at peak temperature : 10 seconds or less Time at temperature of 220°C or higher : 60 seconds or less Preheating time at 120 to 180°C : 120±30 seconds Maximum number of reflow processes : 3 times Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below IR260 VPS Peak temperature (package surface temperature) : 215°C or below Time at temperature of 200°C or higher : 25 to 40 seconds Preheating time at 120 to 150°C : 30 to 60 seconds Maximum number of reflow processes : 3 times Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below VP215 Wave Soldering Peak temperature (molten solder temperature) : 260°C or below Time at peak temperature : 10 seconds or less Preheating temperature (package surface temperature) : 120°C or below Maximum number of flow processes : 1 time Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below WS260 Partial Heating Peak temperature (pin temperature) : 350°C or below Soldering time (per side of device) : 3 seconds or less Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below HS350 Caution Do not use different soldering methods together (except for partial heating). UPB1009K

4590 P a t r ick Hen r y Drive

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