UF3SC065007K4S

UF3SC065007K4S UNITEDSIC | Alldatasheet

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w Typical on-resistance RDS(on),typ of 6.7mW w Maximum operating temperature of 175°C w Excellent reverse recovery w Low gate charge w Low intrinsic capacitance Part Number Marking UF3SC065007K4S UF3SC065007K4S w ESD protected, HBM class 2 w Induction heating w TO-247-4L package for faster switching, clean gate waveforms w EV charging w PV inverters w Switch mode power supplies w Power factor correction modules w Motor drives This SiC FET device is based on a unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device’s standard gate-drive characteristics allows for a true “drop-in replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction devices. Available in the TO-247-4L package, this device exhibits ultra- low gate charge and exceptional reverse recovery characteristics, making it ideal for switching inductive loads , and any application requiring standard gate drive. 650V-6.7mW SiC FET DATASHEET UF3SC065007K4S CASE D (1) S (2) G (4) KS (3) CASE 1 2 4 Datasheet: UF3SC065007K4S Rev. B, December 2019 1

TJ,max 175 °C TJ, TSTG -55 to 175 °C TL 250 °C 1. Limited by bondwires 2. Pulse width tp limited by TJ,max 3. Starting TJ = 25°C Thermal Characteristics Min Typ Max RqJC 0.15 0.19 °C/W Parameter Test Conditions Drain-source voltage L=15mH, IAS =8.6A Continuous drain current 1 Gate-source voltage DC Max. lead temperature for soldering, 1/8” from case for 5 seconds Power dissipation TC = 25°C Maximum junction temperature Operating and storage temperature TC < 135°C Pulsed drain current 2 TC = 25°C Single pulsed avalanche energy 3 UnitsParameter Symbol Test Conditions Value Thermal resistance, junction-to-case Datasheet: UF3SC065007K4S Rev. B, December 2019 2

Electrical Characteristics (TJ = +25°C unless otherwise specified) Typical Performance - Static Min Typ Max BVDS 650 V 7 600 IGSS 5 20 mA 6.7 9 8.8 VG(th) 4 4.7 6 V RG 0.8 1.5 W Typical Performance - Reverse Diode Min Typ Max IS 120 A IS,pulse 550 A 1.31 1.5 1.4 Qrr 856 nC trr 53 ns Qrr 865 nC trr 35 ns Total gate leakage current VDS=0V, TJ=25°C, VGS=-20V / +20V VGS=12V, ID=50A, TJ=25°C VGS=12V, ID=50A, TJ=175°C Drain-source breakdown voltage VGS=0V, ID=1mA VDS=650V, VGS=0V, TJ=25°C VDS=650V, VGS=0V, TJ=175°C Parameter Symbol Test Conditions Value Units mATotal drain leakage current IDSS Forward voltage VFSD VGS=0V, IF=80A, TJ=25°C V VGS=0V, IF=80A, TJ=175°C Diode continuous forward current 1 TC < 135°C Diode pulse current 2 TC=25°C Drain-source on-resistance RDS(on) mW Parameter Symbol Test Conditions Value Units Gate threshold voltage VDS=5V, ID=10mA Gate resistance f=1MHz, open drain VGS=12V, ID=50A, TJ=125°C Reverse recovery charge Reverse recovery time VR=400V, IF=80A, VGS=-5V, RG_EXT=10W di/dt=1400A/ms, TJ=25°C Reverse recovery charge VR=400V, IF=80A, VGS=-5V, RG_EXT=10W di/dt=1400A/ms, TJ=150°CReverse recovery time Datasheet: UF3SC065007K4S Rev. B, December 2019 3

Typical Performance - Dynamic Min Typ Max Ciss 8360 Coss 1190 Crss 11.3 Coss(er) 856 pF Coss(tr) 1806 pF Eoss 69 mJ QG 214 QGD 28 QGS 96 td(on) 36 tr 46 td(off) 72 tf 14 EON 925 EOFF 83 ETOTAL 1008 td(on) 38 tr 47 td(off) 75 tf 14 EON 1081 EOFF 105 ETOTAL 1186 Value Units Reverse transfer capacitance Effective output capacitance, energy related VDS=0V to 400V, VGS=0V pF Parameter Symbol Test Conditions Input capacitance Output capacitance VDS=100V, VGS=0V f=100kHz Effective output capacitance, time related VDS=0V to 400V, VGS=0V COSS stored energy VDS=400V, VGS=0V mJ ns Turn-off energy Fall time Turn-on energy VDS=400V, ID=80A, Gate Driver =-5V to +15V, Turn-on RG,EXT=1.5W, Turn-off RG,EXT=5W Inductive Load, FWD: same device with VGS = -5V, RG = 10W, TJ=25°C Turn-on delay time Rise time Turn-off delay time Gate-source charge Gate-drain charge VDS=400V, ID=80A, VGS = -5V to 15V nC Total gate charge Total switching energy Turn-on delay time VDS=400V, ID=80A, Gate Driver =-5V to +15V, Turn-on RG,EXT=1.5W, Turn-off RG,EXT=5W Inductive Load, FWD: same device with VGS = -5V, RG = 10W, TJ=150°C ns Rise time Turn-off delay time Fall time Turn-on energy mJTurn-off energy Total switching energy Datasheet: UF3SC065007K4S Rev. B, December 2019 4

Typical Performance - Dynamic (continued) Min Typ Max td(on) 36 tr 37 td(off) 72 tf 14 EON 545 EOFF 82 ETOTAL 627 td(on) 34 tr 40 td(off) 79 tf 14 EON 555 EOFF 84 ETOTAL 639 Turn-off energy Total switching energy Turn-on delay time VDS=400V, ID=80A, Gate Driver =-5V to +15V, Turn-on RG,EXT=1.5W, Turn-off RG,EXT=5W Inductive Load, FWD:UJ3D065030TS TJ=150°C ns Rise time Turn-off delay time Fall time Turn-on energy mJTurn-off energy Total switching energy Parameter Symbol Test Conditions Value Units Turn-on delay time VDS=400V, ID=80A, Gate Driver =-5V to +15V, Turn-on RG,EXT=1.5W, Turn-off RG,EXT=5W Inductive Load, FWD: UJ3D065030TS TJ=25°C ns Rise time Turn-off delay time Fall time Turn-on energy mJ Datasheet: UF3SC065007K4S Rev. B, December 2019 5

UnitedSiC assumes no liability whatsoever relating to the choice, selection or use of the UnitedSiC products and services described herein. SiC FETs are enhancement-mode power switches formed by a high- voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Information on all products and contained herein is intended for description only. No license, express or implied, to any intellectual property rights is granted within this document. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com. UnitedSiC reserves the right to change or modify any of the products and their inherent physical and technical specifications without prior notice. UnitedSiC assumes no responsibility or liability for any errors or inaccuracies within. Datasheet: UF3SC065007K4S Rev. B, December 2019 12