TPH3205WSBQA TRANSPHORM | Alldatasheet
Document overview
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Technical content
Features
JEDEC and AEC-Q101 qualified GaN technology Dynamic RDS(on)eff production tested Robust design, defined by — Intrinsic lifetime tests — Wide gate safety margin — Transient over-voltage capability Very low QRR Reduced crossover loss RoHS compliant and Halogen-free packaging Benefits Enables AC-DC bridgeless totem-pole PFC designs — Increased power density — Reduced system size and weight — Overall lower system cost Achieves increased efficiency in both hard- and soft- switched circuits Easy to drive with commonly-used gate drivers GSD pin layout improves high speed design
Applications
Automotive Datacom Broad industrial PV inverter Servo motor Key Specifications VDSS (V) 650 V(TR)DSS (V) 800 RDS(on)eff (mΩ) max* 62 QRR (nC) typ 136 QG (nC) typ 28 * Dynamic on-resistance; see Figures 19 and 20 Cascode Device Structure Cascode Schematic Symbol A ll data sheet.com
November 22, 2017 transphormusa.com tph3205wsbqa.1 2 TPH3205WSBQA Thermal Resistance Symbol Parameter Typical Unit RΘJC Junction-to-case 1 °C/W RΘJA Junction-to-ambient 40 °C/W Absolute Maximum Ratings (Tc=25°C unless otherwise stated.) Symbol Parameter Limit Value Unit VDSS Drain to source voltage (TJ = -55°C to 150°C) 650 V V(TR)DSS Transient drain to source voltage a 800 VGSS Gate to source voltage ±18 PD Maximum power dissipation @TC=25°C 125 W ID Continuous drain current @TC=25°C b 35 A Continuous drain current @TC=100°C b 22 A IDM Pulsed drain current (pulse width: 10µs) 150 A (di/dt)RDMC Reverse diode di/dt, repetitive c 1500 A/µs (di/dt)RDMT Reverse diode di/dt, transient d 2900 A/µs TC Operating temperature Case -55 to +150 °C TJ Junction -55 to +150 °C TS Storage temperature -55 to +150 °C TSOLD Soldering peak temperature e 260 °C Notes: a. In off-state, spike duty cycle D<0.01, spike duration <1µs b. For increased stability at high current operation, see Circuit Implementation on page 3 c. Continuous switching operation d. ≤300 pulses per second for a total duration ≤20 minutes e. For 10 sec., 1.6mm from the case A ll data sheet.com
November 22, 2017 transphormusa.com tph3205wsbqa.1 3 TPH3205WSBQA Circuit Implementation Recommended gate drive: (0V, 8-10V) with RG(tot) = 15Ω, where RG(tot) = RG + RDRIVER Simplified Half-bridge Schematic Efficiency vs Output Power Required DC Link RC Snubber (RCDCL) a Recommended Switching Node RC Snubber (RCSN) b, c [10nF + 8Ω] x 2 100pF + 10Ω Notes: a. RCDCL should be placed as close as possible to the drain pin b. A switching node RC snubber (C, R) is recommended for high switching currents (>70% of I RDMC1 or IRDMC2; see page 5 for IRDMC1 and IRDMC2) c. I RDM values can be increased by increasing RG and CSN A ll data sheet.com
November 22, 2017 transphormusa.com tph3205wsbqa.1 4 TPH3205WSBQA Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Forward Device Characteristics V(BL)DSS Drain-source voltage 650 — — V VGS=0V VGS(th) Gate threshold voltage 1.6 2.1 2.6 V VDS=VGS, ID=0.7mA RDS(on)eff Drain-source on-resistance a — 49 62 mΩ VGS=8V, ID=22A — 105 — VGS=8V, ID=22A, TJ=150°C IDSS Drain-to-source leakage current — 4 40 µA VDS=650V, VGS=0V — 50 — VDS=650V, VGS=0V, TJ=150°C IGSS Gate-to-source forward leakage current — — 100 nA VGS=18V Gate-to-source reverse leakage current — — -100 VGS=-18V CISS Input capacitance — 2200 — pF VGS=0V, VDS=400V, f=1MHz COSS Output capacitance — 135 — CRSS Reverse transfer capacitance — 23 — CO(er) Output capacitance, energy related b — 190 — pF VGS=0V, VDS=0V to 400V CO(tr) Output capacitance, time related c — 300 — QG Total gate charge — 28 42 nC VDS=400V, VGS=0V to 8V, ID=22A QGS Gate-source charge — 10 — QGD Gate-drain charge — 6 — QOSS Output charge — 107.4 — nC VGS=0V, VDS=0V to 400V tD(on) Turn-on delay — 36 — ns VDS=400V, VGS=0V to 8V, ID=22A, RG=10Ω tR Rise time — 7.6 — tD(off) Turn-off delay — 40 — tF Fall time — 8.6 — Notes: a. Dynamic on-resistance; see Figures 19 and 20 for test circuit and conditions b. Equivalent capacitance to give same stored energy as V DS rises from 0V to 400V c. Equivalent capacitance to give same charging time as V DS rises from 0V to 400V A ll data sheet.com
November 22, 2017 transphormusa.com tph3205wsbqa.1 5 TPH3205WSBQA Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Reverse Device Characteristics IS Reverse current — — 22 A VGS=0V, TC=100°C, ≤25% duty cycle VSD Reverse voltage a — 2.0 2.4 V VGS=0V, IS=22A — 1.5 1.7 VGS=0V, IS=11A tRR Reverse recovery time — 40 — ns IS=22A, VDD=400V, di/dt=1000A/s QRR Reverse recovery charge — 136 — nC (di/dt)RDMC Reverse diode di/dt, repetitive b — — 1500 A/µs IRDMC1 Reverse diode switching current, repeti- tive (dc) c, e — — 23 A Circuit implementation and parameters on page 3 IRDMC2 Reverse diode switching current, repeti- tive (ac) c, e — — 27 A Circuit implementation and parameters on page 3 (di/dt)RDMT Reverse diode di/dt, transient d — — 2900 A/µs IRDMT Reverse diode switching current, transi- ent d,e — — 35 A Circuit implementation and parameters on page 3 Notes: a. Includes dynamic R DS(on) effect b. Continuous switching operation c. Definitions: dc = dc- to-dc converter topologies; ac = inverter and PFC topologies, 50-60Hz line frequency d. ≤300 pulses per second for a total duration ≤20 minutes e. I RDM values can be increased by increasing RG and CSN on page 3 A ll data sheet.com
November 22, 2017 transphormusa.com tph3205wsbqa.1 11 TPH3205WSBQA Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switche s requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The table below provides some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Minimize lead length of TO-220 and TO-247 package when mounting to the PCB Use long traces in drive circuit, long lead length of the devices Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points Use differential mode probe or probe ground clip with long wire See AN0003 : Printed Circuit Board Layout and Probing GaN Design Resources The complete technical library of GaN design tools can be found at transphormusa.com/design: Reference designs Evaluation kits Application notes Design guides Simulation models Technical papers and presentations A ll data sheet.com
November 22, 2017 transphormusa.com tph3205wsbqa.1 12 TPH3205WSBQA Mechanical 3 Lead TO-247 Package A ll data sheet.com
November 22, 2017 transphormusa.com tph3205wsbqa.1 13 TPH3205WSBQA
Revision History
Version Date Change(s) 0 3/1/2017 QA version denotes AEC-Q101 qualification 1 11/1/2017 Updated effective on-resistance symbol to RDS(on)eff to adhere to new JEDEC standards; Added common topology max power recommendations (pg 1), switching current values (pg 2), Circuit Implementation (pg 3), QOSS value (pg 4), Figures 7 & 8 (pg 6) A ll data sheet.com