TP65H480G4JSG TRANSPHORM | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 12

Technical content

Features

  • Gen IV technology
  • JEDEC-qualified GaN technology
  • Dynamic RDS(on)eff production tested
  • Robust design, defined by — Wide gate safety margin — Transient over-voltage capability
  • Very low QRR
  • Reduced crossover loss
  • RoHS compliant and Halogen-free packaging Benefits
  • Achieves increased efficiency in both hard- and soft- switched circuits — Increased power density — Reduced system size and weight — Overall lower system cost
  • Easy to drive with commonly-used gate drivers
  • GSD pin layout improves high speed design

Applications

  • Consumer
  • Power adapters
  • Low power SMPS
  • Lighting

Description

The TP65H480G4JSG 650V, 480mΩ Gallium Nitride (GaN) FET is a normally-off device using Transphorm’s Gen IV platform. It combines a state-of-the-art high voltage GaN HEMT with a low voltage silicon MOSFET to offer superior reliability and performance. The Gen IV SuperGaN® platform uses advanced epi and patented design technologies to simplify manufacturability while improving efficiency over silicon via lower gate charge, output capacitance, crossover loss, and reverse recovery charge. Related Literature

  • AN0003: Printed Circuit Board Layout and Probing
  • AN0007: Recommendations for Vapor Phase Reflow
  • AN0009: Recommended External Circuitry for GaN FETs
  • AN0012: PQFN Tape and Reel Information Product Series and Ordering Information Part Number Package Package Configuration TP65H480G4JSG-TR* 5x6 PQFN Source S G D TP65H480G4JSG PQFN (bottom view) Cascode Device Structure Cascode Schematic Symbol * “-TR” suffix refers to tape and reel. Refer to AN0012 for details. Pin 1

September 12, 2023 transphormusa.com tp65h480g4lsg.3v3 2 TP65H480G4JSG Absolute Maximum Ratings (Tc=25°C unless otherwise stated.) Symbol Parameter Limit Value Unit VDSS Drain to source voltage (TJ = -55°C to 150°C) 650 V VDSS (TR) Transient drain to source voltage a 800 VGSS Gate to source voltage ±18 PD Maximum power dissipation @TC=25°C 13.2 W ID Continuous drain current @TC=25°C b 3.6 A Continuous drain current @TC=100°C b 2.3 A IDM Pulsed drain current (pulse width: 10µs) 17 A TC Operating temperature Case -55 to +150 °C TJ Junction -55 to +150 °C TS Storage temperature -55 to +150 °C TSOLD Reflow soldering temperature c 260 °C Notes: a. In off-state, spike duration < 30s, non-repetitive b. For increased stability at high current operation, see Circuit Implementation on page 3 c. Reflow MSL3 Thermal Resistance Symbol Parameter Maximum Unit RΘJC Junction-to-case 9.5 °C/W RΘJA Junction-to-ambient d 50 °C/W Notes: d. Device on one layer epoxy PCB for drain connection (vertical and without air stream cooling, with 6cm2 copper area and 70µm thickness) VDSS(TR) VDSS(BL)

September 12, 2023 transphormusa.com tp65h480g4lsg.3v3 3 TP65H480G4JSG Gate Ferrite Bead (FB1) Required DC Link RC Snubber (RCDCL) b 240Ω @ 100MHz 4.7-10nF + 5Ω Notes: a. For bridge topologies only. RG could be much smaller in single ended topologies. b. RCDCL should be placed as close as possible to the drain pin. Circuit Implementation Recommended gate drive: (0V, 8V) with RG(tot) = 30 Ωa Simplified Half-bridge Schematic VBUSDC Bus RG RG Driver FB FBDriver RCDCL VO Recommended gate drive: (0V, 12V) with RG(ON) = 100 to 300 Ω RG(OFF) = 0 to 15 Ω Simplified Single Ended Schematic

September 12, 2023 transphormusa.com tp65h480g4lsg.3v3 4 TP65H480G4JSG Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Forward Device Characteristics VDSS(BL) Maximum drain-source voltage 650 — — V VGS=0V VGS(th) Gate threshold voltage 1.6 2.1 2.8 V VDS=VGS, ID=0.5mA ΔVGS(th)/TJ Gate threshold voltage temperature coefficient — -5.8 — mV/°C RDS(on)eff Drain-source on-resistance a — 480 560 mΩ VGS=8V, ID=3.4A — 1000 — VGS=8V, ID=3.4A, TJ=150°C IDSS Drain-to-source leakage current — 1 10 µA VDS=650V, VGS=0V — 5 — VDS=650V, VGS=0V, TJ=150°C IGSS Gate-to-source forward leakage current — — 100 nA VGS=18V Gate-to-source reverse leakage current — — -100 VGS=-18V CISS Input capacitance — 760 — pF VGS=0V, VDS=400V, f=1MHz COSS Output capacitance — 9 — CRSS Reverse transfer capacitance — 1.5 — CO(er) Output capacitance, energy related b — 13 — pF VGS=0V, VDS=0V to 400V CO(tr) Output capacitance, time related c — 29 — QG Total gate charge — 9 — nC VDS=400V, VGS=0V to 8V, ID=3.4A QGS Gate-source charge — 2.1 — QGD Gate-drain charge — 2.1 — QOSS Output charge — 13.5 — nC VGS=0V, VDS=0V to 400V tD(on) Turn-on delay — 16.6 — ns VDS=400V, VGS=0V to 8V, ID=3.4A, RG=30Ω, ZFB=240Ω at 100MHz (See Figure 14) tR Rise time — 3.5 — tD(off) Turn-off delay — 53.2 — tF Fall time — 7.6 — Notes: a. Dynamic RDS(on) value; see Figures 18 and 19 for conditions b. Equivalent capacitance to give same stored energy from 0V to 400V c. Equivalent capacitance to give same charging time from 0V to 400V

September 12, 2023 transphormusa.com tp65h480g4lsg.3v3 5 TP65H480G4JSG Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Reverse Device Characteristics IS Reverse current — — 2.3 A VGS=0V, TC=100°C, ≤25% duty cycle VSD Reverse voltage a — 1.3 — V VGS=0V, IS=1.15A — 1.8 — VGS=0V, IS=2.3A tRR Reverse recovery time — 14.5 — ns IS=3.4A, VDD=400V, di/dt=1000A/us QRR Reverse recovery charge — 14 — nC Notes: a. Includes dynamic RDS(on) effect

Figure 13. Safe Operating Area TC=25°C

September 12, 2023 transphormusa.com tp65h480g4lsg.3v3 11 TP65H480G4JSG Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switches requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The table below provides some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Minimize lead length of TO-220 and TO-247 package when mounting to the PCB Use long traces in drive circuit, long lead length of the devices Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points Use differential mode probe or probe ground clip with long wire See AN0003: Printed Circuit Board Layout and Probing GaN Design Resources The complete technical library of GaN design tools can be found at transphormusa.com/design:

  • Evaluation kits
  • Application notes
  • Design guides
  • Simulation models
  • Technical papers and presentations

September 12, 2023 transphormusa.com tp65h480g4lsg.3v3 12 TP65H480G4JSG Mechanical 5x6 PQFN Package