TP65H035G4WS TRANSPHORM | Alldatasheet

Document overview

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Technical content

Features

 JEDEC qualified GaN technology  Dynamic RDS(on)eff production tested  Robust design, defined by — Wide gate safety margin — Transient over-voltage capability  Enhanced inrush current capability  Very low QRR  Reduced crossover loss Benefits  Enables AC-DC bridgeless totem-pole PFC designs — Increased power density — Reduced system size and weight — Overall lower system cost  Achieves increased efficiency in both hard- and soft- switched circuits  Easy to drive with commonly-used gate drivers  GSD pin layout improves high speed design

Applications

 Datacom  Broad industrial  PV inverter  Servo motor

Description

The TP65H035G4WS 650V, 35 mΩ gallium nitride (GaN) FET is a normally-off device using Transphorm’s Gen IV platform. It combines a state-of-the-art high voltage GaN HEMT with a low voltage silicon MOSFET to offer superior reliability and performance. The Gen IV SuperGaN™ platform uses advanced epi and patented design technologies to simplify manufacturability while improving efficiency over silicon via lower gate charge, output capacitance, crossover loss, and reverse recovery charge. Related Literature  AN0009: Recommended External Circuitry for GaN FETs  AN0003: Printed Circuit Board Layout and Probing S G D S TP65H035G4WS TO-247 (top view)

Ordering Information

Part Number Package Package Configuration TP65H035G4WS 3 lead TO-247 Source Key Specifications VDSS (V) 650 V(TR)DSS (V) 725 RDS(on)eff (mΩ) max* 41 QRR (nC) typ 150 QG (nC) typ 22 * Dynamic on-resistance; ; see Figures 18 and 19 Cascode Device Structure Cascode Schematic Symbol

Apr. 28, 2020 transphormusa.com tp65h035G4ws.1 2 TP65H035G4WS Thermal Resistance Symbol Parameter Typical Unit RΘJC Junction-to-case 0.8 °C/W RΘJA Junction-to-ambient 40 °C/W Absolute Maximum Ratings (Tc=25°C unless otherwise stated.) Symbol Parameter Limit Value Unit VDSS Drain to source voltage (TJ = -55°C to 150°C) 650 V V(TR)DSS Transient drain to source voltage a 725 VGSS Gate to source voltage ±20 PD Maximum power dissipation @TC=25°C 156 W ID Continuous drain current @TC=25°C b 46.5 A Continuous drain current @TC=100°C b 29.5 A IDM Pulsed drain current (pulse width: 10µs) 240 A TC Operating temperature Case -55 to +150 °C TJ Junction -55 to +150 °C TS Storage temperature -55 to +150 °C TSOLD Soldering peak temperature e 260 °C Notes: a. In off-state, spike duty cycle D<0.01, spike duration <1µs b. For increased stability at high current operation, see Circuit Implementation on page 3 c. Continuous switching operation d. ≤300 pulses per second for a total duration ≤20 minutes e. For 10 sec., 1.6mm from the case

Apr. 28, 2020 transphormusa.com tp65h035G4ws.1 3 TP65H035G4WS Circuit Implementation Recommended gate drive: (0V, 12V) with RG= 30Ω Simplified Half-bridge Schematic Required DC Link RC Snubber (RCDCL) a Recommended Switching Node RC Snubber (RCSN) b, c Gate Ferrite Bead (FB1) [4.7nF + 5Ω] x 2 Not necessary b 200 — 270Ω at 100MHz Notes: a. RCDCL should be placed as close as possible to the drain pin b. RCSN is needed only if RG is smaller than recommendations

Apr. 28, 2020 transphormusa.com tp65h035G4ws.1 4 TP65H035G4WS Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Forward Device Characteristics V(BL)DSS Drain-source voltage 650 — — V VGS=0V VGS(th) Gate threshold voltage 3.3 4 4.8 V VDS=VGS, ID=1mA ΔVGS(th)/TJ Gate threshold voltage temperature co- efficient — -6.5 — mV/°C RDS(on)eff Drain-source on-resistance a — 35 41 mΩ VGS=10V, ID=30A — 72 — VGS=10V, ID=30A, TJ=150°C IDSS Drain-to-source leakage current — 3 30 µA VDS=650V, VGS=0V — 20 — VDS=650V, VGS=0V, TJ=150°C IGSS Gate-to-source forward leakage current — — 400 nA VGS=20V Gate-to-source reverse leakage current — — -400 VGS=-20V CISS Input capacitance — 1500 — pF VGS=0V, VDS=400V, f=1MHz COSS Output capacitance — 147 — CRSS Reverse transfer capacitance — 5 — CO(er) Output capacitance, energy related b — 220 — pF VGS=0V, VDS=0V to 400V CO(tr) Output capacitance, time related c — 380 — QG Total gate charge — 22 — nC VDS=400V, VGS=0V to 10V, ID=32A QGS Gate-source charge — 8.4 — QGD Gate-drain charge — 6.6 — QOSS Output charge — 150 — nC VGS=0V, VDS=0V to 400V tD(on) Turn-on delay — 60 — ns VDS=400V, VGS=0V to 12V, RG=30, ID=32A, ZFB=240Ω at 100MHz (See Figure 14) tR Rise time — 10 — tD(off) Turn-off delay — 94 — tF Fall time — 10 — Notes: a. Dynamic on-resistance; see Figures 19 and 20 for test circuit and conditions b. Equivalent capacitance to give same stored energy as VDS rises from 0V to 400V c. Equivalent capacitance to give same charging time as VDS rises from 0V to 400V

Apr. 28, 2020 transphormusa.com tp65h035G4ws.1 5 TP65H035G4WS Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Reverse Device Characteristics IS Reverse current — — 29.5 A VGS=0V, TC=100°C ≤25% duty cycle VSD Reverse voltage a — 1.8 — V VGS=0V, IS=32A — 1.3 — VGS=0V, IS=16A tRR Reverse recovery time — 59 — ns IS=32A, VDD=400V, di/dt=1000A/s QRR Reverse recovery charge — 150 — nC (di/dt)RM Reverse diode di/dt b — — 3200 A/µs Circuit implementation and parameters on page 3 Notes: a. Includes dynamic RDS(on) effect b. Reverse conduction di/dt will not exceed this max value with recommended RG.

Figure 13. Safe Operating Area TC=25°C

Apr. 28, 2020 transphormusa.com tp65h035G4ws.1 11 TP65H035G4WS Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switche s requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The table below provides some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Minimize lead length of TO-220 and TO-247 package when mounting to the PCB Use long traces in drive circuit, long lead length of the devices Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points Use differential mode probe or probe ground clip with long wire See AN0003: Printed Circuit Board Layout and Probing GaN Design Resources The complete technical library of GaN design tools can be found at transphormusa.com/design:  Evaluation kits  Application notes  Design guides  Simulation models  Technical papers and presentations

Apr. 28, 2020 transphormusa.com tp65h035G4ws.1 12 TP65H035G4WS Mechanical 3 Lead TO-247 Package

Apr. 28, 2020 transphormusa.com tp65h035G4ws.1 13 TP65H035G4WS

Revision History

Version Date Change(s) 0 1/17/2020 Preliminary Datasheet 1 3/28/2020 Completed datasheet 1.1 4/23/2020 Corrected Qg and Qg Curve 1.2 4/29/2020 Updated Qoss Curve