TP90H050WS TRANSPHORM | Alldatasheet

Document overview

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Technical content

Features

  • JEDEC qualified GaN technology
  • Dynamic RDS(on)eff production tested
  • Robust design, defined by — Intrinsic lifetime tests — Wide gate safety margin — Transient over-voltage capability
  • Very low QRR
  • Reduced crossover loss
  • RoHS compliant and Halogen-free packaging Benefits
  • Enables AC-DC bridgeless totem-pole PFC designs — Increased power density — Reduced system size and weight — Overall lower system cost
  • Achieves increased efficiency in both hard- and soft- switched circuits
  • Easy to drive with commonly-used gate drivers
  • GSD pin layout improves high speed design

Applications

  • Datacom
  • Broad industrial
  • PV inverter
  • Servo motor

Description

The TP90H050WS 900V, 50mΩ Gallium Nitride (GaN) FET is a normally-off device. It combines state-of-the-art high voltage GaN HEMT and low voltage silicon MOSFET technologies—offering superior reliability and performance. Transphorm GaN offers improved efficiency over silicon, through lower gate charge, lower crossover loss, and smaller reverse recovery charge. Related Literature

  • AN0009: Recommended External Circuitry for GaN FETs
  • AN0003: Printed Circuit Board Layout and Probing
  • AN0010: Paralleling GaN FETs S G D S TP90H050WS TO-247 (top view)

Ordering Information

Part Number Package Package Configuration TP90H050WS 3 lead TO-247 Source Cascode Device Structure Cascode Schematic Symbol Key Specifications VDS (V) 900 V(TR)DSS (V) max 1000 RDS(on)eff (mΩ) max* 63 QRR (nC) typ 156 QG (nC) typ 15 * Reflects both static and dynamic on-resistance; see Figures 18 and 19

July 7, 2020 transphormusa.com tp90h050ws.1 2 TP90H050WS Absolute Maximum Ratings (TJ=25°C unless otherwise stated. All recommended current levels (IDM) are based on adequate heat sinking, ensuring TJ=150°C ) Symbol Parameter Limit Value Unit ID Continuous drain current @TC=25°C a 34 A Continuous drain current @TC=100°C a 22 A IDM Pulsed drain current (pulse width: 10µs) 150 A di/dtRDMC Reverse diode di/dt, repetitive b 1600 A/µs IRDMC1 Reverse diode switching current, repetitive (dc) c 24 A IRDMC2 Reverse diode switching current, repetitive (ac) c 28 A di/dtRDMT Reverse diode di/dt, transient d 3000 A/µs IRDMT Reverse diode switching current, transient 36 A V(TR)DSS Transient drain to source voltage e 1000 V VGSS Gate to source voltage ±20 V PD Maximum power dissipation @TC=25°C 119 W TC Operating temperature Case -55 to +150 °C TJ Junction -55 to +150 °C TS Storage temperature -55 to +150 °C TSOLD Soldering peak temperature f 260 °C - Mounting Torque 80 N cm Notes: a. For increased stability at high current operation, see Circuit Implementation on page 3 b. Continuous switching operation c. Definitions: dc = dc to dc converter topologies; ac = inverter and PFC topologies, 50-60Hz line frequency d. ≤300 pulses in 1 second e. In off-state, spike duty cycle D<0.01, spike duration <1µs f. For 10 sec., 1.6mm from the case Thermal Resistance Symbol Parameter Typical Unit RΘJC Junction-to-case 1.05 °C/W RΘJA Junction-to-ambient 40 °C/W

July 7, 2020 transphormusa.com tp90h050ws.1 3 TP90H050WS Circuit Implementation Recommended gate drive: (0V, 12-14V) with RG(tot) = 22-30Ω, where RG(tot) = RG + RDRIVER Simplified Half-bridge Schematic Efficiency vs Output Power Required DC Link RC Snubber (RCDCL) a Recommended Switching Node RC Snubber (RCSN) b [10nF + 8Ω] x 2 100pF + 10Ω Notes: a. RCDCL should be placed as close as possible to the drain pin b. A switching node RC snubber (C, R) is recommended for high switching currents (>70% of IRDMC1 or IRDMC2)

July 7, 2020 transphormusa.com tp90h050ws.1 4 TP90H050WS Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Forward Device Characteristics V(BL)DSS Maximum drain-source voltage 900 — — V VGS=0V VGS(th) Gate threshold voltage 3.4 3.9 4.4 V VDS=VGS, ID=0.7mA ΔVGS(th)/TJ Gate threshold voltage temperature coefficient — -6.5 — mV/°C RDS(on)eff Drain-source on-resistance a — 50 63 mΩ VGS=10V, ID=22A — 105 — VGS=10V, ID=22A, TJ=150°C IDSS Drain-to-source leakage current — 4 40 µA VDS=900V, VGS=0V — 15 — VDS=900V, VGS=0V, TJ=150°C IGSS Gate-to-source forward leakage current — — 100 nA VGS=20V Gate-to-source reverse leakage current — — -100 VGS=-20V CISS Input capacitance — 1000 — pF VGS=0V, VDS=600V, f=1MHz COSS Output capacitance — 115 — CRSS Reverse transfer capacitance — 3.5 — CO(er) Output capacitance, energy related b — 153 — pF VGS=0V, VDS=0V to 600V CO(tr) Output capacitance, time related c — 260 — QG Total gate charge — 15 — nC VDS=600V, VGS=10V, ID=22A QGS Gate-source charge — 5 — QGD Gate-drain charge — 4.7 — QOSS Output charge — 155 — nC VGS=0V, VDS=0V to 600V tD(on) Turn-on delay — 48 — ns VDS=600V, VGS=10V, ID=22A RG=25Ω, 4A driver tR Rise time — 12 — tD(off) Turn-off delay — 70 — tF Fall time — 12 — Reverse Device Characteristics IS Reverse current — — 22 A VGS=0V, TC=100°C, ≤25% duty cycle VSD Reverse voltage a — 2.2 2.6 V VGS=0V, IS=22A — 1.6 1.9 VGS=0V, IS=11A tRR Reverse recovery time — 53 — ns IS=22A, VDD=600V, di/dt=1000A/µs QRR Reverse recovery charge — 156 — nC Notes: a. Reflects both static and dynamic on-resistance; dynamic on-resistance test setup and waveform; see Figures 14 and 15 for conditions b. Equivalent capacitance to give same stored energy from 0V to 600V c. Equivalent capacitance to give same charging time from 0V to 600V

Figure 13. Safe Operating Area TC=25°C

July 7, 2020 transphormusa.com tp90h050ws.1 10 TP90H050WS Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switche s requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The table below provides some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Minimize lead length of TO-220 and TO-247 package when mounting to the PCB Use long traces in drive circuit, long lead length of the devices Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points Use differential mode probe or probe ground clip with long wire See AN0003: Printed Circuit Board Layout and Probing GaN Design Resources The complete technical library of GaN design tools can be found at transphormusa.com/design:

  • Evaluation kits
  • Application notes
  • Design guides
  • Simulation models
  • Technical papers and presentations

July 7, 2020 transphormusa.com tp90h050ws.1 11 TP90H050WS Mechanical 3 Lead TO-247 Package

July 7, 2020 transphormusa.com tp90h050ws.1 12 TP90H050WS

Revision History

Version Date Change(s) 0.1 10/27/2017 Release preliminary datasheet 0.2 11/20/2018 preliminary datasheet Add max mouting torque 0.3 02/27/2020 preliminary datasheet Updated Qrr Coss Qoss and Qg 1.1 07/07/2020 Datasheet Completed