TP65H070G4QS TRANSPHORM | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 13

Technical content

Features

  • JEDEC qualified GaN technology
  • Dynamic RDS(on)eff production tested
  • Robust design, defined by — Wide gate safety margin — Transient over-voltage capability
  • Enhanced inrush current capability
  • Very low QRR
  • Reduced crossover loss Benefits
  • Enables AC-DC bridgeless totem-pole PFC designs — Increased power density — Reduced system size and weight — Overall lower system cost
  • Achieves increased efficiency in both hard- and soft- switched circuits
  • Easy to drive with commonly-used gate drivers
  • GSD pin layout improves high speed design

Applications

  • Datacom
  • Broad industrial
  • PV inverter
  • Servo motor TP65H070G4QS TOLL (bottom view) * “-TR” suffix refers to tape and reel. Refer to AN0012 for details. Preliminary

August 17, 2023 transphormusa.com tp65h070g4qs.0v2 2 TP65H070G4QS — Preliminary Thermal Resistance Symbol Parameter Typical Unit RΘJC Junction-to-case 1 °C/W RΘJA Junction-to-ambient 62 °C/W Absolute Maximum Ratings (Tc=25°C unless otherwise stated.) Symbol Parameter Limit Value Unit VDSS Drain to source voltage (TJ = -55°C to 150°C) 650 V VDSS(TR) Transient drain to source voltage (a) 800 VGSS Gate to source voltage ±20 PD Maximum power dissipation @TC=25°C 96 W ID Continuous drain current @TC=25°C (b) 29 A Continuous drain current @TC=100°C (b) 18.4 A IDM Pulsed drain current (pulse width: 10µs) 120 A TC Operating temperature Case -55 to +150 °C TJ Junction -55 to +150 °C TS Storage temperature -55 to +150 °C TSOLD Soldering peak temperature (c) 260 °C Notes: a. In off-state, spike duty cycle D<0.01, spike duration <30µs, non repetitive b. For increased stability at high current operation, see Circuit Implementation on page 3 c. For 10 sec., 1.6mm from the case Preliminary

August 17, 2023 transphormusa.com tp65h070g4qs.0v2 3 TP65H070G4QS — Preliminary Circuit Implementation (d) Recommended gate drive: (0V, 12V) with RG= 50Ω(d) Simplified Half-bridge Schematic ( See also on Figure 15 ) Required DC Link RC Snubber (RCDCL) (e) Recommended Switching Node RC Snubber (RCSN) (f) Gate Ferrite Bead (FB1) 10nF + 5Ω Not necessary (f) 200 — 300Ω at 100MHz Notes: d. For bridge topologies only. RG can be smaller in single ended topologies. RGS: typically 10 kΩ e. RCDCL should be placed as close as possible to the drain pin f. RCSN (200pF + 5Ω) is needed only if RG is smaller than recommendations For additional gate driver options/configurations, please see Layout Recommendations Gate Loop:

  • Gate Driver: SiLab Si823x/Si827x
  • Keep gate loop compact
  • Minimize coupling with power loop Power loop: ( For reference see page 12 )
  • Minimize power loop path inductance
  • Minimize switching node coupling with high and low power plane
  • Add DC bus snubber to reduce to voltage ringing
  • Add Switching node snubber for high current operation Preliminary

August 17, 2023 transphormusa.com tp65h070g4qs.0v2 4 TP65H070G4QS — Preliminary Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Forward Device Characteristics VDSS(BL) Drain-source voltage 650 — — V VGS=0V VGS(th) Gate threshold voltage 3.3 4 4.8 V VDS=VGS, ID=0.7mA ΔVGS(th)/TJ Gate threshold voltage temperature coefficient — -6.2 — mV/°C RDS(on)eff Drain-source on-resistance (g) — 72 85 mΩ VGS=10V, ID=16A — 148 — VGS=10V, ID=16A, TJ=150°C IDSS Drain-to-source leakage current — 3 30 µA VDS=650V, VGS=0V — 12 — VDS=650V, VGS=0V, TJ=150°C IGSS Gate-to-source forward leakage current — — 100 nA VGS=20V — — -100 VGS=-20V CISS Input capacitance — 600 — pF VGS=0V, VDS=400V, f=1MHz COSS Output capacitance — 74 — CRSS Reverse transfer capacitance — 2 — CO(er) Output capacitance, energy related (h) — 109 — pF VGS=0V, VDS=0V to 400V CO(tr) Output capacitance, time related (i) — 200 — QG Total gate charge — 8.4 — nC VDS=400V, VGS=0V to 10V, ID=16A QGS Gate-source charge — 3.3 — QGD Gate-drain charge — 2.3 — QOSS Output charge — 78 — nC VGS=0V, VDS=0V to 400V tD(on) Turn-on delay — 27 — ns VDS=400V, VGS=0V to 10V, ID=22A, Rg=45Ω, ZFB=240Ω at 100MHz (See Figure 14) tR Rise time — 9 — tD(off) Turn-off delay — 71 — tF Fall time — 6.5 — Eoff Turn off Energy — TBD — VDS=400V, VGS=0V to 12V, RG=30, ID=16A, ZFB=180Ω at 100MHz Eon Turn on Energy — TBD — Notes: g. Dynamic on-resistance; see Figures 17 and 18 for test circuit and conditions h. Equivalent capacitance to give same stored energy as VDS rises from 0V to 400V i. Equivalent capacitance to give same charging time as VDS rises from 0V to 400V Preliminary

August 17, 2023 transphormusa.com tp65h070g4qs.0v2 5 TP65H070G4QS — Preliminary Electrical Parameters (TJ=25°C unless otherwise stated) Symbol Parameter Min Typ Max Unit Test Conditions Reverse Device Characteristics IS Reverse current — — 16 A VGS=0V, TC=100°C, ≤25% duty cycle VSD Reverse voltage (j) — 2.2 2.6 V VGS=0V, IS=16A — 1.6 1.9 VGS=0V, IS=8A tRR Reverse recovery time — 34 — ns IS=16A, VDD=400V di/dt = 1000A/us QRR Reverse recovery charge — 120 — nC (di/dt)RM Reverse diode di/dt (k) — — 1900 A/µs Circuit implementation and parameters on page 3 Notes: j. Includes dynamic RDS(on) effect k. Reverse conduction di/dt will not exceed this max value with recommended RG. Preliminary

Figure 13. Safe Operating Area TC=25°C Figure 14. Inductive Switching Loss TC=25°C

August 17, 2023 transphormusa.com tp65h070g4qs.0v2 11 TP65H070G4QS — Preliminary Design Considerations The fast switching of GaN devices reduces current-voltage crossover losses and enables high frequency operation while simultaneously achieving high efficiency. However, taking full advantage of the fast switching characteristics of GaN switche s requires adherence to specific PCB layout guidelines and probing techniques. Before evaluating Transphorm GaN devices, see application note Printed Circuit Board Layout and Probing for GaN Power Switches. The table below provides some practical rules that should be followed during the evaluation. When Evaluating Transphorm GaN Devices: DO DO NOT Minimize circuit inductance by keeping traces short, both in the drive and power loop Twist the pins of TO-220 or TO-247 to accommodate GDS board layout Minimize lead length of TO-220 and TO-247 package when mounting to the PCB Use long traces in drive circuit, long lead length of the devices Use shortest sense loop for probing; attach the probe and its ground connection directly to the test points Use differential mode probe or probe ground clip with long wire See AN0003: Printed Circuit Board Layout and Probing GaN Design Resources The complete technical library of GaN design tools can be found at transphormusa.com/design:

  • Evaluation kits
  • Application notes
  • Design guides
  • Simulation models
  • Technical papers and presentations Preliminary

August 17, 2023 transphormusa.com tp65h070g4qs.0v2 12 TP65H070G4QS — Preliminary Preliminary

August 17, 2023 transphormusa.com tp65h070g4qs.0v2 13 TP65H070G4QS — Preliminary Half-bridge Reference Schematic and PCB Layout Preliminary